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kendryte-freertos-sdk
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Refactory build system

pull/18/merge
Guo Hui 2018-10-10 17:02:27 +08:00
parent c81e2e1a98
commit 27f7509bd4
38 changed files with 423 additions and 498 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
cmake/executable.cmake
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@ -23,7 +23,7 @@ set_target_properties(${PROJECT_NAME} PROPERTIES LINKER_LANGUAGE C)
target_link_libraries(${PROJECT_NAME}
-Wl,--start-group
m kendryte
m freertos bsp
-Wl,--end-group
)

10
cmake/macros.internal.cmake
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@ -1,12 +1,4 @@
# Add lib headers
macro(header_directories parent)
file(GLOB_RECURSE newList ${parent}/*.h)
set(dir_list "")
foreach (file_path ${newList})
get_filename_component(dir_path ${file_path} DIRECTORY)
set(dir_list ${dir_list} ${dir_path})
endforeach ()
list(REMOVE_DUPLICATES dir_list)
include_directories(${dir_list})
include_directories(${parent})
endmacro()

49
lib/CMakeLists.txt
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@ -1,45 +1,6 @@
#project(kendryte_drivers)
#project(kendryte)
INCLUDE_DIRECTORIES(${CMAKE_CURRENT_LIST_DIR}/arch/include ${CMAKE_CURRENT_LIST_DIR}/utils/include)
# create driver library
FILE(GLOB_RECURSE LIB_SRC_NOASM
"${CMAKE_CURRENT_LIST_DIR}/*.h"
"${CMAKE_CURRENT_LIST_DIR}/*.hpp"
"${CMAKE_CURRENT_LIST_DIR}/*.cpp"
"${CMAKE_CURRENT_LIST_DIR}/*.c"
)
FILE(GLOB_RECURSE ASSEMBLY_FILES
"${CMAKE_CURRENT_LIST_DIR}/*.s"
"${CMAKE_CURRENT_LIST_DIR}/*.S"
)
SET(LIB_SRC ${LIB_SRC_NOASM} ${ASSEMBLY_FILES})
include_directories(${CMAKE_CURRENT_LIST_DIR}/drivers/include ${CMAKE_CURRENT_LIST_DIR}/bsp/include)
#
#HEADER_DIRECTORIES(LIB_HEADERS)
#
#INCLUDE_DIRECTORIES(${LIB_HEADERS})
SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C)
SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64")
#MESSAGE("CMAKE_C_FLAGS: ${CMAKE_C_FLAGS}")
ADD_LIBRARY(kendryte STATIC ${LIB_SRC})
SET_TARGET_PROPERTIES(kendryte PROPERTIES LINKER_LANGUAGE C)
# find headers files to INSTALL
file(GLOB_RECURSE LIB_HEADERS
"../lib/*.h"
"../lib/*.hpp"
)
set_target_properties(kendryte PROPERTIES PUBLIC_HEADER "${LIB_HEADERS}")
# copy .a file and headers
install(TARGETS kendryte
EXPORT kendryte
ARCHIVE
DESTINATION ${CMAKE_BINARY_DIR}/archive
PUBLIC_HEADER DESTINATION ${CMAKE_BINARY_DIR}/archive/include
)
ADD_SUBDIRECTORY(drivers)
ADD_SUBDIRECTORY(freertos)
ADD_SUBDIRECTORY(bsp)

0
lib/bsp/include/atomic.h → lib/arch/include/atomic.h
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0
lib/bsp/include/encoding.h → lib/arch/include/encoding.h
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276
lib/arch/include/platform.h Normal file
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@ -0,0 +1,276 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _BSP_PLATFORM_H
#define _BSP_PLATFORM_H
/* clang-format off */
/* Register base address */
/* Under Coreplex */
#define CLINT_BASE_ADDR (0x02000000)
#define PLIC_BASE_ADDR (0x0C000000)
/* Under TileLink */
#define UARTHS_BASE_ADDR (0x38000000)
#define GPIOHS_BASE_ADDR (0x38001000)
/* Under AXI 64 bit */
#define RAM_BASE_ADDR (0x80000000)
#define RAM_SIZE (6 * 1024 * 1024)
#define IO_BASE_ADDR (0x40000000)
#define IO_SIZE (6 * 1024 * 1024)
#define AI_RAM_BASE_ADDR (0x80600000)
#define AI_RAM_SIZE (2 * 1024 * 1024)
#define AI_IO_BASE_ADDR (0x40600000)
#define AI_IO_SIZE (2 * 1024 * 1024)
#define AI_BASE_ADDR (0x40800000)
#define AI_SIZE (12 * 1024 * 1024)
#define FFT_BASE_ADDR (0x42000000)
#define FFT_SIZE (4 * 1024 * 1024)
#define ROM_BASE_ADDR (0x88000000)
#define ROM_SIZE (128 * 1024)
/* Under AHB 32 bit */
#define DMAC_BASE_ADDR (0x50000000)
/* Under APB1 32 bit */
#define GPIO_BASE_ADDR (0x50200000)
#define UART1_BASE_ADDR (0x50210000)
#define UART2_BASE_ADDR (0x50220000)
#define UART3_BASE_ADDR (0x50230000)
#define SPI_SLAVE_BASE_ADDR (0x50240000)
#define I2S0_BASE_ADDR (0x50250000)
#define I2S1_BASE_ADDR (0x50260000)
#define I2S2_BASE_ADDR (0x50270000)
#define I2C0_BASE_ADDR (0x50280000)
#define I2C1_BASE_ADDR (0x50290000)
#define I2C2_BASE_ADDR (0x502A0000)
#define FPIOA_BASE_ADDR (0x502B0000)
#define SHA256_BASE_ADDR (0x502C0000)
#define TIMER0_BASE_ADDR (0x502D0000)
#define TIMER1_BASE_ADDR (0x502E0000)
#define TIMER2_BASE_ADDR (0x502F0000)
/* Under APB2 32 bit */
#define WDT0_BASE_ADDR (0x50400000)
#define WDT1_BASE_ADDR (0x50410000)
#define OTP_BASE_ADDR (0x50420000)
#define DVP_BASE_ADDR (0x50430000)
#define SYSCTL_BASE_ADDR (0x50440000)
#define AES_BASE_ADDR (0x50450000)
#define RTC_BASE_ADDR (0x50460000)
/* Under APB3 32 bit */
#define SPI0_BASE_ADDR (0x52000000)
#define SPI1_BASE_ADDR (0x53000000)
#define SPI3_BASE_ADDR (0x54000000)
/* clang-format on */
/**
* @brief PLIC External Interrupt Numbers
*
* @note PLIC interrupt sources
*
* | Source | Name | Description |
* |--------|--------------------------|------------------------------------|
* | 0 | IRQN_NO_INTERRUPT | The non-existent interrupt |
* | 1 | IRQN_SPI0_INTERRUPT | SPI0 interrupt |
* | 2 | IRQN_SPI1_INTERRUPT | SPI1 interrupt |
* | 3 | IRQN_SPI_SLAVE_INTERRUPT | SPI_SLAVE interrupt |
* | 4 | IRQN_SPI3_INTERRUPT | SPI3 interrupt |
* | 5 | IRQN_I2S0_INTERRUPT | I2S0 interrupt |
* | 6 | IRQN_I2S1_INTERRUPT | I2S1 interrupt |
* | 7 | IRQN_I2S2_INTERRUPT | I2S2 interrupt |
* | 8 | IRQN_I2C0_INTERRUPT | I2C0 interrupt |
* | 9 | IRQN_I2C1_INTERRUPT | I2C1 interrupt |
* | 10 | IRQN_I2C2_INTERRUPT | I2C2 interrupt |
* | 11 | IRQN_UART1_INTERRUPT | UART1 interrupt |
* | 12 | IRQN_UART2_INTERRUPT | UART2 interrupt |
* | 13 | IRQN_UART3_INTERRUPT | UART3 interrupt |
* | 14 | IRQN_TIMER0A_INTERRUPT | TIMER0 channel 0 or 1 interrupt |
* | 15 | IRQN_TIMER0B_INTERRUPT | TIMER0 channel 2 or 3 interrupt |
* | 16 | IRQN_TIMER1A_INTERRUPT | TIMER1 channel 0 or 1 interrupt |
* | 17 | IRQN_TIMER1B_INTERRUPT | TIMER1 channel 2 or 3 interrupt |
* | 18 | IRQN_TIMER2A_INTERRUPT | TIMER2 channel 0 or 1 interrupt |
* | 19 | IRQN_TIMER2B_INTERRUPT | TIMER2 channel 2 or 3 interrupt |
* | 20 | IRQN_RTC_INTERRUPT | RTC tick and alarm interrupt |
* | 21 | IRQN_WDT0_INTERRUPT | Watching dog timer0 interrupt |
* | 22 | IRQN_WDT1_INTERRUPT | Watching dog timer1 interrupt |
* | 23 | IRQN_APB_GPIO_INTERRUPT | APB GPIO interrupt |
* | 24 | IRQN_DVP_INTERRUPT | Digital video port interrupt |
* | 25 | IRQN_AI_INTERRUPT | AI accelerator interrupt |
* | 26 | IRQN_FFT_INTERRUPT | FFT accelerator interrupt |
* | 27 | IRQN_DMA0_INTERRUPT | DMA channel0 interrupt |
* | 28 | IRQN_DMA1_INTERRUPT | DMA channel1 interrupt |
* | 29 | IRQN_DMA2_INTERRUPT | DMA channel2 interrupt |
* | 30 | IRQN_DMA3_INTERRUPT | DMA channel3 interrupt |
* | 31 | IRQN_DMA4_INTERRUPT | DMA channel4 interrupt |
* | 32 | IRQN_DMA5_INTERRUPT | DMA channel5 interrupt |
* | 33 | IRQN_UARTHS_INTERRUPT | Hi-speed UART0 interrupt |
* | 34 | IRQN_GPIOHS0_INTERRUPT | Hi-speed GPIO0 interrupt |
* | 35 | IRQN_GPIOHS1_INTERRUPT | Hi-speed GPIO1 interrupt |
* | 36 | IRQN_GPIOHS2_INTERRUPT | Hi-speed GPIO2 interrupt |
* | 37 | IRQN_GPIOHS3_INTERRUPT | Hi-speed GPIO3 interrupt |
* | 38 | IRQN_GPIOHS4_INTERRUPT | Hi-speed GPIO4 interrupt |
* | 39 | IRQN_GPIOHS5_INTERRUPT | Hi-speed GPIO5 interrupt |
* | 40 | IRQN_GPIOHS6_INTERRUPT | Hi-speed GPIO6 interrupt |
* | 41 | IRQN_GPIOHS7_INTERRUPT | Hi-speed GPIO7 interrupt |
* | 42 | IRQN_GPIOHS8_INTERRUPT | Hi-speed GPIO8 interrupt |
* | 43 | IRQN_GPIOHS9_INTERRUPT | Hi-speed GPIO9 interrupt |
* | 44 | IRQN_GPIOHS10_INTERRUPT | Hi-speed GPIO10 interrupt |
* | 45 | IRQN_GPIOHS11_INTERRUPT | Hi-speed GPIO11 interrupt |
* | 46 | IRQN_GPIOHS12_INTERRUPT | Hi-speed GPIO12 interrupt |
* | 47 | IRQN_GPIOHS13_INTERRUPT | Hi-speed GPIO13 interrupt |
* | 48 | IRQN_GPIOHS14_INTERRUPT | Hi-speed GPIO14 interrupt |
* | 49 | IRQN_GPIOHS15_INTERRUPT | Hi-speed GPIO15 interrupt |
* | 50 | IRQN_GPIOHS16_INTERRUPT | Hi-speed GPIO16 interrupt |
* | 51 | IRQN_GPIOHS17_INTERRUPT | Hi-speed GPIO17 interrupt |
* | 52 | IRQN_GPIOHS18_INTERRUPT | Hi-speed GPIO18 interrupt |
* | 53 | IRQN_GPIOHS19_INTERRUPT | Hi-speed GPIO19 interrupt |
* | 54 | IRQN_GPIOHS20_INTERRUPT | Hi-speed GPIO20 interrupt |
* | 55 | IRQN_GPIOHS21_INTERRUPT | Hi-speed GPIO21 interrupt |
* | 56 | IRQN_GPIOHS22_INTERRUPT | Hi-speed GPIO22 interrupt |
* | 57 | IRQN_GPIOHS23_INTERRUPT | Hi-speed GPIO23 interrupt |
* | 58 | IRQN_GPIOHS24_INTERRUPT | Hi-speed GPIO24 interrupt |
* | 59 | IRQN_GPIOHS25_INTERRUPT | Hi-speed GPIO25 interrupt |
* | 60 | IRQN_GPIOHS26_INTERRUPT | Hi-speed GPIO26 interrupt |
* | 61 | IRQN_GPIOHS27_INTERRUPT | Hi-speed GPIO27 interrupt |
* | 62 | IRQN_GPIOHS28_INTERRUPT | Hi-speed GPIO28 interrupt |
* | 63 | IRQN_GPIOHS29_INTERRUPT | Hi-speed GPIO29 interrupt |
* | 64 | IRQN_GPIOHS30_INTERRUPT | Hi-speed GPIO30 interrupt |
* | 65 | IRQN_GPIOHS31_INTERRUPT | Hi-speed GPIO31 interrupt |
*
*/
/* clang-format off */
typedef enum plic_irq_t
{
IRQN_NO_INTERRUPT = 0, /*!< The non-existent interrupt */
IRQN_SPI0_INTERRUPT = 1, /*!< SPI0 interrupt */
IRQN_SPI1_INTERRUPT = 2, /*!< SPI1 interrupt */
IRQN_SPI_SLAVE_INTERRUPT = 3, /*!< SPI_SLAVE interrupt */
IRQN_SPI3_INTERRUPT = 4, /*!< SPI3 interrupt */
IRQN_I2S0_INTERRUPT = 5, /*!< I2S0 interrupt */
IRQN_I2S1_INTERRUPT = 6, /*!< I2S1 interrupt */
IRQN_I2S2_INTERRUPT = 7, /*!< I2S2 interrupt */
IRQN_I2C0_INTERRUPT = 8, /*!< I2C0 interrupt */
IRQN_I2C1_INTERRUPT = 9, /*!< I2C1 interrupt */
IRQN_I2C2_INTERRUPT = 10, /*!< I2C2 interrupt */
IRQN_UART1_INTERRUPT = 11, /*!< UART1 interrupt */
IRQN_UART2_INTERRUPT = 12, /*!< UART2 interrupt */
IRQN_UART3_INTERRUPT = 13, /*!< UART3 interrupt */
IRQN_TIMER0A_INTERRUPT = 14, /*!< TIMER0 channel 0 or 1 interrupt */
IRQN_TIMER0B_INTERRUPT = 15, /*!< TIMER0 channel 2 or 3 interrupt */
IRQN_TIMER1A_INTERRUPT = 16, /*!< TIMER1 channel 0 or 1 interrupt */
IRQN_TIMER1B_INTERRUPT = 17, /*!< TIMER1 channel 2 or 3 interrupt */
IRQN_TIMER2A_INTERRUPT = 18, /*!< TIMER2 channel 0 or 1 interrupt */
IRQN_TIMER2B_INTERRUPT = 19, /*!< TIMER2 channel 2 or 3 interrupt */
IRQN_RTC_INTERRUPT = 20, /*!< RTC tick and alarm interrupt */
IRQN_WDT0_INTERRUPT = 21, /*!< Watching dog timer0 interrupt */
IRQN_WDT1_INTERRUPT = 22, /*!< Watching dog timer1 interrupt */
IRQN_APB_GPIO_INTERRUPT = 23, /*!< APB GPIO interrupt */
IRQN_DVP_INTERRUPT = 24, /*!< Digital video port interrupt */
IRQN_AI_INTERRUPT = 25, /*!< AI accelerator interrupt */
IRQN_FFT_INTERRUPT = 26, /*!< FFT accelerator interrupt */
IRQN_DMA0_INTERRUPT = 27, /*!< DMA channel0 interrupt */
IRQN_DMA1_INTERRUPT = 28, /*!< DMA channel1 interrupt */
IRQN_DMA2_INTERRUPT = 29, /*!< DMA channel2 interrupt */
IRQN_DMA3_INTERRUPT = 30, /*!< DMA channel3 interrupt */
IRQN_DMA4_INTERRUPT = 31, /*!< DMA channel4 interrupt */
IRQN_DMA5_INTERRUPT = 32, /*!< DMA channel5 interrupt */
IRQN_UARTHS_INTERRUPT = 33, /*!< Hi-speed UART0 interrupt */
IRQN_GPIOHS0_INTERRUPT = 34, /*!< Hi-speed GPIO0 interrupt */
IRQN_GPIOHS1_INTERRUPT = 35, /*!< Hi-speed GPIO1 interrupt */
IRQN_GPIOHS2_INTERRUPT = 36, /*!< Hi-speed GPIO2 interrupt */
IRQN_GPIOHS3_INTERRUPT = 37, /*!< Hi-speed GPIO3 interrupt */
IRQN_GPIOHS4_INTERRUPT = 38, /*!< Hi-speed GPIO4 interrupt */
IRQN_GPIOHS5_INTERRUPT = 39, /*!< Hi-speed GPIO5 interrupt */
IRQN_GPIOHS6_INTERRUPT = 40, /*!< Hi-speed GPIO6 interrupt */
IRQN_GPIOHS7_INTERRUPT = 41, /*!< Hi-speed GPIO7 interrupt */
IRQN_GPIOHS8_INTERRUPT = 42, /*!< Hi-speed GPIO8 interrupt */
IRQN_GPIOHS9_INTERRUPT = 43, /*!< Hi-speed GPIO9 interrupt */
IRQN_GPIOHS10_INTERRUPT = 44, /*!< Hi-speed GPIO10 interrupt */
IRQN_GPIOHS11_INTERRUPT = 45, /*!< Hi-speed GPIO11 interrupt */
IRQN_GPIOHS12_INTERRUPT = 46, /*!< Hi-speed GPIO12 interrupt */
IRQN_GPIOHS13_INTERRUPT = 47, /*!< Hi-speed GPIO13 interrupt */
IRQN_GPIOHS14_INTERRUPT = 48, /*!< Hi-speed GPIO14 interrupt */
IRQN_GPIOHS15_INTERRUPT = 49, /*!< Hi-speed GPIO15 interrupt */
IRQN_GPIOHS16_INTERRUPT = 50, /*!< Hi-speed GPIO16 interrupt */
IRQN_GPIOHS17_INTERRUPT = 51, /*!< Hi-speed GPIO17 interrupt */
IRQN_GPIOHS18_INTERRUPT = 52, /*!< Hi-speed GPIO18 interrupt */
IRQN_GPIOHS19_INTERRUPT = 53, /*!< Hi-speed GPIO19 interrupt */
IRQN_GPIOHS20_INTERRUPT = 54, /*!< Hi-speed GPIO20 interrupt */
IRQN_GPIOHS21_INTERRUPT = 55, /*!< Hi-speed GPIO21 interrupt */
IRQN_GPIOHS22_INTERRUPT = 56, /*!< Hi-speed GPIO22 interrupt */
IRQN_GPIOHS23_INTERRUPT = 57, /*!< Hi-speed GPIO23 interrupt */
IRQN_GPIOHS24_INTERRUPT = 58, /*!< Hi-speed GPIO24 interrupt */
IRQN_GPIOHS25_INTERRUPT = 59, /*!< Hi-speed GPIO25 interrupt */
IRQN_GPIOHS26_INTERRUPT = 60, /*!< Hi-speed GPIO26 interrupt */
IRQN_GPIOHS27_INTERRUPT = 61, /*!< Hi-speed GPIO27 interrupt */
IRQN_GPIOHS28_INTERRUPT = 62, /*!< Hi-speed GPIO28 interrupt */
IRQN_GPIOHS29_INTERRUPT = 63, /*!< Hi-speed GPIO29 interrupt */
IRQN_GPIOHS30_INTERRUPT = 64, /*!< Hi-speed GPIO30 interrupt */
IRQN_GPIOHS31_INTERRUPT = 65, /*!< Hi-speed GPIO31 interrupt */
IRQN_MAX
} plic_irq_t;
/* clang-format on */
typedef enum _sysctl_dma_select_t
{
SYSCTL_DMA_SELECT_SSI0_RX_REQ,
SYSCTL_DMA_SELECT_SSI0_TX_REQ,
SYSCTL_DMA_SELECT_SSI1_RX_REQ,
SYSCTL_DMA_SELECT_SSI1_TX_REQ,
SYSCTL_DMA_SELECT_SSI2_RX_REQ,
SYSCTL_DMA_SELECT_SSI2_TX_REQ,
SYSCTL_DMA_SELECT_SSI3_RX_REQ,
SYSCTL_DMA_SELECT_SSI3_TX_REQ,
SYSCTL_DMA_SELECT_I2C0_RX_REQ,
SYSCTL_DMA_SELECT_I2C0_TX_REQ,
SYSCTL_DMA_SELECT_I2C1_RX_REQ,
SYSCTL_DMA_SELECT_I2C1_TX_REQ,
SYSCTL_DMA_SELECT_I2C2_RX_REQ,
SYSCTL_DMA_SELECT_I2C2_TX_REQ,
SYSCTL_DMA_SELECT_UART1_RX_REQ,
SYSCTL_DMA_SELECT_UART1_TX_REQ,
SYSCTL_DMA_SELECT_UART2_RX_REQ,
SYSCTL_DMA_SELECT_UART2_TX_REQ,
SYSCTL_DMA_SELECT_UART3_RX_REQ,
SYSCTL_DMA_SELECT_UART3_TX_REQ,
SYSCTL_DMA_SELECT_AES_REQ,
SYSCTL_DMA_SELECT_SHA_RX_REQ,
SYSCTL_DMA_SELECT_AI_RX_REQ,
SYSCTL_DMA_SELECT_FFT_RX_REQ,
SYSCTL_DMA_SELECT_FFT_TX_REQ,
SYSCTL_DMA_SELECT_I2S0_TX_REQ,
SYSCTL_DMA_SELECT_I2S0_RX_REQ,
SYSCTL_DMA_SELECT_I2S1_TX_REQ,
SYSCTL_DMA_SELECT_I2S1_RX_REQ,
SYSCTL_DMA_SELECT_I2S2_TX_REQ,
SYSCTL_DMA_SELECT_I2S2_RX_REQ,
SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ,
SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ,
SYSCTL_DMA_SELECT_MAX
} sysctl_dma_select_t;
#endif /* _BSP_PLATFORM_H */

0
lib/bsp/include/printf.h → lib/arch/include/printf.h
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22
lib/bsp/CMakeLists.txt Normal file
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@ -0,0 +1,22 @@
#project(bsp)
# create bsp library
FILE(GLOB_RECURSE LIB_SRC_NOASM
"${CMAKE_CURRENT_LIST_DIR}/*.cpp"
"${CMAKE_CURRENT_LIST_DIR}/*.c"
)
FILE(GLOB_RECURSE ASSEMBLY_FILES
"${CMAKE_CURRENT_LIST_DIR}/*.s"
"${CMAKE_CURRENT_LIST_DIR}/*.S"
)
SET(LIB_SRC ${LIB_SRC_NOASM} ${ASSEMBLY_FILES})
INCLUDE_DIRECTORIES(${CMAKE_CURRENT_LIST_DIR}/include)
SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C)
SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64")
ADD_LIBRARY(bsp STATIC ${LIB_SRC})
SET_TARGET_PROPERTIES(bsp PROPERTIES LINKER_LANGUAGE C)
TARGET_LINK_LIBRARIES(bsp PRIVATE drivers freertos)

2
lib/bsp/config/fpioa_cfg.c
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@ -12,7 +12,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <fpioa_cfg.h>
#include "../device/fpioa_cfg.h"
const fpioa_cfg_t g_fpioa_cfg =
{

2
lib/bsp/crt.S
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@ -11,7 +11,7 @@
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# include "encoding.h"
# include <encoding.h>
# define REGBYTES 8
# define STKSHIFT 15

27
lib/bsp/device/fpioa.c
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@ -1,27 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "fpioa_cfg.h"
int fpioa_get_io_by_func(enum fpioa_function_e function)
{
int index;
for (index = 0; index < FPIOA_NUM_IO; index++)
{
if (fpioa->io[index].ch_sel == function)
return index;
}
return -1;
}

6
lib/bsp/dump.c
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@ -13,11 +13,11 @@
* limitations under the License.
*/
#include <atomic.h>
#include <dump.h>
#include <stdlib.h>
#include <string.h>
#include "syslog.h"
#include "uarths.h"
#include <syslog.h>
#include <uarths.h>
#include "dump.h"
#define DUMP_PRINTF printk

2
lib/bsp/except.c
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@ -12,9 +12,9 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <dump.h>
#include <encoding.h>
#include <stdlib.h>
#include "dump.h"
#ifndef UNUSED
#define UNUSED(x) (void)(x)

89
lib/bsp/include/platform.h
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@ -1,89 +0,0 @@
/* Copyright 2018 Canaan Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _BSP_PLATFORM_H
#define _BSP_PLATFORM_H
/* clang-format off */
/* Register base address */
/* Under Coreplex */
#define CLINT_BASE_ADDR (0x02000000)
#define PLIC_BASE_ADDR (0x0C000000)
/* Under TileLink */
#define UARTHS_BASE_ADDR (0x38000000)
#define GPIOHS_BASE_ADDR (0x38001000)
/* Under AXI 64 bit */
#define RAM_BASE_ADDR (0x80000000)
#define RAM_SIZE (6 * 1024 * 1024)
#define IO_BASE_ADDR (0x40000000)
#define IO_SIZE (6 * 1024 * 1024)
#define AI_RAM_BASE_ADDR (0x80600000)
#define AI_RAM_SIZE (2 * 1024 * 1024)
#define AI_IO_BASE_ADDR (0x40600000)
#define AI_IO_SIZE (2 * 1024 * 1024)
#define AI_BASE_ADDR (0x40800000)
#define AI_SIZE (12 * 1024 * 1024)
#define FFT_BASE_ADDR (0x42000000)
#define FFT_SIZE (4 * 1024 * 1024)
#define ROM_BASE_ADDR (0x88000000)
#define ROM_SIZE (128 * 1024)
/* Under AHB 32 bit */
#define DMAC_BASE_ADDR (0x50000000)
/* Under APB1 32 bit */
#define GPIO_BASE_ADDR (0x50200000)
#define UART1_BASE_ADDR (0x50210000)
#define UART2_BASE_ADDR (0x50220000)
#define UART3_BASE_ADDR (0x50230000)
#define SPI_SLAVE_BASE_ADDR (0x50240000)
#define I2S0_BASE_ADDR (0x50250000)
#define I2S1_BASE_ADDR (0x50260000)
#define I2S2_BASE_ADDR (0x50270000)
#define I2C0_BASE_ADDR (0x50280000)
#define I2C1_BASE_ADDR (0x50290000)
#define I2C2_BASE_ADDR (0x502A0000)
#define FPIOA_BASE_ADDR (0x502B0000)
#define SHA256_BASE_ADDR (0x502C0000)
#define TIMER0_BASE_ADDR (0x502D0000)
#define TIMER1_BASE_ADDR (0x502E0000)
#define TIMER2_BASE_ADDR (0x502F0000)
/* Under APB2 32 bit */
#define WDT0_BASE_ADDR (0x50400000)
#define WDT1_BASE_ADDR (0x50410000)
#define OTP_BASE_ADDR (0x50420000)
#define DVP_BASE_ADDR (0x50430000)
#define SYSCTL_BASE_ADDR (0x50440000)
#define AES_BASE_ADDR (0x50450000)
#define RTC_BASE_ADDR (0x50460000)
/* Under APB3 32 bit */
#define SPI0_BASE_ADDR (0x52000000)
#define SPI1_BASE_ADDR (0x53000000)
#define SPI3_BASE_ADDR (0x54000000)
/* clang-format on */
#endif /* _BSP_PLATFORM_H */

5
lib/bsp/printf.c
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@ -41,10 +41,9 @@
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <printf.h>
#include <stddef.h>
#include "printf.h"
/*
* Configuration
*/
@ -641,7 +640,7 @@ static corelock_t lock = CORELOCK_INIT;
static void uart_putf(void* unused, char c)
{
UNUSED(unused);
uarths_putchar(c);
uarths_write_byte(c);
}
int printk(const char* format, ...)

2
lib/bsp/sleep.c
View File

@ -14,8 +14,8 @@
*/
#include <FreeRTOS.h>
#include <task.h>
#include <sleep.h>
#include <sysctl.h>
#include "sleep.h"
int nanosleep(const struct timespec* req, struct timespec* rem)
{

38
lib/bsp/syscalls.c
View File

@ -12,12 +12,19 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <atomic.h>
#include <clint.h>
#include <devices.h>
#include <errno.h>
#include <dump.h>
#include <fpioa.h>
#include <interrupt.h>
#include <limits.h>
#include <machine/syscall.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/unistd.h>
#include <errno.h>
#include <limits.h>
#include <sysctl.h>
#include <stdarg.h>
#include <stdbool.h>
#include <stdint.h>
@ -25,14 +32,7 @@
#include <stdlib.h>
#include <string.h>
#include <syslog.h>
#include "../freertos/device/devices.h"
#include "atomic.h"
#include "clint.h"
#include "dump.h"
#include "fpioa.h"
#include "interrupt.h"
#include "sysctl.h"
#include "uarths.h"
#include <uarths.h>
/*
* @note System call list
@ -113,14 +113,8 @@ void __attribute__((noreturn)) sys_exit(int code)
{
/* First print some diagnostic information. */
LOGW(TAG, "sys_exit called with 0x%lx\n", (uint64_t)code);
/* Write exit register to pause netlist simulation */
volatile uint32_t* reg = (uint32_t*)&sysctl->peri;
/* Write stop bit and write back */
*reg = (*reg) | 0x80000000UL;
/* Send 0 to uart */
uarths_putchar(0);
while (1)
continue;
;
}
static int sys_nosys(long a0, long a1, long a2, long a3, long a4, long a5, unsigned long n)
@ -129,11 +123,6 @@ static int sys_nosys(long a0, long a1, long a2, long a3, long a4, long a5, unsig
UNUSED(a4);
UNUSED(a5);
LOGE(TAG, "Unsupported syscall %ld: a0=%lx, a1=%lx, a2=%lx!\n", n, a0, a1, a2);
/* Send 0 to uart */
uarths_putchar(0);
while (1)
continue;
return -ENOSYS;
}
@ -176,8 +165,6 @@ static size_t sys_brk(size_t pos)
/* Call again */
if ((uintptr_t)pos > (uintptr_t)&_heap_end[0])
{
/* Memory out, return -ENOMEM */
LOGE(TAG, "Out of memory\n");
res = -ENOMEM;
}
else
@ -217,14 +204,13 @@ static ssize_t sys_write(int file, const void* ptr, size_t len)
{
/* Write data */
while (length-- > 0 && *data != 0)
uarths_putchar(*(data++));
uarths_write_byte(*(data++));
/* Return the actual size written */
res = len;
}
else
{
/* Not support yet */
res = io_write(file, data, length);
}

24
lib/drivers/CMakeLists.txt Normal file
View File

@ -0,0 +1,24 @@
#project(drivers)
# create drivers library
FILE(GLOB_RECURSE LIB_SRC_NOASM
"${CMAKE_CURRENT_LIST_DIR}/*.cpp"
"${CMAKE_CURRENT_LIST_DIR}/*.c"
)
FILE(GLOB_RECURSE ASSEMBLY_FILES
"${CMAKE_CURRENT_LIST_DIR}/*.s"
"${CMAKE_CURRENT_LIST_DIR}/*.S"
)
SET(LIB_SRC ${LIB_SRC_NOASM} ${ASSEMBLY_FILES})
SET(LIB_INC ${CMAKE_CURRENT_LIST_DIR}/include)
SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C)
SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64")
ADD_LIBRARY(drivers STATIC ${LIB_SRC})
SET_TARGET_PROPERTIES(drivers PROPERTIES LINKER_LANGUAGE C)
TARGET_LINK_LIBRARIES(drivers m)
TARGET_INCLUDE_DIRECTORIES(drivers PUBLIC ${LIB_INC})

2
lib/drivers/clint.c
View File

@ -12,9 +12,9 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <encoding.h>
#include <stddef.h>
#include <stdint.h>
#include "encoding.h"
#include "clint.h"
#include "sysctl.h"

2
lib/drivers/fpioa.c
View File

@ -14,8 +14,8 @@
*/
#include <stddef.h>
#include <stdint.h>
#include "sysctl.h"
#include "fpioa.h"
#include "sysctl.h"
volatile struct fpioa_t *const fpioa = (volatile struct fpioa_t *)FPIOA_BASE_ADDR;

150
lib/drivers/include/plic.h
View File

@ -75,154 +75,6 @@ extern "C" {
#define PLIC_NUM_HARTS (2)
/* clang-format on */
/**
* @brief PLIC External Interrupt Numbers
*
* @note PLIC interrupt sources
*
* | Source | Name | Description |
* |--------|--------------------------|------------------------------------|
* | 0 | IRQN_NO_INTERRUPT | The non-existent interrupt |
* | 1 | IRQN_SPI0_INTERRUPT | SPI0 interrupt |
* | 2 | IRQN_SPI1_INTERRUPT | SPI1 interrupt |
* | 3 | IRQN_SPI_SLAVE_INTERRUPT | SPI_SLAVE interrupt |
* | 4 | IRQN_SPI3_INTERRUPT | SPI3 interrupt |
* | 5 | IRQN_I2S0_INTERRUPT | I2S0 interrupt |
* | 6 | IRQN_I2S1_INTERRUPT | I2S1 interrupt |
* | 7 | IRQN_I2S2_INTERRUPT | I2S2 interrupt |
* | 8 | IRQN_I2C0_INTERRUPT | I2C0 interrupt |
* | 9 | IRQN_I2C1_INTERRUPT | I2C1 interrupt |
* | 10 | IRQN_I2C2_INTERRUPT | I2C2 interrupt |
* | 11 | IRQN_UART1_INTERRUPT | UART1 interrupt |
* | 12 | IRQN_UART2_INTERRUPT | UART2 interrupt |
* | 13 | IRQN_UART3_INTERRUPT | UART3 interrupt |
* | 14 | IRQN_TIMER0A_INTERRUPT | TIMER0 channel 0 or 1 interrupt |
* | 15 | IRQN_TIMER0B_INTERRUPT | TIMER0 channel 2 or 3 interrupt |
* | 16 | IRQN_TIMER1A_INTERRUPT | TIMER1 channel 0 or 1 interrupt |
* | 17 | IRQN_TIMER1B_INTERRUPT | TIMER1 channel 2 or 3 interrupt |
* | 18 | IRQN_TIMER2A_INTERRUPT | TIMER2 channel 0 or 1 interrupt |
* | 19 | IRQN_TIMER2B_INTERRUPT | TIMER2 channel 2 or 3 interrupt |
* | 20 | IRQN_RTC_INTERRUPT | RTC tick and alarm interrupt |
* | 21 | IRQN_WDT0_INTERRUPT | Watching dog timer0 interrupt |
* | 22 | IRQN_WDT1_INTERRUPT | Watching dog timer1 interrupt |
* | 23 | IRQN_APB_GPIO_INTERRUPT | APB GPIO interrupt |
* | 24 | IRQN_DVP_INTERRUPT | Digital video port interrupt |
* | 25 | IRQN_AI_INTERRUPT | AI accelerator interrupt |
* | 26 | IRQN_FFT_INTERRUPT | FFT accelerator interrupt |
* | 27 | IRQN_DMA0_INTERRUPT | DMA channel0 interrupt |
* | 28 | IRQN_DMA1_INTERRUPT | DMA channel1 interrupt |
* | 29 | IRQN_DMA2_INTERRUPT | DMA channel2 interrupt |
* | 30 | IRQN_DMA3_INTERRUPT | DMA channel3 interrupt |
* | 31 | IRQN_DMA4_INTERRUPT | DMA channel4 interrupt |
* | 32 | IRQN_DMA5_INTERRUPT | DMA channel5 interrupt |
* | 33 | IRQN_UARTHS_INTERRUPT | Hi-speed UART0 interrupt |
* | 34 | IRQN_GPIOHS0_INTERRUPT | Hi-speed GPIO0 interrupt |
* | 35 | IRQN_GPIOHS1_INTERRUPT | Hi-speed GPIO1 interrupt |
* | 36 | IRQN_GPIOHS2_INTERRUPT | Hi-speed GPIO2 interrupt |
* | 37 | IRQN_GPIOHS3_INTERRUPT | Hi-speed GPIO3 interrupt |
* | 38 | IRQN_GPIOHS4_INTERRUPT | Hi-speed GPIO4 interrupt |
* | 39 | IRQN_GPIOHS5_INTERRUPT | Hi-speed GPIO5 interrupt |
* | 40 | IRQN_GPIOHS6_INTERRUPT | Hi-speed GPIO6 interrupt |
* | 41 | IRQN_GPIOHS7_INTERRUPT | Hi-speed GPIO7 interrupt |
* | 42 | IRQN_GPIOHS8_INTERRUPT | Hi-speed GPIO8 interrupt |
* | 43 | IRQN_GPIOHS9_INTERRUPT | Hi-speed GPIO9 interrupt |
* | 44 | IRQN_GPIOHS10_INTERRUPT | Hi-speed GPIO10 interrupt |
* | 45 | IRQN_GPIOHS11_INTERRUPT | Hi-speed GPIO11 interrupt |
* | 46 | IRQN_GPIOHS12_INTERRUPT | Hi-speed GPIO12 interrupt |
* | 47 | IRQN_GPIOHS13_INTERRUPT | Hi-speed GPIO13 interrupt |
* | 48 | IRQN_GPIOHS14_INTERRUPT | Hi-speed GPIO14 interrupt |
* | 49 | IRQN_GPIOHS15_INTERRUPT | Hi-speed GPIO15 interrupt |
* | 50 | IRQN_GPIOHS16_INTERRUPT | Hi-speed GPIO16 interrupt |
* | 51 | IRQN_GPIOHS17_INTERRUPT | Hi-speed GPIO17 interrupt |
* | 52 | IRQN_GPIOHS18_INTERRUPT | Hi-speed GPIO18 interrupt |
* | 53 | IRQN_GPIOHS19_INTERRUPT | Hi-speed GPIO19 interrupt |
* | 54 | IRQN_GPIOHS20_INTERRUPT | Hi-speed GPIO20 interrupt |
* | 55 | IRQN_GPIOHS21_INTERRUPT | Hi-speed GPIO21 interrupt |
* | 56 | IRQN_GPIOHS22_INTERRUPT | Hi-speed GPIO22 interrupt |
* | 57 | IRQN_GPIOHS23_INTERRUPT | Hi-speed GPIO23 interrupt |
* | 58 | IRQN_GPIOHS24_INTERRUPT | Hi-speed GPIO24 interrupt |
* | 59 | IRQN_GPIOHS25_INTERRUPT | Hi-speed GPIO25 interrupt |
* | 60 | IRQN_GPIOHS26_INTERRUPT | Hi-speed GPIO26 interrupt |
* | 61 | IRQN_GPIOHS27_INTERRUPT | Hi-speed GPIO27 interrupt |
* | 62 | IRQN_GPIOHS28_INTERRUPT | Hi-speed GPIO28 interrupt |
* | 63 | IRQN_GPIOHS29_INTERRUPT | Hi-speed GPIO29 interrupt |
* | 64 | IRQN_GPIOHS30_INTERRUPT | Hi-speed GPIO30 interrupt |
* | 65 | IRQN_GPIOHS31_INTERRUPT | Hi-speed GPIO31 interrupt |
*
*/
/* clang-format off */
typedef enum plic_irq_t
{
IRQN_NO_INTERRUPT = 0, /*!< The non-existent interrupt */
IRQN_SPI0_INTERRUPT = 1, /*!< SPI0 interrupt */
IRQN_SPI1_INTERRUPT = 2, /*!< SPI1 interrupt */
IRQN_SPI_SLAVE_INTERRUPT = 3, /*!< SPI_SLAVE interrupt */
IRQN_SPI3_INTERRUPT = 4, /*!< SPI3 interrupt */
IRQN_I2S0_INTERRUPT = 5, /*!< I2S0 interrupt */
IRQN_I2S1_INTERRUPT = 6, /*!< I2S1 interrupt */
IRQN_I2S2_INTERRUPT = 7, /*!< I2S2 interrupt */
IRQN_I2C0_INTERRUPT = 8, /*!< I2C0 interrupt */
IRQN_I2C1_INTERRUPT = 9, /*!< I2C1 interrupt */
IRQN_I2C2_INTERRUPT = 10, /*!< I2C2 interrupt */
IRQN_UART1_INTERRUPT = 11, /*!< UART1 interrupt */
IRQN_UART2_INTERRUPT = 12, /*!< UART2 interrupt */
IRQN_UART3_INTERRUPT = 13, /*!< UART3 interrupt */
IRQN_TIMER0A_INTERRUPT = 14, /*!< TIMER0 channel 0 or 1 interrupt */
IRQN_TIMER0B_INTERRUPT = 15, /*!< TIMER0 channel 2 or 3 interrupt */
IRQN_TIMER1A_INTERRUPT = 16, /*!< TIMER1 channel 0 or 1 interrupt */
IRQN_TIMER1B_INTERRUPT = 17, /*!< TIMER1 channel 2 or 3 interrupt */
IRQN_TIMER2A_INTERRUPT = 18, /*!< TIMER2 channel 0 or 1 interrupt */
IRQN_TIMER2B_INTERRUPT = 19, /*!< TIMER2 channel 2 or 3 interrupt */
IRQN_RTC_INTERRUPT = 20, /*!< RTC tick and alarm interrupt */
IRQN_WDT0_INTERRUPT = 21, /*!< Watching dog timer0 interrupt */
IRQN_WDT1_INTERRUPT = 22, /*!< Watching dog timer1 interrupt */
IRQN_APB_GPIO_INTERRUPT = 23, /*!< APB GPIO interrupt */
IRQN_DVP_INTERRUPT = 24, /*!< Digital video port interrupt */
IRQN_AI_INTERRUPT = 25, /*!< AI accelerator interrupt */
IRQN_FFT_INTERRUPT = 26, /*!< FFT accelerator interrupt */
IRQN_DMA0_INTERRUPT = 27, /*!< DMA channel0 interrupt */
IRQN_DMA1_INTERRUPT = 28, /*!< DMA channel1 interrupt */
IRQN_DMA2_INTERRUPT = 29, /*!< DMA channel2 interrupt */
IRQN_DMA3_INTERRUPT = 30, /*!< DMA channel3 interrupt */
IRQN_DMA4_INTERRUPT = 31, /*!< DMA channel4 interrupt */
IRQN_DMA5_INTERRUPT = 32, /*!< DMA channel5 interrupt */
IRQN_UARTHS_INTERRUPT = 33, /*!< Hi-speed UART0 interrupt */
IRQN_GPIOHS0_INTERRUPT = 34, /*!< Hi-speed GPIO0 interrupt */
IRQN_GPIOHS1_INTERRUPT = 35, /*!< Hi-speed GPIO1 interrupt */
IRQN_GPIOHS2_INTERRUPT = 36, /*!< Hi-speed GPIO2 interrupt */
IRQN_GPIOHS3_INTERRUPT = 37, /*!< Hi-speed GPIO3 interrupt */
IRQN_GPIOHS4_INTERRUPT = 38, /*!< Hi-speed GPIO4 interrupt */
IRQN_GPIOHS5_INTERRUPT = 39, /*!< Hi-speed GPIO5 interrupt */
IRQN_GPIOHS6_INTERRUPT = 40, /*!< Hi-speed GPIO6 interrupt */
IRQN_GPIOHS7_INTERRUPT = 41, /*!< Hi-speed GPIO7 interrupt */
IRQN_GPIOHS8_INTERRUPT = 42, /*!< Hi-speed GPIO8 interrupt */
IRQN_GPIOHS9_INTERRUPT = 43, /*!< Hi-speed GPIO9 interrupt */
IRQN_GPIOHS10_INTERRUPT = 44, /*!< Hi-speed GPIO10 interrupt */
IRQN_GPIOHS11_INTERRUPT = 45, /*!< Hi-speed GPIO11 interrupt */
IRQN_GPIOHS12_INTERRUPT = 46, /*!< Hi-speed GPIO12 interrupt */
IRQN_GPIOHS13_INTERRUPT = 47, /*!< Hi-speed GPIO13 interrupt */
IRQN_GPIOHS14_INTERRUPT = 48, /*!< Hi-speed GPIO14 interrupt */
IRQN_GPIOHS15_INTERRUPT = 49, /*!< Hi-speed GPIO15 interrupt */
IRQN_GPIOHS16_INTERRUPT = 50, /*!< Hi-speed GPIO16 interrupt */
IRQN_GPIOHS17_INTERRUPT = 51, /*!< Hi-speed GPIO17 interrupt */
IRQN_GPIOHS18_INTERRUPT = 52, /*!< Hi-speed GPIO18 interrupt */
IRQN_GPIOHS19_INTERRUPT = 53, /*!< Hi-speed GPIO19 interrupt */
IRQN_GPIOHS20_INTERRUPT = 54, /*!< Hi-speed GPIO20 interrupt */
IRQN_GPIOHS21_INTERRUPT = 55, /*!< Hi-speed GPIO21 interrupt */
IRQN_GPIOHS22_INTERRUPT = 56, /*!< Hi-speed GPIO22 interrupt */
IRQN_GPIOHS23_INTERRUPT = 57, /*!< Hi-speed GPIO23 interrupt */
IRQN_GPIOHS24_INTERRUPT = 58, /*!< Hi-speed GPIO24 interrupt */
IRQN_GPIOHS25_INTERRUPT = 59, /*!< Hi-speed GPIO25 interrupt */
IRQN_GPIOHS26_INTERRUPT = 60, /*!< Hi-speed GPIO26 interrupt */
IRQN_GPIOHS27_INTERRUPT = 61, /*!< Hi-speed GPIO27 interrupt */
IRQN_GPIOHS28_INTERRUPT = 62, /*!< Hi-speed GPIO28 interrupt */
IRQN_GPIOHS29_INTERRUPT = 63, /*!< Hi-speed GPIO29 interrupt */
IRQN_GPIOHS30_INTERRUPT = 64, /*!< Hi-speed GPIO30 interrupt */
IRQN_GPIOHS31_INTERRUPT = 65, /*!< Hi-speed GPIO31 interrupt */
IRQN_MAX
} plic_irq_t;
/* clang-format on */
/**
* @brief Interrupt Source Priorities
*
@ -350,8 +202,6 @@ struct plic_t
struct plic_target_t targets;
} __attribute__((packed, aligned(4)));
extern volatile struct plic_t *const plic;
/**
* @brief Definitions for the interrupt callbacks
*/

38
lib/drivers/include/sysctl.h
View File

@ -93,44 +93,6 @@ typedef enum _sysctl_dma_channel_t
SYSCTL_DMA_CHANNEL_MAX
} sysctl_dma_channel_t;
typedef enum _sysctl_dma_select_t
{
SYSCTL_DMA_SELECT_SSI0_RX_REQ,
SYSCTL_DMA_SELECT_SSI0_TX_REQ,
SYSCTL_DMA_SELECT_SSI1_RX_REQ,
SYSCTL_DMA_SELECT_SSI1_TX_REQ,
SYSCTL_DMA_SELECT_SSI2_RX_REQ,
SYSCTL_DMA_SELECT_SSI2_TX_REQ,
SYSCTL_DMA_SELECT_SSI3_RX_REQ,
SYSCTL_DMA_SELECT_SSI3_TX_REQ,
SYSCTL_DMA_SELECT_I2C0_RX_REQ,
SYSCTL_DMA_SELECT_I2C0_TX_REQ,
SYSCTL_DMA_SELECT_I2C1_RX_REQ,
SYSCTL_DMA_SELECT_I2C1_TX_REQ,
SYSCTL_DMA_SELECT_I2C2_RX_REQ,
SYSCTL_DMA_SELECT_I2C2_TX_REQ,
SYSCTL_DMA_SELECT_UART1_RX_REQ,
SYSCTL_DMA_SELECT_UART1_TX_REQ,
SYSCTL_DMA_SELECT_UART2_RX_REQ,
SYSCTL_DMA_SELECT_UART2_TX_REQ,
SYSCTL_DMA_SELECT_UART3_RX_REQ,
SYSCTL_DMA_SELECT_UART3_TX_REQ,
SYSCTL_DMA_SELECT_AES_REQ,
SYSCTL_DMA_SELECT_SHA_RX_REQ,
SYSCTL_DMA_SELECT_AI_RX_REQ,
SYSCTL_DMA_SELECT_FFT_RX_REQ,
SYSCTL_DMA_SELECT_FFT_TX_REQ,
SYSCTL_DMA_SELECT_I2S0_TX_REQ,
SYSCTL_DMA_SELECT_I2S0_RX_REQ,
SYSCTL_DMA_SELECT_I2S1_TX_REQ,
SYSCTL_DMA_SELECT_I2S1_RX_REQ,
SYSCTL_DMA_SELECT_I2S2_TX_REQ,
SYSCTL_DMA_SELECT_I2S2_RX_REQ,
SYSCTL_DMA_SELECT_I2S0_BF_DIR_REQ,
SYSCTL_DMA_SELECT_I2S0_BF_VOICE_REQ,
SYSCTL_DMA_SELECT_MAX
} sysctl_dma_select_t;
/**
* @brief System controller clock id
*/

44
lib/drivers/include/uarths.h
View File

@ -172,48 +172,30 @@ struct uarths_t
/**
* @brief Initialization Core UART
*
* @return result
* - 0 Success
* - Other Fail
*/
int uarths_init();
void uarths_init();
/**
* @brief Put a char to UART
* @brief Get a byte from UART
*
* @param[in] c The char to put
*
* @note If c is '\n', a '\r' will be appended automatically
*
* @return result
* - 0 Success
* - Other Fail
* @return byte from UART
*/
int uarths_putchar(char c);
uint8_t uarths_read_byte();
/**
* @brief Put a byte to UART
*
* @param[in] value The byte to put
*/
void uarths_write_byte(uint8_t value);
/**
* @brief Send a string to UART
*
* @param[in] s The string to send
*
* @note The string must ending with '\0'
*
* @return result
* - 0 Success
* - Other Fail
*/
int uarths_puts(const char *s);
/**
* @brief Get a byte from UART
*
* @return byte as int type from UART
*/
int uarths_getc(void);
void uarths_puts(const char *s);
#ifdef __cplusplus
}

2
lib/drivers/io.c
View File

@ -12,7 +12,7 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <io.h>
#include "io.h"
uint32_t get_bit_mask(volatile uint32_t* bits, uint32_t mask)
{

6
lib/drivers/sysctl.c
View File

@ -12,13 +12,13 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <encoding.h>
#include <math.h>
#include <stdint.h>
#include <stdlib.h>
#include <math.h>
#include <string.h>
#include <stdio.h>
#include "sysctl.h"
#include "string.h"
#include "encoding.h"
#define SYSCTRL_CLOCK_FREQ_IN0 (26000000UL)

60
lib/drivers/uarths.c
View File

@ -12,70 +12,38 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <encoding.h>
#include <stdint.h>
#include <stdio.h>
#include "uarths.h"
#include "sysctl.h"
#include "encoding.h"
#include "uarths.h"
volatile struct uarths_t *const uarths = (volatile struct uarths_t *)UARTHS_BASE_ADDR;
static inline int uart_putc(char c)
uint8_t uarths_read_byte()
{
/* Read core id */
unsigned long core_id = read_csr(mhartid);
/* Set print data reg */
volatile uint32_t *reg = (volatile uint32_t *)0x50440080UL;
/* Push data out */
if (core_id == 0)
while (1)
{
/* Select core 0 data reg */
*reg = (0UL << 30) | c;
}
else
{
/* Select core 1 data reg */
*reg = (1UL << 30) | c;
struct uarths_rxdata_t recv = uarths->rxdata;
if (!recv.empty)
return recv.data;
}
}
/* Convert to DOS style (CRLF terminated) */
if (c == '\n')
{
while (uarths->txdata.full)
continue;
uarths->txdata.data = '\r';
}
void uarths_write_byte(uint8_t c)
{
while (uarths->txdata.full)
continue;
uarths->txdata.data = c;
return 0;
}
int uarths_getc(void)
{
/* while not empty */
struct uarths_rxdata_t recv = uarths->rxdata;
if (recv.empty)
return EOF;
else
return recv.data;
}
int uarths_putchar(char c)
{
return uart_putc(c);
}
int uarths_puts(const char *s)
void uarths_puts(const char *s)
{
while (*s)
if (uart_putc(*s++) != 0)
return -1;
return 0;
uarths_write_byte(*s++);
}
int uarths_init()
void uarths_init()
{
uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
uint16_t div = freq / 115200 - 1;
@ -90,6 +58,4 @@ int uarths_init()
uarths->ip.rxwm = 1;
uarths->ie.txwm = 0;
uarths->ie.rxwm = 1;
return 0;
}

24
lib/freertos/CMakeLists.txt Normal file
View File

@ -0,0 +1,24 @@
#project(freertos)
# create freertos library
FILE(GLOB_RECURSE LIB_SRC_NOASM
"${CMAKE_CURRENT_LIST_DIR}/*.cpp"
"${CMAKE_CURRENT_LIST_DIR}/*.c"
)
FILE(GLOB_RECURSE ASSEMBLY_FILES
"${CMAKE_CURRENT_LIST_DIR}/*.s"
"${CMAKE_CURRENT_LIST_DIR}/*.S"
)
SET(LIB_SRC ${LIB_SRC_NOASM} ${ASSEMBLY_FILES})
SET(LIB_INC ${CMAKE_CURRENT_LIST_DIR}/include ${CMAKE_CURRENT_LIST_DIR}/conf ${CMAKE_CURRENT_LIST_DIR}/portable)
SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C)
SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64")
ADD_LIBRARY(freertos STATIC ${LIB_SRC})
SET_TARGET_PROPERTIES(freertos PROPERTIES LINKER_LANGUAGE C)
TARGET_LINK_LIBRARIES(freertos PRIVATE drivers)
TARGET_INCLUDE_DIRECTORIES(freertos PUBLIC ${LIB_INC})

4
lib/freertos/core_sync.c
View File

@ -12,15 +12,13 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <FreeRTOS.h>
#include <atomic.h>
#include <clint.h>
#include <core_sync.h>
#include <encoding.h>
#include <plic.h>
#include "portable/portmacro.h"
#include "FreeRTOS.h"
#include "task.h"
#include <printf.h>
volatile UBaseType_t g_core_pending_switch[portNUM_PROCESSORS] = { 0 };
static volatile UBaseType_t s_core_sync_events[portNUM_PROCESSORS] = { 0 };

2
lib/freertos/device/device_priv.h
View File

@ -15,9 +15,9 @@
#ifndef _FREERTOS_DEVICE_PRIV_H
#define _FREERTOS_DEVICE_PRIV_H
#include <driver.h>
#include <stddef.h>
#include <stdint.h>
#include "driver.h"
#ifdef __cplusplus
extern "C"

4
lib/freertos/device/devices.c
View File

@ -12,9 +12,9 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <FreeRTOS.h>
#include "FreeRTOS.h"
#include <atomic.h>
#include <device_priv.h>
#include "device_priv.h"
#include <devices.h>
#include <driver.h>
#include <hal.h>

2
lib/freertos/device/devices.h → lib/freertos/include/devices.h
View File

@ -15,9 +15,9 @@
#ifndef _FREERTOS_DEVICES_H
#define _FREERTOS_DEVICES_H
#include <driver.h>
#include <stddef.h>
#include <stdint.h>
#include "driver.h"
#ifdef __cplusplus
extern "C"

0
lib/freertos/device/driver.h → lib/freertos/include/driver.h
View File

0
lib/freertos/device/hal.h → lib/freertos/include/hal.h
View File

9
lib/freertos/os_entry.c
View File

@ -12,16 +12,15 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <FreeRTOS.h>
#include <clint.h>
#include <encoding.h>
#include <fpioa.h>
#include <stdlib.h>
#include <task.h>
#include <device_priv.h>
#include <stdio.h>
#include <core_sync.h>
#include "portable/portmacro.h"
#include "core_sync.h"
#include "device/device_priv.h"
#include "FreeRTOS.h"
#include "task.h"
typedef struct
{

2
lib/freertos/portable/heap_4.c
View File

@ -54,9 +54,9 @@ all the API functions to use the MPU wrappers. That should only be done when
task.h is included from an application file. */
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
#include "atomic.h"
#include "FreeRTOS.h"
#include "task.h"
#include "atomic.h"
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE

8
lib/freertos/portable/port.c
View File

@ -45,16 +45,16 @@
/* Scheduler includes. */
#include <atomic.h>
#include <core_sync.h>
#include <clint.h>
#include <encoding.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sysctl.h>
#include <syslog.h>
#include "core_sync.h"
#include "FreeRTOS.h"
#include "clint.h"
#include "encoding.h"
#include "portmacro.h"
#include "stdio.h"
#include "task.h"
/* A variable is used to keep track of the critical section nesting. This

2
lib/freertos/portable/portmacro.h
View File

@ -55,7 +55,7 @@ extern "C" {
* These settings should not be altered.
*-----------------------------------------------------------
*/
#include "encoding.h"
#include <encoding.h>
/* Multi-Core */
#define portNUM_PROCESSORS 2

4
lib/utils/include/syslog.h
View File

@ -17,8 +17,8 @@
#include <stdint.h>
#include <stdio.h>
#include "printf.h"
#include "encoding.h"
#include <printf.h>
#include <encoding.h>
#ifdef __cplusplus
extern "C" {