Debug PLIC
parent
a263ae5661
commit
9e5ee183af
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@ -116,11 +116,13 @@ public:
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virtual void on_first_open() override
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{
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sysctl_clock_enable(clock_);
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dma_ch_ = dma_open_free();
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}
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virtual void on_last_close() override
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{
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sysctl_clock_disable(clock_);
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dma_close(dma_ch_);
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}
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virtual handle_t model_load_from_buffer(uint8_t *buffer) override
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@ -134,7 +136,7 @@ public:
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auto model_context = system_handle_to_object(context).as<k_model_context>();
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model_context->get(&ctx_);
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dma_ch_ = dma_open_free();
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ctx_.current_layer = 0;
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ctx_.current_body = ctx_.body_start;
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@ -147,7 +149,7 @@ public:
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kpu_.interrupt_mask.reg = 0b110;
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pic_set_irq_priority(IRQN_AI_INTERRUPT, 1);
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pic_set_irq_priority(IRQN_AI_INTERRUPT, 2);
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pic_set_irq_handler(IRQN_AI_INTERRUPT, kpu_isr_handle, this);
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pic_set_irq_enable(IRQN_AI_INTERRUPT, 1);
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@ -186,7 +188,7 @@ public:
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}
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}
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done_flag_ = 0;
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dma_close(dma_ch_);
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return 0;
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}
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@ -342,6 +344,7 @@ private:
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void kpu_input_dma(const kpu_layer_argument_t *layer, const uint8_t *src)
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{
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configASSERT(!is_memory_cache((uintptr_t)src));
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uint64_t input_size = layer->kernel_calc_type_cfg.data.channel_switch_addr * 64 * (layer->image_channel_num.data.i_ch_num + 1);
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dma_set_request_source(dma_ch_, dma_req_);
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@ -805,7 +808,7 @@ private:
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kpu_.interrupt_mask.reg = 0b111;
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layer.dma_parameter.data.send_data_out = 1;
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dma_set_request_source(dma_ch_, dma_req_);
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dma_transmit_async(dma_ch_, (void *)(&kpu_.fifo_data_out), dest-0x40000000, 0, 1, sizeof(uint64_t), (layer.dma_parameter.data.dma_total_byte + 8) / 8, 8, completion_event_);
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dma_transmit_async(dma_ch_, (void *)(&kpu_.fifo_data_out), (void *)dest, 0, 1, sizeof(uint64_t), (layer.dma_parameter.data.dma_total_byte + 8) / 8, 8, completion_event_);
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}
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else
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{
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@ -21,7 +21,7 @@
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using namespace sys;
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static volatile plic_t &plic = *reinterpret_cast<volatile plic_t *>(PLIC_BASE_ADDR);
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volatile plic_t &plic = *reinterpret_cast<volatile plic_t *>(PLIC_BASE_ADDR);
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class k_plic_driver : public pic_driver, public static_object, public free_object_access
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{
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@ -27,6 +27,7 @@
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#include <sysctl.h>
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#include <utility.h>
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#include <printf.h>
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#include <plic.h>
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using namespace sys;
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@ -35,6 +36,7 @@ using namespace sys;
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/* SPI Controller */
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extern volatile plic_t plic;
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#define TMOD_MASK (3 << tmod_off_)
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#define TMOD_VALUE(value) (value << tmod_off_)
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#define COMMON_ENTRY \
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@ -711,9 +713,15 @@ int k_spi_driver::read(k_spi_device_driver &device, gsl::span<uint8_t> buffer)
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write_inst_addr(spi_.dr, &buffer_it, device.addr_width_);
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spi_.ser = device.chip_select_mask_;
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uint32_t spi_mstatus_t = 0;
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if(pdFALSE == xSemaphoreTake(event_read, SPI_DMA_BLOCK_TIME))
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{
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printk("read:context.flag = %d \n", context_.flag);
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asm("csrr %0, mstatus"
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: "=r"(spi_mstatus_t)
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:
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: "cc");
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printk("read:context.flag = %d plic.pending_bits.u32[0]=0x%x plic.pending_bits.u32[1]=0x%x\n", context_.flag,plic.pending_bits.u32[0],plic.pending_bits.u32[1]);
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printk("read:spi_mstatus_t = 0x%x claim_complete=%d \n", spi_mstatus_t, plic.targets.target[0].claim_complete);
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}
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context_.flag = 0;
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dma_test_async(dma_read, &context_);
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@ -789,7 +797,13 @@ int k_spi_driver::write(k_spi_device_driver &device, gsl::span<const uint8_t> bu
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spi_.ser = device.chip_select_mask_;
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if(pdFALSE == xSemaphoreTake(event_write, SPI_DMA_BLOCK_TIME))
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{
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printk("write:context.flag = %d \n", context_.flag);
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uint32_t spi_mstatus_t = 0;
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asm("csrr %0, mstatus"
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: "=r"(spi_mstatus_t)
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:
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: "cc");
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printk("write:context.flag = %d plic.pending_bits.u32[0]=0x%x plic.pending_bits.u32[1]=0x%x\n", context_.flag,plic.pending_bits.u32[0],plic.pending_bits.u32[1]);
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printk("write:spi_mstatus_t=0x%x claim_complete=%d \n", spi_mstatus_t, plic.targets.target[0].claim_complete);
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}
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context_.flag = 0;
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dma_test_async(dma_write, &context_);
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@ -93,7 +93,7 @@ enum
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/* memory */
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#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 1024 )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 2*1024 * 1024 ) )
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#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024 * 1024 ) )
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#define configSUPPORT_STATIC_ALLOCATION 1
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#define configSUPPORT_DYNAMIC_ALLOCATION 1
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@ -116,8 +116,10 @@ static void draw_edge(uint32_t *gram, obj_info_t *obj_info, uint32_t index, uint
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}
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}
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#define TEST_START_ADDR (0x300000U)
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#define TEST_NUMBER (0x100U)
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#define TEST_START_ADDR (0xB00000U)
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#define TEST_START_ADDR2 (0x100000U)
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#define TEST_NUMBER (0x1000U)
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uint8_t data_buf_send[TEST_NUMBER];
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uint8_t *data_buf_recv;
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handle_t spi3;
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@ -145,24 +147,42 @@ void vTask1()
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{
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int32_t index = 0;
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int32_t page_addr = TEST_START_ADDR;
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for (index = 0; index < TEST_NUMBER; index++)
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data_buf_send[index] = (uint8_t)(index);
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struct timeval get_time[2];
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while (1)
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{
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task1_flag = 1;
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//configASSERT(xSemaphoreTake(event_read, 200) == pdTRUE);
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_lock_acquire_recursive(&flash_lock);
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gettimeofday(&get_time[0], NULL);
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#if 0
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fseek(stream,0,SEEK_SET);
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fwrite(msg, 1, strlen(msg)+1, stream);
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#else
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if(page_addr >= 0x1000000 - TEST_NUMBER)
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{
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page_addr = TEST_START_ADDR;
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}
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task1_flag = 2;
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w25qxx_write_data(page_addr, data_buf_send, TEST_NUMBER);
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w25qxx_read_data(page_addr, data_buf_recv, TEST_NUMBER);
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for (index = 0; index < TEST_NUMBER; index++)
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{
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if (data_buf_recv[index] != (uint8_t)index) {
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printk("task1 Read err:0x%x 0x%x\n", data_buf_recv[index], index);
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index += 0x100;
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}
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}
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page_addr += TEST_NUMBER;
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task1_flag = 3;
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#endif
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gettimeofday(&get_time[1], NULL);;
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//printf("vtask1:%f ms \n", ((get_time[1].tv_sec - get_time[0].tv_sec)*1000*1000 + (get_time[1].tv_usec - get_time[0].tv_usec))/1000.0);
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//xSemaphoreGive(event_read);
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_lock_release_recursive(&flash_lock);
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task1_flag = 4;
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vTaskDelay(50 / portTICK_PERIOD_MS);
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}
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@ -171,40 +191,44 @@ void vTask1()
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void vTask2()
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{
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int32_t index = 0;
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int32_t page_addr = TEST_START_ADDR;
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data_buf_recv = iomem_malloc(TEST_NUMBER);
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while (1)
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int32_t page_addr = TEST_START_ADDR2;
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struct timeval get_time[2];
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while (1)
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{
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task2_flag = 1;
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//configASSERT(xSemaphoreTake(event_read, 200) == pdTRUE);
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_lock_acquire_recursive(&flash_lock);
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for (index = 0; index < TEST_NUMBER; index++)
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data_buf_recv[index] = 0;
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gettimeofday(&get_time[0], NULL);
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#if 0
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fseek(stream,0,SEEK_SET);
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fread(buffer, 1, strlen(msg)+1, stream);
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printk("test syscalls buffer : %s\n", buffer);
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xSemaphoreGive(event_read);
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fwrite(msg, 1, strlen(msg)+1, stream);
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#else
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if(page_addr >= 0xA00000 - TEST_NUMBER)
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{
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page_addr = TEST_START_ADDR2;
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}
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task2_flag = 2;
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w25qxx_read_data(page_addr, data_buf_recv, TEST_NUMBER);
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task2_flag = 3;
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w25qxx_write_data(page_addr, data_buf_send, TEST_NUMBER);
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w25qxx_read_data(page_addr, data_buf_recv, TEST_NUMBER);
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//xSemaphoreGive(event_read);
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_lock_release_recursive(&flash_lock);
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for (index = 0; index < TEST_NUMBER; index++)
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{
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if (data_buf_recv[index] != (uint8_t)index) {
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printf("Read err\n");
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while(1)
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;
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printk("task2 Read err:0x%x 0x%x\n", data_buf_recv[index], index);
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index += 0x100;
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}
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}
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//printf("%X Test OK\n", page_addr);
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task2_flag = 4;
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page_addr += TEST_NUMBER;
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task2_flag = 3;
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#endif
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gettimeofday(&get_time[1], NULL);;
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//printf("vtask2:%f ms \n", ((get_time[1].tv_sec - get_time[0].tv_sec)*1000*1000 + (get_time[1].tv_usec - get_time[0].tv_usec))/1000.0);
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//xSemaphoreGive(event_read);
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_lock_release_recursive(&flash_lock);
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task2_flag = 4;
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vTaskDelay(50 / portTICK_PERIOD_MS);
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}
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}
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@ -234,10 +258,12 @@ void detect()
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face_detect_rl.input = output;
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region_layer_run(&face_detect_rl, &face_detect_info);
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for (uint32_t face_cnt = 0; face_cnt < face_detect_info.obj_number; face_cnt++) {
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draw_edge(lcd_gram, &face_detect_info, face_cnt, RED);
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}
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//for (uint32_t face_cnt = 0; face_cnt < face_detect_info.obj_number; face_cnt++) {
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// draw_edge(lcd_gram, &face_detect_info, face_cnt, RED);
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//}
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#endif
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if(face_detect_info.obj_number)
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printk("=====>face detect %d \n", face_detect_info.obj_number);
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if(!task1_flag)
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printk("==========>%d %d \n", task1_flag, task2_flag);
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if(!task2_flag)
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@ -281,6 +307,11 @@ int main(void)
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struct timeval get_time[2];
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gettimeofday(&get_time[0], NULL);
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//event_read = xSemaphoreCreateMutex();
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data_buf_recv = iomem_malloc(TEST_NUMBER);
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for (uint32_t index = 0; index < TEST_NUMBER; index++)
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{
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data_buf_send[index] = (uint8_t)(index);
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}
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#if LOAD_KMODEL_FROM_FLASH
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model_data = (uint8_t *)iomem_malloc(KMODEL_SIZE);
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#endif
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