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kendryte-freertos-sdk
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Delete Debug

pull/60/head
xiangbingj 2019-10-26 14:35:44 +08:00
parent 5df96cd571
commit c30f67ee92
2 changed files with 14 additions and 49 deletions
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38
lib/bsp/device/kpu.cpp Normal file → Executable file
View File

@ -47,22 +47,15 @@ class k_model_context : public heap_object, public free_object_access
public:
k_model_context(uint8_t *buffer)
{
uint8_t *buffer_iomem;
#if FIX_CACHE
if(is_memory_cache((uintptr_t)buffer))
{
buffer_iomem = (uint8_t *)((uintptr_t)buffer - 0x40000000);
}
else
configASSERT(!is_memory_cache((uintptr_t)buffer));
#endif
{
buffer_iomem = buffer;
}
uintptr_t base_addr = (uintptr_t)buffer_iomem;
const kpu_model_header_t *header = (const kpu_model_header_t *)buffer_iomem;
uintptr_t base_addr = (uintptr_t)buffer;
const kpu_model_header_t *header = (const kpu_model_header_t *)buffer;
if (header->version == 3 && header->arch == 0)
{
model_buffer_ = buffer_iomem;
model_buffer_ = buffer;
output_count_ = header->output_count;
outputs_ = (const kpu_model_output_t *)(base_addr + sizeof(kpu_model_header_t));
layer_headers_ = (const kpu_model_layer_header_t *)((uintptr_t)outputs_ + sizeof(kpu_model_output_t) * output_count_);
@ -353,11 +346,7 @@ private:
uint64_t input_size = layer->kernel_calc_type_cfg.data.channel_switch_addr * 64 * (layer->image_channel_num.data.i_ch_num + 1);
dma_set_request_source(dma_ch_, dma_req_);
#if PRINT_DMA_CH
dma_test_async(dma_ch_, &context_);
printk("kpu intput: dma=%d \n", context_.channel);
#endif
dma_transmit_async(dma_ch_, src, (void *)(uintptr_t)((uint8_t *)AI_IO_BASE_ADDR + layer->image_addr.data.image_src_addr * 64), 1, 1, sizeof(uint64_t), input_size / 8, 16, completion_event_);
}
@ -748,9 +737,10 @@ private:
float *dest = (float *)(ctx_.main_buffer + arg->main_mem_out_address);
uint32_t in_channels = arg->in_channels, out_channels = arg->out_channels, ic, oc;
float *weights, *bias;
memcpy(weights, arg->weights, sizeof(float));
memcpy(bias, arg->weights + in_channels * out_channels, sizeof(float));
float *weights = (float *)malloc(out_channels * in_channels);
float *bias = (float *)malloc(out_channels);
memcpy(weights, arg->weights, out_channels * in_channels * sizeof(float));
memcpy(bias, arg->weights + in_channels * out_channels, out_channels * sizeof(float));
for (oc = 0; oc < out_channels; oc++)
{
@ -818,12 +808,7 @@ private:
kpu_.interrupt_mask.reg = 0b111;
layer.dma_parameter.data.send_data_out = 1;
dma_set_request_source(dma_ch_, dma_req_);
#if PRINT_DMA_CH
context_.flag = 0;
dma_test_async(dma_ch_, &context_);
printk("kpu output: dma=%d \n", context_.channel);
#endif
dest_len_ = (layer.dma_parameter.data.dma_total_byte + 8) / 8 * sizeof(uint64_t);
dest_kpu_ = ctx_.main_buffer + arg->main_mem_out_address;
@ -1068,7 +1053,6 @@ private:
uint8_t done_flag_ = 0;
kpu_model_context_t ctx_;
test_context_t context_;
uint8_t *dest_kpu_;
uint8_t *dest_io_;
size_t dest_len_;

25
lib/bsp/device/spi.cpp Normal file → Executable file
View File

@ -27,7 +27,6 @@
#include <sysctl.h>
#include <utility.h>
#include <printf.h>
#include <plic.h>
using namespace sys;
@ -36,7 +35,6 @@ using namespace sys;
/* SPI Controller */
extern volatile plic_t plic;
#define TMOD_MASK (3 << tmod_off_)
#define TMOD_VALUE(value) (value << tmod_off_)
#define COMMON_ENTRY \
@ -713,16 +711,8 @@ int k_spi_driver::read(k_spi_device_driver &device, gsl::span<uint8_t> buffer)
write_inst_addr(spi_.dr, &buffer_it, device.addr_width_);
spi_.ser = device.chip_select_mask_;
uint32_t spi_mstatus_t = 0;
if(pdFALSE == xSemaphoreTake(event_read, SPI_DMA_BLOCK_TIME))
{
asm("csrr %0, mstatus"
: "=r"(spi_mstatus_t)
:
: "cc");
printk("read:context.flag = %d plic.pending_bits.u32[0]=0x%x plic.pending_bits.u32[1]=0x%x\n", context_.flag,plic.pending_bits.u32[0],plic.pending_bits.u32[1]);
printk("read:spi_mstatus_t = 0x%x claim_complete=%d \n", spi_mstatus_t, plic.targets.target[0].claim_complete);
}
configASSERT(pdTRUE == xSemaphoreTake(event_read, SPI_DMA_BLOCK_TIME));
context_.flag = 0;
dma_test_async(dma_read, &context_);
dma_close(dma_read);
@ -795,16 +785,7 @@ int k_spi_driver::write(k_spi_device_driver &device, gsl::span<const uint8_t> bu
dma_test_async(dma_write, &context_);
dma_transmit_async(dma_write, buffer_write, &spi_.dr[0], 1, 0, device.buffer_width_, tx_frames, 4, event_write);
spi_.ser = device.chip_select_mask_;
if(pdFALSE == xSemaphoreTake(event_write, SPI_DMA_BLOCK_TIME))
{
uint32_t spi_mstatus_t = 0;
asm("csrr %0, mstatus"
: "=r"(spi_mstatus_t)
:
: "cc");
printk("write:context.flag = %d plic.pending_bits.u32[0]=0x%x plic.pending_bits.u32[1]=0x%x\n", context_.flag,plic.pending_bits.u32[0],plic.pending_bits.u32[1]);
printk("write:spi_mstatus_t=0x%x claim_complete=%d \n", spi_mstatus_t, plic.targets.target[0].claim_complete);
}
configASSERT(pdTRUE == xSemaphoreTake(event_write, SPI_DMA_BLOCK_TIME));
context_.flag = 0;
dma_test_async(dma_write, &context_);
dma_close(dma_write);