124 lines
4.0 KiB
C
124 lines
4.0 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <FreeRTOS.h>
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#include <driver.h>
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#include <plic.h>
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#include <semphr.h>
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#include <stdio.h>
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#include <sysctl.h>
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#define plic ((volatile struct plic_t*)PLIC_BASE_ADDR)
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static void plic_install(void* userdata)
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{
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int i = 0;
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size_t hart_id;
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for (hart_id = 0; hart_id < PLIC_NUM_HARTS; hart_id++)
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{
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/* Disable all interrupts for the current hart. */
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for (i = 0; i < ((PLIC_NUM_SOURCES + 32u) / 32u); i++)
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plic->target_enables.target[hart_id].enable[i] = 0;
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}
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/* Set priorities to zero. */
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for (i = 0; i < PLIC_NUM_SOURCES; i++)
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plic->source_priorities.priority[i] = 0;
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/* Set the threshold to zero. */
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for (hart_id = 0; hart_id < PLIC_NUM_HARTS; hart_id++)
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{
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plic->targets.target[hart_id].priority_threshold = 0;
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}
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/* Enable machine external interrupts. */
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set_csr(mie, MIP_MEIP);
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}
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static int plic_open(void* userdata)
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{
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return 1;
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}
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static void plic_close(void* userdata)
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{
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}
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static void plic_set_irq_enable(size_t irq, int enable, void* userdata)
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{
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configASSERT(irq <= PLIC_NUM_SOURCES);
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/* Get current enable bit array by IRQ number */
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uint32_t current = plic->target_enables.target[0].enable[irq / 32];
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/* Set enable bit in enable bit array */
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if (enable)
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current |= (uint32_t)1 << (irq % 32);
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else
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current &= ~((uint32_t)1 << (irq % 32));
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/* Write back the enable bit array */
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plic->target_enables.target[0].enable[irq / 32] = current;
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}
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static void plic_set_irq_priority(size_t irq, size_t priority, void* userdata)
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{
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configASSERT(irq <= PLIC_NUM_SOURCES);
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/* Set interrupt priority by IRQ number */
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plic->source_priorities.priority[irq] = priority;
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}
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static void plic_complete_irq(uint32_t source)
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{
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unsigned long hart_id = xPortGetProcessorId();
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/* Perform IRQ complete */
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plic->targets.target[hart_id].claim_complete = source;
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}
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/*Entry Point for PLIC Interrupt Handler*/
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uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
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{
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/**
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* After the highest-priority pending interrupt is claimed by a target
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* and the corresponding IP bit is cleared, other lower-priority
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* pending interrupts might then become visible to the target, and so
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* the PLIC EIP bit might not be cleared after a claim. The interrupt
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* handler can check the local meip/heip/seip/ueip bits before exiting
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* the handler, to allow more efficient service of other interrupts
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* without first restoring the interrupted context and taking another
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* interrupt trap.
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*/
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if (read_csr(mip) & MIP_MEIP)
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{
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/* Get current hart id */
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uint64_t hart_id = read_csr(mhartid);
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uint64_t ie_flag = read_csr(mie);
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uint32_t int_num = plic->targets.target[hart_id].claim_complete;
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uint32_t int_threshold = plic->targets.target[hart_id].priority_threshold;
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plic->targets.target[hart_id].priority_threshold = plic->source_priorities.priority[int_num];
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clear_csr(mie, MIP_MTIP | MIP_MSIP);
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set_csr(mstatus, MSTATUS_MIE);
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kernel_iface_pic_on_irq(int_num);
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plic_complete_irq(int_num);
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clear_csr(mstatus, MSTATUS_MIE);
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set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP);
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write_csr(mie, ie_flag);
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plic->targets.target[hart_id].priority_threshold = int_threshold;
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}
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return epc;
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}
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const pic_driver_t g_pic_driver_plic0 = {{NULL, plic_install, plic_open, plic_close}, plic_set_irq_enable, plic_set_irq_priority};
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