190 lines
5.9 KiB
C
190 lines
5.9 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief The CLINT block holds memory-mapped control and status registers
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* associated with local interrupts for a Coreplex.
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*
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* @note CLINT RAM Layout
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*
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* | Address -| Description |
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* |------------|---------------------------------|
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* | 0x02000000 | msip for hart 0 |
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* | 0x02000004 | msip for hart 1 |
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* | ... | ... |
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* | 0x02003FF8 | msip for hart 4094 |
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* | | |
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* | 0x02004000 | mtimecmp for hart 0 |
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* | 0x02004008 | mtimecmp for hart 1 |
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* | ... | ... |
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* | 0x0200BFF0 | mtimecmp For hart 4094 |
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* | 0x0200BFF8 | mtime |
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* | | |
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* | 0x0200C000 | Reserved |
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* | ... | ... |
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* | 0x0200EFFC | Reserved |
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*/
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#ifndef _DRIVER_CLINT_H
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#define _DRIVER_CLINT_H
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#include <stddef.h>
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#include <stdint.h>
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#include "platform.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/* Register address offsets */
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#define CLINT_MSIP (0x0000)
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#define CLINT_MSIP_SIZE (0x4)
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#define CLINT_MTIMECMP (0x4000)
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#define CLINT_MTIMECMP_SIZE (0x8)
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#define CLINT_MTIME (0xBFF8)
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#define CLINT_MTIME_SIZE (0x8)
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/* Max number of cores */
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#define CLINT_MAX_HARTS (4095)
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/* Real number of cores */
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#define CLINT_NUM_HARTS (2)
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/* Clock frequency division factor */
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#define CLINT_CLOCK_DIV (50)
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/* clang-format on */
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/**
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* @brief MSIP Registers
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*
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* Machine-mode software interrupts are generated by writing to a
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* per-hart memory-mapped control register. The msip registers are
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* 32-bit wide WARL registers, where the LSB is reflected in the
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* msip bit of the associated hart’s mip register. Other bits in
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* the msip registers are hardwired to zero. The mapping supports
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* up to 4095 machine-mode harts.
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*/
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struct clint_msip_t
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{
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uint32_t msip : 1; /*!< Bit 0 is msip */
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uint32_t zero : 31; /*!< Bits [32:1] is 0 */
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} __attribute__((packed, aligned(4)));
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/**
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* @brief Timer compare Registers Machine-mode timer interrupts are
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* generated by a real-time counter and a per-hart comparator. The
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* mtime register is a 64-bit read-only register that contains the
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* current value of the real-time counter. Each mtimecmp register
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* holds its hart’s time comparator. A timer interrupt is pending
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* whenever mtime is greater than or equal to the value in a
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* hart’s mtimecmp register. The timer interrupt is reflected in
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* the mtip bit of the associated hart’s mip register.
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*/
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typedef uint64_t clint_mtimecmp_t;
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/**
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* @brief Timer Registers
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*
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* The mtime register has a 64-bit precision on all RV32, RV64,
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* and RV128 systems. Platforms provide a 64-bit memory-mapped
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* machine-mode timer compare register (mtimecmp), which causes a
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* timer interrupt to be posted when the mtime register contains a
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* value greater than or equal to the value in the mtimecmp
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* register. The interrupt remains posted until it is cleared by
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* writing the mtimecmp register. The interrupt will only be taken
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* if interrupts are enabled and the MTIE bit is set in the mie
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* register.
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*/
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typedef uint64_t clint_mtime_t;
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/**
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* @brief CLINT object
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*
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* Coreplex-Local INTerrupts, which includes software interrupts,
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* local timer interrupts, and other interrupts routed directly to
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* a core.
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*/
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struct clint_t
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{
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/* 0x0000 to 0x3FF8, MSIP Registers */
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struct clint_msip_t msip[CLINT_MAX_HARTS];
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/* Resverd space, do not use */
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uint32_t resv0;
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/* 0x4000 to 0xBFF0, Timer Compare Registers */
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clint_mtimecmp_t mtimecmp[CLINT_MAX_HARTS];
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/* 0xBFF8, Time Register */
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clint_mtime_t mtime;
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} __attribute__((packed, aligned(4)));
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/**
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* @brief Clint object instanse
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*/
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extern volatile struct clint_t* const clint;
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/**
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* @brief Initialize local interprocessor interrupt
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int clint_ipi_init(void);
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/**
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* @brief Enable local interprocessor interrupt
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int clint_ipi_enable(void);
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/**
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* @brief Disable local interprocessor interrupt
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int clint_ipi_disable(void);
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/**
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* @brief Send local interprocessor interrupt to core by hart id
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*
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* @param[in] hart_id The hart identifier
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int clint_ipi_send(size_t hart_id);
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/**
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* @brief Clear local interprocessor interrupt
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*
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* @param[in] hart_id The hart identifier
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*
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* @return result
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* - 1 An IPI was pending
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* - 0 Non IPI was pending
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* - -1 Fail
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*/
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int clint_ipi_clear(size_t hart_id);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_CLINT_H */
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