108 lines
4.5 KiB
C
108 lines
4.5 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_SPI_H
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#define _DRIVER_SPI_H
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#include <stdint.h>
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#include <stddef.h>
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#include "dmac.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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struct spi_t
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{
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/* SPI Control Register 0 (0x00)*/
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volatile uint32_t ctrlr0;
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/* SPI Control Register 1 (0x04)*/
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volatile uint32_t ctrlr1;
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/* SPI Enable Register (0x08)*/
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volatile uint32_t ssienr;
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/* SPI Microwire Control Register (0x0c)*/
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volatile uint32_t mwcr;
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/* SPI Slave Enable Register (0x10)*/
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volatile uint32_t ser;
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/* SPI Baud Rate Select (0x14)*/
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volatile uint32_t baudr;
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/* SPI Transmit FIFO Threshold Level (0x18)*/
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volatile uint32_t txftlr;
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/* SPI Receive FIFO Threshold Level (0x1c)*/
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volatile uint32_t rxftlr;
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/* SPI Transmit FIFO Level Register (0x20)*/
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volatile uint32_t txflr;
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/* SPI Receive FIFO Level Register (0x24)*/
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volatile uint32_t rxflr;
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/* SPI Status Register (0x28)*/
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volatile uint32_t sr;
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/* SPI Interrupt Mask Register (0x2c)*/
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volatile uint32_t imr;
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/* SPI Interrupt Status Register (0x30)*/
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volatile uint32_t isr;
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/* SPI Raw Interrupt Status Register (0x34)*/
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volatile uint32_t risr;
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/* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38)*/
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volatile uint32_t txoicr;
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/* SPI Receive FIFO Overflow Interrupt Clear Register (0x3c)*/
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volatile uint32_t rxoicr;
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/* SPI Receive FIFO Underflow Interrupt Clear Register (0x40)*/
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volatile uint32_t rxuicr;
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/* SPI Multi-Master Interrupt Clear Register (0x44)*/
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volatile uint32_t msticr;
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/* SPI Interrupt Clear Register (0x48)*/
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volatile uint32_t icr;
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/* SPI DMA Control Register (0x4c)*/
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volatile uint32_t dmacr;
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/* SPI DMA Transmit Data Level (0x50)*/
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volatile uint32_t dmatdlr;
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/* SPI DMA Receive Data Level (0x54)*/
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volatile uint32_t dmardlr;
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/* SPI Identification Register (0x58)*/
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volatile uint32_t idr;
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/* SPI DWC_ssi component version (0x5c)*/
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volatile uint32_t ssic_version_id;
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/* SPI Data Register 0-36 (0x60 -- 0xec)*/
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volatile uint32_t dr[36];
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/* SPI RX Sample Delay Register (0xf0)*/
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volatile uint32_t rx_sample_delay;
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/* SPI SPI Control Register (0xf4)*/
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volatile uint32_t spi_ctrlr0;
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/* reserved (0xf8)*/
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volatile uint32_t resv;
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/* SPI XIP Mode bits (0xfc)*/
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volatile uint32_t xip_mode_bits;
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/* SPI XIP INCR transfer opcode (0x100)*/
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volatile uint32_t xip_incr_inst;
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/* SPI XIP WRAP transfer opcode (0x104)*/
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volatile uint32_t xip_wrap_inst;
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/* SPI XIP Control Register (0x108)*/
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volatile uint32_t xip_ctrl;
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/* SPI XIP Slave Enable Register (0x10c)*/
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volatile uint32_t xip_ser;
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/* SPI XIP Receive FIFO Overflow Interrupt Clear Register (0x110)*/
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volatile uint32_t xrxoicr;
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/* SPI XIP time out register for continuous transfers (0x114)*/
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volatile uint32_t xip_cnt_time_out;
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volatile uint32_t endian;
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} __attribute__((packed, aligned(4)));
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/* clang-format on */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_SPI_H */
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