100 lines
2.8 KiB
C
100 lines
2.8 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _BSP_PLATFORM_H
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#define _BSP_PLATFORM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/* Register base address */
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/* Under Coreplex */
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#define CLINT_BASE_ADDR (0x02000000U)
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#define PLIC_BASE_ADDR (0x0C000000U)
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/* Under TileLink */
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#define UARTHS_BASE_ADDR (0x38000000U)
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#define GPIOHS_BASE_ADDR (0x38001000U)
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/* Under AXI 64 bit */
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#define RAM_BASE_ADDR (0x80000000U)
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#define RAM_SIZE (6 * 1024 * 1024U)
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#define IO_BASE_ADDR (0x40000000U)
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#define IO_SIZE (6 * 1024 * 1024U)
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#define AI_RAM_BASE_ADDR (0x80600000U)
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#define AI_RAM_SIZE (2 * 1024 * 1024U)
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#define AI_IO_BASE_ADDR (0x40600000U)
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#define AI_IO_SIZE (2 * 1024 * 1024U)
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#define AI_BASE_ADDR (0x40800000U)
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#define AI_SIZE (12 * 1024 * 1024U)
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#define FFT_BASE_ADDR (0x42000000U)
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#define FFT_SIZE (4 * 1024 * 1024U)
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#define ROM_BASE_ADDR (0x88000000U)
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#define ROM_SIZE (128 * 1024U)
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/* Under AHB 32 bit */
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#define DMAC_BASE_ADDR (0x50000000U)
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/* Under APB1 32 bit */
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#define GPIO_BASE_ADDR (0x50200000U)
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#define UART1_BASE_ADDR (0x50210000U)
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#define UART2_BASE_ADDR (0x50220000U)
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#define UART3_BASE_ADDR (0x50230000U)
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#define SPI_SLAVE_BASE_ADDR (0x50240000U)
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#define I2S0_BASE_ADDR (0x50250000U)
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#define I2S1_BASE_ADDR (0x50260000U)
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#define I2S2_BASE_ADDR (0x50270000U)
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#define I2C0_BASE_ADDR (0x50280000U)
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#define I2C1_BASE_ADDR (0x50290000U)
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#define I2C2_BASE_ADDR (0x502A0000U)
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#define FPIOA_BASE_ADDR (0x502B0000U)
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#define SHA256_BASE_ADDR (0x502C0000U)
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#define TIMER0_BASE_ADDR (0x502D0000U)
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#define TIMER1_BASE_ADDR (0x502E0000U)
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#define TIMER2_BASE_ADDR (0x502F0000U)
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/* Under APB2 32 bit */
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#define WDT0_BASE_ADDR (0x50400000U)
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#define WDT1_BASE_ADDR (0x50410000U)
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#define OTP_BASE_ADDR (0x50420000U)
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#define DVP_BASE_ADDR (0x50430000U)
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#define SYSCTL_BASE_ADDR (0x50440000U)
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#define AES_BASE_ADDR (0x50450000U)
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#define RTC_BASE_ADDR (0x50460000U)
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/* Under APB3 32 bit */
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#define SPI0_BASE_ADDR (0x52000000U)
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#define SPI1_BASE_ADDR (0x53000000U)
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#define SPI3_BASE_ADDR (0x54000000U)
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/* clang-format on */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _BSP_PLATFORM_H */
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