1687 lines
48 KiB
C
1687 lines
48 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_DMAC_H
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#define _DRIVER_DMAC_H
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#include <stdint.h>
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#include "io.h"
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#include "platform.h"
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#include "stdbool.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMAC */
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#define DMAC_CHANNEL_COUNT (DMAC_CHANNEL_MAX)
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#define LAST_ROW (-1)
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typedef enum _dmac_channel_number
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{
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DMAC_CHANNEL0 = 0,
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DMAC_CHANNEL1 = 1,
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DMAC_CHANNEL2 = 2,
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DMAC_CHANNEL3 = 3,
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DMAC_CHANNEL4 = 4,
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DMAC_CHANNEL5 = 5,
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DMAC_CHANNEL_MAX
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} dmac_channel_number;
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typedef enum _dmac_src_dst_select
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{
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DMAC_SRC = 0x1,
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DMAC_DST = 0x2,
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DMAC_SRC_DST = 0x3
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} dmac_src_dst_select;
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typedef enum _state_value
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{
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clear = 0,
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set = 1
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} state_value;
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enum dmac_lock_bus_ch
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{
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DMAC_LOCK_BUS = 0x1,
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DMAC_LOCK_CHANNEL = 0x2,
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DMAC_LOCK_BUS_CH = 0x3
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};
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enum dmac_sw_hw_hs_select
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{
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DMAC_HS_HARDWARE = 0x0,
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DMAC_HS_SOFTWARE = 0x1
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};
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enum dmac_scatter_gather_param
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{
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DMAC_SG_COUNT = 0x0,
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DMAC_SG_INTERVAL = 0x1
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};
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enum dmac_irq
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{
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/* no interrupts */
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DMAC_IRQ_NONE = 0x00,
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/* transfer complete */
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DMAC_IRQ_TFR = 0x01,
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/* block transfer complete */
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DMAC_IRQ_BLOCK = 0x02,
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/* source transaction complete */
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DMAC_IRQ_SRCTRAN = 0x04,
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/* destination transaction complete */
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DMAC_IRQ_DSTTRAN = 0x08,
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/* error */
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DMAC_IRQ_ERR = 0x10,
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/* all interrupts */
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DMAC_IRQ_ALL = 0x1f
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};
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enum dmac_software_req
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{
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/* ReqSrcReq/ReqDstReq */
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DMAC_REQUEST = 0x1,
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/* SglReqSrcReq/SglReqDstReq */
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DMAC_SINGLE_REQUEST = 0x2,
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/* LstReqSrcReq/LstReqDstReq */
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DMAC_LAST_REQUEST = 0x4
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};
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enum dmac_master_number
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{
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DMAC_MASTER1 = 0x0,
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DMAC_MASTER2 = 0x1
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};
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enum dmac_transfer_flow
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{
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/* mem to mem - DMAC flow ctlr */
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DMAC_MEM2MEM_DMA = 0x0,
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/* mem to prf - DMAC flow ctlr */
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DMAC_MEM2PRF_DMA = 0x1,
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/* prf to mem - DMAC flow ctlr */
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DMAC_PRF2MEM_DMA = 0x2,
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/* prf to prf - DMAC flow ctlr */
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DMAC_PRF2PRF_DMA = 0x3,
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/* prf to mem - periph flow ctlr */
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DMAC_PRF2MEM_PRF = 0x4,
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/* prf to prf - source flow ctlr */
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DMAC_PRF2PRF_SRCPRF = 0x5,
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/* mem to prf - periph flow ctlr */
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DMAC_MEM2PRF_PRF = 0x6,
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/* prf to prf - dest flow ctlr */
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DMAC_PRF2PRF_DSTPRF = 0x7
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};
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enum dmac_burst_trans_length
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{
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DMAC_MSIZE_1 = 0x0,
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DMAC_MSIZE_4 = 0x1,
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DMAC_MSIZE_8 = 0x2,
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DMAC_MSIZE_16 = 0x3,
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DMAC_MSIZE_32 = 0x4,
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DMAC_MSIZE_64 = 0x5,
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DMAC_MSIZE_128 = 0x6,
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DMAC_MSIZE_256 = 0x7
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};
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enum dmac_address_increment
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{
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DMAC_ADDR_INCREMENT = 0x0,
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DMAC_ADDR_NOCHANGE = 0x1
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};
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enum dmac_transfer_width
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{
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DMAC_TRANS_WIDTH_8 = 0x0,
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DMAC_TRANS_WIDTH_16 = 0x1,
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DMAC_TRANS_WIDTH_32 = 0x2,
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DMAC_TRANS_WIDTH_64 = 0x3,
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DMAC_TRANS_WIDTH_128 = 0x4,
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DMAC_TRANS_WIDTH_256 = 0x5
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};
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enum dmac_hs_interface
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{
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DMAC_HS_IF0 = 0x0,
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DMAC_HS_IF1 = 0x1,
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DMAC_HS_IF2 = 0x2,
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DMAC_HS_IF3 = 0x3,
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DMAC_HS_IF4 = 0x4,
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DMAC_HS_IF5 = 0x5,
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DMAC_HS_IF6 = 0x6,
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DMAC_HS_IF7 = 0x7,
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DMAC_HS_IF8 = 0x8,
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DMAC_HS_IF9 = 0x9,
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DMAC_HS_IF10 = 0xa,
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DMAC_HS_IF11 = 0xb,
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DMAC_HS_IF12 = 0xc,
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DMAC_HS_IF13 = 0xd,
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DMAC_HS_IF14 = 0xe,
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DMAC_HS_IF15 = 0xf
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};
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enum dmac_multiblk_transfer_type
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{
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CONTIGUOUS = 0,
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RELOAD = 1,
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SHADOWREGISTER = 2,
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LINKEDLIST = 3
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};
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enum dmac_multiblk_type
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{
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DMAC_SRC_DST_CONTINUE = 0,
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DMAC_SRC_CONTINUE_DST_RELAOD = 2,
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DMAC_SRC_CONTINUE_DST_LINKEDLIST = 3,
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DMAC_SRC_RELOAD_DST_CONTINUE = 4,
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DMAC_SRC_RELOAD_DST_RELOAD = 5,
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DMAC_SRC_RELOAD_DST_LINKEDLIST = 6,
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DMAC_SRC_LINKEDLIST_DST_CONTINUE = 7,
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DMAC_SRC_LINKEDLIST_DST_RELOAD = 8,
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DMAC_SRC_LINKEDLIST_DST_LINKEDLIST = 9,
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DMAC_SRC_SHADOWREG_DST_CONTINUE = 10
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};
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enum dmac_transfer_type
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{
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DMAC_TRANSFER_ROW1 = 0x1,
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DMAC_TRANSFER_ROW2 = 0x2,
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DMAC_TRANSFER_ROW3 = 0x3,
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DMAC_TRANSFER_ROW4 = 0x4,
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DMAC_TRANSFER_ROW5 = 0x5,
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DMAC_TRANSFER_ROW6 = 0x6,
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DMAC_TRANSFER_ROW7 = 0x7,
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DMAC_TRANSFER_ROW8 = 0x8,
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DMAC_TRANSFER_ROW9 = 0x9,
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DMAC_TRANSFER_ROW10 = 0xa
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};
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enum dmac_prot_level
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{
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/* default prot level */
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DMAC_NONCACHE_NONBUFF_NONPRIV_OPCODE = 0x0,
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DMAC_NONCACHE_NONBUFF_NONPRIV_DATA = 0x1,
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DMAC_NONCACHE_NONBUFF_PRIV_OPCODE = 0x2,
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DMAC_NONCACHE_NONBUFF_PRIV_DATA = 0x3,
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DMAC_NONCACHE_BUFF_NONPRIV_OPCODE = 0x4,
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DMAC_NONCACHE_BUFF_NONPRIV_DATA = 0x5,
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DMAC_NONCACHE_BUFF_PRIV_OPCODE = 0x6,
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DMAC_NONCACHE_BUFF_PRIV_DATA = 0x7,
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DMAC_CACHE_NONBUFF_NONPRIV_OPCODE = 0x8,
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DMAC_CACHE_NONBUFF_NONPRIV_DATA = 0x9,
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DMAC_CACHE_NONBUFF_PRIV_OPCODE = 0xa,
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DMAC_CACHE_NONBUFF_PRIV_DATA = 0xb,
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DMAC_CACHE_BUFF_NONPRIV_OPCODE = 0xc,
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DMAC_CACHE_BUFF_NONPRIV_DATA = 0xd,
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DMAC_CACHE_BUFF_PRIV_OPCODE = 0xe,
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DMAC_CACHE_BUFF_PRIV_DATA = 0xf
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};
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enum dmac_fifo_mode
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{
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DMAC_FIFO_MODE_SINGLE = 0x0,
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DMAC_FIFO_MODE_HALF = 0x1
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};
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enum dw_dmac_flow_ctl_mode
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{
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DMAC_DATA_PREFETCH_ENABLED = 0x0,
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DMAC_DATA_PREFETCH_DISABLED = 0x1
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};
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enum dmac_polarity_level
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{
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DMAC_ACTIVE_HIGH = 0x0,
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DMAC_ACTIVE_LOW = 0x1
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};
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enum dmac_lock_level
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{
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DMAC_LOCK_LEVEL_DMA_TRANSFER = 0x0,
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DMAC_LOCK_LEVEL_BLOCK_TRANSFER = 0x1,
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DMAC_LOCK_LEVEL_TRANSACTION = 0x2
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};
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enum dmac_channel_priority
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{
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DMAC_PRIORITY_0 = 0x0,
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DMAC_PRIORITY_1 = 0x1,
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DMAC_PRIORITY_2 = 0x2,
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DMAC_PRIORITY_3 = 0x3,
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DMAC_PRIORITY_4 = 0x4,
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DMAC_PRIORITY_5 = 0x5,
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DMAC_PRIORITY_6 = 0x6,
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DMAC_PRIORITY_7 = 0x7
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};
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enum dmac_state
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{
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ZERO,
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ONE
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};
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enum dmca_common_int
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{
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SLVIF_COMMON_DEC_ERR = 0,
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SLVIF_COMMON_WR2RO_ERR = 1,
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SLVIF_COMMON_RD2WO_ERR = 2,
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SLVIF_COMMON__WRONHOLD_ERR = 3,
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SLVIF_UNDEFINED_DEC_ERR = 4,
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SLVIF_ALL_INT = 5
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};
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struct dmac_cfg_t
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{
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/**
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* Bit 0 is used to enable dmac
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t dmac_en : 1;
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/**
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* Bit 1 is used to glabally enable interrupt generation
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* 0x1 for enable interrupt, 0x0 for disable interrupt
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*/
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uint64_t int_en : 1;
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/* Bits [63:2] is reserved */
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uint64_t rsvd : 62;
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} __attribute__((packed, aligned(8)));
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union dmac_cfg_u
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{
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struct dmac_cfg_t cfg;
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uint64_t data;
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};
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struct damc_chen_t
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{
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/**
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* Bit 0 is used to enable channel 1
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch1_en : 1;
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/**
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* Bit 1 is used to enable channel 2
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch2_en : 1;
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/**
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* Bit 2 is used to enable channel 3
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch3_en : 1;
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/**
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* Bit 3 is used to enable channel 4
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch4_en : 1;
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/**
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* Bit 4 is used to enable channel 5
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch5_en : 1;
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/**
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* Bit 5 is used to enable channel 6
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch6_en : 1;
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/* Bits [7:6] is reserved */
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uint64_t rsvd1 : 2;
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/**
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* Bit 8 is write enable bit
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch1_en_we : 1;
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/**
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* Bit 9 is write enable bit
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch2_en_we : 1;
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/**
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* Bit 10 is write enable bit
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch3_en_we : 1;
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/**
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* Bit 11 is write enable bit
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch4_en_we : 1;
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/**
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* Bit 12 is write enable bit
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch5_en_we : 1;
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/**
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* Bit 13 is write enable bit
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* 0x1 for enable, 0x0 for disable
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*/
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uint64_t ch6_en_we : 1;
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/* Bits [15:14] is reserved */
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uint64_t rsvd2 : 2;
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/**
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* Bit 16 is susped reuest
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* 0x1 for request channel suspend
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* 0x0 for no channel suspend request
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*/
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uint64_t ch1_susp : 1;
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/**
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* Bit 17 is susped reuest
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* 0x1 for request channel suspend
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* 0x0 for no channel suspend request
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*/
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uint64_t ch2_susp : 1;
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/* Bit 18 is susped reuest
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* 0x1 for request channel suspend
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* 0x0 for no channel suspend request
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*/
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uint64_t ch3_susp : 1;
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/**
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* Bit 19 is susped reuest
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* 0x1 for request channel suspend
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* 0x0 for no channel suspend request
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*/
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uint64_t ch4_susp : 1;
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/**
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* Bit 20 is susped reuest
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* 0x1 for request channel suspend
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* 0x0 for no channel suspend request
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*/
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uint64_t ch5_susp : 1;
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/**
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* Bit 21 is susped reuest
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* 0x1 for request channel suspend
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* 0x0 for no channel suspend request
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*/
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uint64_t ch6_susp : 1;
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/* Bits [23:22] is reserved */
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uint64_t rsvd3 : 2;
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/**
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* Bit 24 is write enable to the channel suspend bit
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* 0x1 for enable write to CH1_SUSP bit
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* 0x0 for disable write to CH1_SUSP bit
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*/
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uint64_t ch1_susp_we : 1;
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/**
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* Bit 25 is write enable to the channel suspend bit
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* 0x1 for enable write to CH2_SUSP bit
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* 0x0 for disable write to CH2_SUSP bit
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*/
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uint64_t ch2_susp_we : 1;
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/**
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* Bit 26 is write enable to the channel suspend bit
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* 0x1 for enable write to CH3_SUSP bit
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* 0x0 for disable write to CH3_SUSP bit
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*/
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uint64_t ch3_susp_we : 1;
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/**
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* Bit 27 is write enable to the channel suspend bit
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* 0x1 for enable write to CH4_SUSP bit
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* 0x0 for disable write to CH4_SUSP bit
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*/
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uint64_t ch4_susp_we : 1;
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/**
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* Bit 28 is write enable to the channel suspend bit
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* 0x1 for enable write to CH5_SUSP bit
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* 0x0 for disable write to CH5_SUSP bit
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*/
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uint64_t ch5_susp_we : 1;
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/**
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* Bit 29 is write enable to the channel suspend bit
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* 0x1 for enable write to CH6_SUSP bit
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* 0x0 for disable write to CH6_SUSP bit
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*/
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uint64_t ch6_susp_we : 1;
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/* Bits [31:30] is reserved */
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uint64_t rsvd4 : 2;
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/**
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* Bit 32 is channel-1 abort requst bit
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* 0x1 for request for channnel abort
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* 0x0 for no channel abort request
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*/
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uint64_t ch1_abort : 1;
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/**
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* Bit 33 is channel-2 abort requst bit
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* 0x1 for request for channnel abort
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* 0x0 for no channel abort request
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*/
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uint64_t ch2_abort : 1;
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/**
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* Bit 34 is channel-3 abort requst bit
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* 0x1 for request for channnel abort
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* 0x0 for no channel abort request
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*/
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uint64_t ch3_abort : 1;
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/**
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* Bit 35 is channel-4 abort requst bit
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* 0x1 for request for channnel abort
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* 0x0 for no channel abort request
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*/
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uint64_t ch4_abort : 1;
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/**
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* Bit 36 is channel-5 abort requst bit
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* 0x1 for request for channnel abort
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* 0x0 for no channel abort request
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*/
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uint64_t ch5_abort : 1;
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/**
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* Bit 37 is channel-6 abort requst bit
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* 0x1 for request for channnel abort
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* 0x0 for no channel abort request
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*/
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uint64_t ch6_abort : 1;
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/* Bits [39:38] is reserved */
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uint64_t rsvd5 : 2;
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/**
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* Bit 40 is ued to write enable channel-1 abort bit
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* 0x1 for enable write to CH1_ABORT bit
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* 0x0 for disable write to CH1_ABORT bit
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*/
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uint64_t ch1_abort_we : 1;
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/**
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* Bit 41 is ued to write enable channel-2 abort bit
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* 0x1 for enable write to CH2_ABORT bit
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* 0x0 for disable write to CH2_ABORT bit
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*/
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uint64_t ch2_abort_we : 1;
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/**
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* Bit 42 is ued to write enable channel-3 abort bit
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* 0x1 for enable write to CH3_ABORT bit
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* 0x0 for disable write to CH3_ABORT bit
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*/
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uint64_t ch3_abort_we : 1;
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/**
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* Bit 43 is ued to write enable channel-4 abort bit
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* 0x1 for enable write to CH4_ABORT bit
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* 0x0 for disable write to CH4_ABORT bit
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*/
|
|
uint64_t ch4_abort_we : 1;
|
|
/**
|
|
* Bit 44 is ued to write enable channel-5 abort bit
|
|
* 0x1 for enable write to CH5_ABORT bit
|
|
* 0x0 for disable write to CH5_ABORT bit
|
|
*/
|
|
uint64_t ch5_abort_we : 1;
|
|
/**
|
|
* Bit 45 is ued to write enable channel-6 abort bit
|
|
* 0x1 for enable write to CH6_ABORT bit
|
|
* 0x0 for disable write to CH6_ABORT bit
|
|
*/
|
|
uint64_t ch6_abort_we : 1;
|
|
/* Bits [47:46] is reserved */
|
|
uint64_t rsvd6 : 2;
|
|
/* Bits [63:48] is reserved */
|
|
uint64_t rsvd7 : 16;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_chen_u
|
|
{
|
|
struct damc_chen_t dmac_chen;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_intstatus_t
|
|
{
|
|
/**
|
|
* Bit 0 is channel 1 interrupt bit
|
|
* 0x1 for channel 1 interrupt active
|
|
* 0x0 for channel 1 interrupt inactive
|
|
*/
|
|
uint64_t ch1_intstat : 1;
|
|
/**
|
|
* Bit 1 is channel 1 interrupt bit
|
|
* 0x1 for channel 2 interrupt active
|
|
* 0x0 for channel 2 interrupt inactive
|
|
*/
|
|
uint64_t ch2_intstat : 1;
|
|
/**
|
|
* Bit 2 is channel 3 interrupt bit
|
|
* 0x1 for channel 3 interrupt active
|
|
* 0x0 for channel 3 interrupt inactive
|
|
*/
|
|
uint64_t ch3_intstat : 1;
|
|
/**
|
|
* Bit 3 is channel 4 interrupt bit
|
|
* 0x1 for channel 4 interrupt active
|
|
* 0x0 for channel 4 interrupt inactive
|
|
*/
|
|
uint64_t ch4_intstat : 1;
|
|
/**
|
|
* Bit 4 is channel 5 interrupt bit
|
|
* 0x1 for channel 5 interrupt active
|
|
* 0x0 for channel 5 interrupt inactive
|
|
*/
|
|
uint64_t ch5_intstat : 1;
|
|
/**
|
|
* Bit 5 is channel 6 interrupt bit
|
|
* 0x1 for channel 6 interrupt active
|
|
* 0x0 for channel 6 interrupt inactive
|
|
*/
|
|
uint64_t ch6_intstat : 1;
|
|
/* Bits [15:6] is reserved */
|
|
uint64_t rsvd1 : 10;
|
|
/**
|
|
* Bit 16 is commom register status bit
|
|
* 0x1 for common register interrupt is active
|
|
* 0x0 for common register interrupt inactive
|
|
*/
|
|
uint64_t commonreg_intstat : 1;
|
|
/* Bits [63:17] is reserved */
|
|
uint64_t rsvd2 : 47;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_intstatus_u
|
|
{
|
|
struct dmac_intstatus_t intstatus;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_commonreg_intclear_t
|
|
{
|
|
/**
|
|
* Bit 0 is slave nterface Common Register
|
|
* Decode Error Interrupt clear Bit
|
|
* x01 for clear SLVIF_CommonReg_DEC_ERR interrupt
|
|
* in DMAC_COMMONREG_INTSTATUSREG
|
|
* 0x0 for inactive signal
|
|
*/
|
|
uint64_t cear_slvif_dec_err_intstat : 1;
|
|
/**
|
|
* Bit 1 is Slave Interface Common Register Write
|
|
* to Read only Error Interrupt clear Bit
|
|
* x01 for clear SLVIF_CommonReg_WR2RO_ERR interrupt
|
|
* in DMAC_COMMONREG_INTSTATUSREG
|
|
* 0x0 for inactive signal
|
|
*/
|
|
uint64_t clear_slvif_wr2ro_err_intstat : 1;
|
|
/**
|
|
* Bit 2 is Slave Interface Common Register Read to
|
|
* Write only Error Interrupt clear Bit
|
|
* x01 for clear SLVIF_CommonReg_RD2WO_ERR interrupt
|
|
* in DMAC_COMMONREG_INTSTATUSREG
|
|
* 0x0 for inactive signal
|
|
*/
|
|
uint64_t clear_slvif_rd2wo_err_intstat : 1;
|
|
/**
|
|
* Bit 3 is Slave Interface Common Register Write
|
|
* On Hold Error Interrupt clear Bit
|
|
* x01 for clear SSLVIF_CommonReg_WrOnHold_ERR interrupt
|
|
* in DMAC_COMMONREG_INTSTATUSREG
|
|
* 0x0 for inactive signal
|
|
*/
|
|
uint64_t clear_slvif_wronhold_err_intstat : 1;
|
|
/* Bits [7:4] is reserved */
|
|
uint64_t rsvd1 : 4;
|
|
/**
|
|
* Bit 8 is Slave Interface Undefined register
|
|
* Decode Error Interrupt clear Bit
|
|
* x01 for clear SLVIF_UndefinedReg_DEC_ERRinterrupt
|
|
* in DMAC_COMMONREG_INTSTATUSREG
|
|
* 0x0 for inactive signal
|
|
*/
|
|
uint64_t clear_slvif_undefinedreg_dec_err_intstat : 1;
|
|
/* Bits [63:9] is reserved */
|
|
uint64_t rsvd2 : 55;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_commonreg_intclear_u
|
|
{
|
|
struct dmac_commonreg_intclear_t com_intclear;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_commonreg_intstatus_enable_t
|
|
{
|
|
/**
|
|
* Bit 0 is Slave Interface Common Register Decode Error
|
|
* Interrupt Status Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_DEC_ERR_IntStat bit enable
|
|
* 0x0 for SLVIF_CommonReg_DEC_ERR_IntStat bit disable
|
|
*/
|
|
uint64_t enable_slvif_dec_err_intstat : 1;
|
|
/**
|
|
* Bit 1 is Slave Interface Common Register Write to Read
|
|
* only Error Interrupt Status Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_WR2RO_ERR_IntStat bit enable
|
|
* 0x0 for SLVIF_CommonReg_WR2RO_ERR_IntStat bit disable
|
|
*/
|
|
uint64_t enable_slvif_wr2ro_err_intstat : 1;
|
|
/*!<
|
|
* Bit 2 is Slave Interface Common Register Read to Write
|
|
* only Error Interrupt Status Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_RD2WO_ERR_IntStat bit enable
|
|
* 0x0 for SLVIF_CommonReg_RD2WO_ERR_IntStat bit disable
|
|
*/
|
|
uint64_t enable_slvif_rd2wo_err_intstat : 1;
|
|
/**
|
|
* Bit 3 is Slave Interface Common Register Write On Hold
|
|
* Error Interrupt Status Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_WrOnHold_ERR_IntStat bit enable
|
|
* 0x0 for SLVIF_CommonReg_WrOnHold_ERR_IntStat bit disable
|
|
*/
|
|
uint64_t enable_slvif_wronhold_err_intstat : 1;
|
|
/* Bits [7:4] is reserved */
|
|
uint64_t rsvd1 : 4;
|
|
/**
|
|
* Bit 8 is Slave Interface Undefined register Decode
|
|
* Error Interrupt Status enable Bit
|
|
* 0x1 for SLVIF_UndefinedReg_DEC_ERR_IntStat bit enable
|
|
* 0x0 for SLVIF_UndefinedReg_DEC_ERR_IntStat disable
|
|
*/
|
|
uint64_t enable_slvif_undefinedreg_dec_err_intstat : 1;
|
|
/* Bits [63:9] is reserved */
|
|
uint64_t rsvd2 : 55;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_commonreg_intstatus_enable_u
|
|
{
|
|
struct dmac_commonreg_intstatus_enable_t intstatus_enable;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_commonreg_intsignal_enable_t
|
|
{
|
|
/**
|
|
* Bit 0 is Slave Interface Common Register Decode Error
|
|
* Interrupt Signal Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_DEC_ERR_IntStat signal enable
|
|
* 0x0 for SLVIF_CommonReg_DEC_ERR_IntStat signal disable
|
|
*/
|
|
uint64_t enable_slvif_dec_err_intsignal : 1;
|
|
/**
|
|
* Bit 1 is Slave Interface Common Register Write to Read only
|
|
* Error Interrupt Signal Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_WR2RO_ERR_IntStat signal enable
|
|
* 0x0 for SLVIF_CommonReg_WR2RO_ERR_IntStat signal disable
|
|
*/
|
|
uint64_t enable_slvif_wr2ro_err_intsignal : 1;
|
|
/**
|
|
* Bit 2 is Slave Interface Common Register Read to
|
|
* Write only Error Interrupt Status Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_RD2WO_ERR_IntStat bit enable
|
|
* 0x0 for SLVIF_CommonReg_RD2WO_ERR_IntStat bit disable
|
|
*/
|
|
uint64_t enable_slvif_rd2wo_err_intsignal : 1;
|
|
/**
|
|
* Bit 3 is Slave Interface Common Register Write On Hold Error
|
|
* Interrupt Signal Enable Bit
|
|
* 0x1 for SLVIF_CommonReg_WrOnHold_ERR_IntStat signal enable
|
|
* 0x0 for SLVIF_CommonReg_WrOnHold_ERR_IntStat signal disable
|
|
*/
|
|
uint64_t enable_slvif_wronhold_err_intsignal : 1;
|
|
/* Bits [7:4] is reserved */
|
|
uint64_t rsvd1 : 4;
|
|
/**
|
|
* Bit 8 is Slave Interface Undefined register Decode Error
|
|
* Interrupt Signal Enable Bit
|
|
* 0x1 for SLVIF_UndefinedReg_DEC_ERR_IntStat signal enable
|
|
* 0x0 for SLVIF_UndefinedReg_DEC_ERR_IntStat signal disable
|
|
*/
|
|
uint64_t enable_slvif_undefinedreg_dec_err_intsignal : 1;
|
|
/* Bits [63:9] is reserved */
|
|
uint64_t rsvd2 : 55;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_commonreg_intsignal_enable_u
|
|
{
|
|
struct dmac_commonreg_intsignal_enable_t intsignal_enable;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_commonreg_intstatus_t
|
|
{
|
|
/**
|
|
* Bit 0 is Slave Interface Common Register Decode
|
|
* Error Interrupt Status Bit
|
|
* 0x1 for Slave Interface Decode Error detected
|
|
* 0x0 for No Slave Interface Decode Errors
|
|
*/
|
|
uint64_t slvif_dec_err_intstat : 1;
|
|
/**
|
|
* Bit 1 is Slave Interface Common Register Write to Read Only
|
|
* Error Interrupt Status bit
|
|
* 0x1 for Slave Interface Write to Read Only Error detected
|
|
* 0x0 No Slave Interface Write to Read Only Errors
|
|
*/
|
|
uint64_t slvif_wr2ro_err_intstat : 1;
|
|
/**
|
|
* Bit 2 is Slave Interface Common Register Read to Write
|
|
* only Error Interrupt Status bit
|
|
* 0x1 for Slave Interface Read to Write Only Error detected
|
|
* 0x0 for No Slave Interface Read to Write Only Errors
|
|
*/
|
|
uint64_t slvif_rd2wo_err_intstat : 1;
|
|
/**
|
|
* Bit 3 is Slave Interface Common Register Write On
|
|
* Hold Error Interrupt Status Bit
|
|
* 0x1 for Slave Interface Common Register Write On Hold Error detected
|
|
* 0x0 for No Slave Interface Common Register Write On Hold Errors
|
|
*/
|
|
uint64_t slvif_wronhold_err_intstat : 1;
|
|
/*!< Bits [7:4] is reserved */
|
|
uint64_t rsvd1 : 4;
|
|
/**
|
|
* Bit 8 is Slave Interface Undefined register Decode
|
|
* Error Interrupt Signal Enable Bit
|
|
* 0x1 for Slave Interface Decode Error detected
|
|
* 0x0 for No Slave Interface Decode Errors
|
|
*/
|
|
uint64_t slvif_undefinedreg_dec_err_intstat : 1;
|
|
/* Bits [63:9] is reserved */
|
|
uint64_t rsvd2 : 55;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_commonreg_intstatus_u
|
|
{
|
|
struct dmac_commonreg_intstatus_t commonreg_intstatus;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_reset_t
|
|
{
|
|
/* Bit 0 is DMAC reset request bit */
|
|
uint64_t rst : 1;
|
|
/* Bits [63:1] is reserved */
|
|
uint64_t rsvd : 63;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_reset_u
|
|
{
|
|
struct dmac_reset_t reset;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_block_ts_t
|
|
{
|
|
uint64_t block_ts : 22;
|
|
/*!< Bit [21:0] is block transfer size*/
|
|
uint64_t rsvd : 42;
|
|
/*!< Bits [63:22] is reserved */
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_block_ts_u
|
|
{
|
|
struct dmac_ch_block_ts_t block_ts;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_ctl_t
|
|
{
|
|
/**
|
|
* Bit 0 is source master select
|
|
* 1 for AXI master 2, 0 for AXI master 1
|
|
*/
|
|
uint64_t sms : 1;
|
|
/* Bit 1 is reserved */
|
|
uint64_t rsvd1 : 1;
|
|
/**
|
|
* Bit 2 is destination master select
|
|
* 0x1 for AXI master 2,0x0 for AXI master 1
|
|
*/
|
|
uint64_t dms : 1;
|
|
/* Bit 3 is reserved */
|
|
uint64_t rsvd2 : 1;
|
|
/**
|
|
* Bit 4 is source address increment
|
|
* 0x1 for no change, 0x0 for incremnet
|
|
*/
|
|
uint64_t sinc : 1;
|
|
/**
|
|
* Bit 5 is reserved
|
|
*/
|
|
uint64_t rsvd3 : 1;
|
|
/**
|
|
* Bit 6 is destination address incremnet
|
|
* 0x1 for no change, 0x0 for increment
|
|
*/
|
|
uint64_t dinc : 1;
|
|
/* Bit 7 is reserved*/
|
|
uint64_t rsvd4 : 1;
|
|
/**
|
|
* Bits [10:8] is source transfer width
|
|
* 0x0 for source transfer width is 8 bits
|
|
* 0x1 for source transfer width is 16 bits
|
|
* 0x2 for source transfer width is 32 bits
|
|
* 0x3 for source transfer width is 64 bits
|
|
* 0x4 for source transfer width is 128 bits
|
|
* 0x5 for source transfer width is 256 bits
|
|
* 0x6 for source transfer width is 512 bits
|
|
*/
|
|
uint64_t src_tr_width : 3;
|
|
/**
|
|
* Bits [13:11] is detination transfer width
|
|
* 0x0 for detination transfer width is 8 bits
|
|
* 0x1 for detination transfer width is 16 bits
|
|
* 0x2 for detination transfer width is 32 bits
|
|
* 0x3 for detination transfer width is 64 bits
|
|
* 0x4 for detination transfer width is 128 bits
|
|
* 0x5 for detination transfer width is 256 bits
|
|
* 0x6 for detination transfer width is 512 bits
|
|
*/
|
|
uint64_t dst_tr_width : 3;
|
|
/**
|
|
* Bits [17:14] is source burst transaction length
|
|
* 0x0 for 1 data item read from rource in the burst transaction
|
|
* 0x1 for 4 data item read from rource in the burst transaction
|
|
* 0x2 for 8 data item read from rource in the burst transaction
|
|
* 0x3 for 16 data item read from rource in the burst transaction
|
|
* 0x4 for 32 data item read from rource in the burst transaction
|
|
* 0x5 for 64 data item read from rource in the burst transaction
|
|
* 0x6 for 128 data item read from rource in the burst transaction
|
|
* 0x7 for 256 data item read from rource in the burst transaction
|
|
* 0x8 for 512 data item read from rource in the burst transaction
|
|
* 0x9 for 1024 data item read from rource in the burst transaction
|
|
*/
|
|
uint64_t src_msize : 4;
|
|
/**
|
|
* Bits [17:14] is sdestination burst transaction length
|
|
* 0x0 for 1 data item read from rource in the burst transaction
|
|
* 0x1 for 4 data item read from rource in the burst transaction
|
|
* 0x2 for 8 data item read from rource in the burst transaction
|
|
* 0x3 for 16 data item read from rource in the burst transaction
|
|
* 0x4 for 32 data item read from rource in the burst transaction
|
|
* 0x5 for 64 data item read from rource in the burst transaction
|
|
* 0x6 for 128 data item read from rource in the burst transaction
|
|
* 0x7 for 256 data item read from rource in the burst transaction
|
|
* 0x8 for 512 data item read from rource in the burst transaction
|
|
* 0x9 for 1024 data item read from rource in the burst transaction
|
|
*/
|
|
uint64_t dst_msize : 4;
|
|
/**
|
|
* Bits [25:22] is reserved
|
|
*/
|
|
uint64_t rsvd5 : 4;
|
|
/*!< Bits [29:26] is reserved */
|
|
uint64_t rsvd6 : 4;
|
|
/**
|
|
* Bit 30 is Non Posted Last Write Enable
|
|
* 0x1 for posted writes may be used till the end of the block
|
|
* 0x 0 for posted writes may be used throughout the block transfer
|
|
*/
|
|
uint64_t nonposted_lastwrite_en : 1;
|
|
/* Bit 31 is resrved */
|
|
uint64_t rsvd7 : 1;
|
|
/* Bits [34:32] is reserved*/
|
|
uint64_t rsvd8 : 3;
|
|
/* Bits [37:35] is reserved*/
|
|
uint64_t rsvd9 : 3;
|
|
/**
|
|
* Bit 38 is source burst length enable
|
|
* 1 for enable, 0 for disable
|
|
*/
|
|
uint64_t arlen_en : 1;
|
|
/* Bits [46:39] is source burst length*/
|
|
uint64_t arlen : 8;
|
|
/**
|
|
* Bit 47 is destination burst length enable
|
|
* 1 for enable, 0 for disable
|
|
*/
|
|
uint64_t awlen_en : 1;
|
|
/* Bits [55:48] is destination burst length */
|
|
uint64_t awlen : 8;
|
|
/**
|
|
* Bit 56 is source status enable
|
|
* 0x1 for enable, 0x0 for disable
|
|
*/
|
|
uint64_t src_stat_en : 1;
|
|
/**
|
|
* Bit 57 is destination status enable
|
|
* 0x1 for enable, 0x0 for disable
|
|
*/
|
|
uint64_t dst_stat_en : 1;
|
|
/**
|
|
* Bit 58 is interrupt completion of block transfer
|
|
* 0x1 for enable CHx_IntStatusReg.BLOCK_TFR_DONE_IntStat field
|
|
* 0x0 for dsiable CHx_IntStatusReg.BLOCK_TFR_DONE_IntStat field
|
|
*/
|
|
uint64_t ioc_blktfr : 1;
|
|
/**
|
|
* Bits [61:59] is reserved
|
|
*/
|
|
uint64_t rsvd10 : 3;
|
|
/**
|
|
* Bit 62 is last shadow linked list item
|
|
* 0x1 for indicate shadowreg/LLI content is the last one
|
|
* 0x0 for indicate shadowreg/LLI content not the last one
|
|
*/
|
|
uint64_t shadowreg_or_lli_last : 1;
|
|
/**
|
|
* Bit 63 is last shadow linked list item valid
|
|
* 0x1 for indicate shadowreg/LLI content is valid
|
|
* 0x0 for indicate shadowreg/LLI content is invalid
|
|
*/
|
|
uint64_t shadowreg_or_lli_valid : 1;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_ctl_u
|
|
{
|
|
struct dmac_ch_ctl_t ch_ctl;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_cfg_t
|
|
{
|
|
/**
|
|
* Bit[1:0] is source multi block transfer type
|
|
* 0x0 for continuous multiblock type
|
|
* 0x1 for reload multiblock type
|
|
* 0x2 for shadow register based multiblock type
|
|
* 0x3 for linked lisr bases multiblock type
|
|
*/
|
|
uint64_t src_multblk_type : 2;
|
|
/**
|
|
* Bit[3:2] is source multi block transfer type
|
|
* 0x0 for continuous multiblock type
|
|
* 0x1 for reload multiblock type
|
|
* 0x2 for shadow register based multiblock type
|
|
* 0x3 for linked lisr bases multiblock type
|
|
*/
|
|
uint64_t dst_multblk_type : 2;
|
|
/* Bits [31:4] is reserved*/
|
|
uint64_t rsvd1 : 28;
|
|
/**
|
|
* Bits [34:32] is transfer type and flow control
|
|
* 0x0 transfer memory to memory and flow controler is dmac
|
|
* 0x1 transfer memory to peripheral and flow controler is dmac
|
|
* 0x2 transfer peripheral to memory and flow controler is dmac
|
|
* 0x3 transfer peripheral to peripheral and flow controler is dmac
|
|
* 0x4 transfer peripheral to memory and flow controler is
|
|
* source peripheral
|
|
* 0x5 transfer peripheral to peripheral and flow controler
|
|
* is source peripheral
|
|
* 0x6 transfer memory to peripheral and flow controler is
|
|
* destination peripheral
|
|
* 0x7 transfer peripheral to peripheral and flow controler
|
|
* is destination peripheral
|
|
*/
|
|
uint64_t tt_fc : 3;
|
|
/**
|
|
* Bit 35 is source software or hardware handshaking select
|
|
* 0x1 for software handshaking is used
|
|
* 0x0 for hardware handshaking is used
|
|
*/
|
|
uint64_t hs_sel_src : 1;
|
|
/**
|
|
* Bit 36 is destination software or hardware handshaking select
|
|
*0x1 for software handshaking is used
|
|
*0x0 for hardware handshaking is used
|
|
*/
|
|
uint64_t hs_sel_dst : 1;
|
|
/**
|
|
* Bit 37 is sorce hardware handshaking interface polarity
|
|
* 0x1 active low, 0x0 active high
|
|
*/
|
|
uint64_t src_hwhs_pol : 1;
|
|
/**
|
|
* Bit 38 is destination hardware handshaking interface polarity
|
|
* 0x1 active low, 0x0 active high
|
|
*/
|
|
uint64_t dst_hwhs_pol : 1;
|
|
/**
|
|
* Bits [41:39] is assign a hardware handshaking interface
|
|
* to source of channel x
|
|
*/
|
|
uint64_t src_per : 4;
|
|
/* Bit 43 is reserved*/
|
|
uint64_t rsvd3 : 1;
|
|
/**
|
|
* Bits [46:44] is assign a hardware handshaking interface
|
|
* to destination of channel x
|
|
*/
|
|
uint64_t dst_per : 4;
|
|
/* Bit 48 is reserved*/
|
|
uint64_t rsvd5 : 1;
|
|
/* Bits [51:49] is channel priority,7 is highest, 0 is lowest*/
|
|
uint64_t ch_prior : 3;
|
|
/**
|
|
* Bit 52 is channel lock bit
|
|
* 0x0 for channel is not locked, 0x1 for channel is locked
|
|
*/
|
|
uint64_t lock_ch : 1;
|
|
/**
|
|
* Bits [54:53] is chnannel lock level
|
|
* 0x0 for duration of channel is locked for entire DMA transfer
|
|
* 0x1 for duration of channel is locked for current block transfer
|
|
*/
|
|
uint64_t lock_ch_l : 2;
|
|
uint64_t src_osr_lmt : 4;
|
|
/* Bits [58:55] is source outstanding request limit */
|
|
uint64_t dst_osr_lmt : 4;
|
|
/* Bits [62:59] is destination outstanding request limit */
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_cfg_u
|
|
{
|
|
struct dmac_ch_cfg_t ch_cfg;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_llp_t
|
|
{
|
|
/**
|
|
* Bit 0 is LLI master select
|
|
* 0x0 for next linked list item resides on AXI madster1 interface
|
|
* 0x1 for next linked list item resides on AXI madster2 interface
|
|
*/
|
|
uint64_t lms : 1;
|
|
/* Bits [5:1] is reserved */
|
|
uint64_t rsvd1 : 5;
|
|
/* Bits [63:6] is starting address memeory of LLI block */
|
|
uint64_t loc : 58;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_llp_u
|
|
{
|
|
struct dmac_ch_llp_t llp;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_status_t
|
|
{
|
|
/* Bits [21:0] is completed block transfer size */
|
|
uint64_t cmpltd_blk_size : 22;
|
|
/* Bits [46:32] is reserved */
|
|
uint64_t rsvd1 : 15;
|
|
/* Bits [63:47] is reserved */
|
|
uint64_t rsvd2 : 17;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_status_u
|
|
{
|
|
struct dmac_ch_status_t status;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_swhssrc_t
|
|
{
|
|
/**
|
|
* Bit 0 is software handshake request for channel source
|
|
* 0x1 source periphraral request for a dma transfer
|
|
* 0x0 source peripheral is not request for a burst transfer
|
|
*/
|
|
uint64_t swhs_req_src : 1;
|
|
/**
|
|
* Bit 1 is write enable bit for software handshake request
|
|
*0x1 for enable, 0x0 for disable
|
|
*/
|
|
uint64_t swhs_req_src_we : 1;
|
|
/**
|
|
* Bit 2 is software handshake single request for channel source
|
|
* 0x1 for source peripheral requesr for a single dma transfer
|
|
* 0x0 for source peripheral is not requesting for a single transfer
|
|
*/
|
|
uint64_t swhs_sglreq_src : 1;
|
|
/**
|
|
* Bit 3 is write enable bit for software handshake
|
|
* single request for channle source
|
|
* 0x1 for enable write, 0x0 for disable write
|
|
*/
|
|
uint64_t swhs_sglreq_src_we : 1;
|
|
/**
|
|
* Bit 4 software handshake last request for channel source
|
|
* 0x1 for current transfer is last transfer
|
|
* 0x0 for current transfer is not the last transfer
|
|
*/
|
|
uint64_t swhs_lst_src : 1;
|
|
/**
|
|
* Bit 5 is write enable bit for software
|
|
* handshake last request
|
|
* 0x1 for enable, 0x0 for disable
|
|
*/
|
|
uint64_t swhs_lst_src_we : 1;
|
|
/* Bits [63:6] is reserved */
|
|
uint64_t rsvd : 58;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_swhssrc_u
|
|
{
|
|
struct dmac_ch_swhssrc_t swhssrc;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_swhsdst_t
|
|
{
|
|
/**
|
|
* Bit 0 is software handshake request for channel destination
|
|
* 0x1 destination periphraral request for a dma transfer
|
|
* 0x0 destination peripheral is not request for a burst transfer
|
|
*/
|
|
uint64_t swhs_req_dst : 1;
|
|
/**
|
|
* Bit 1 is write enable bit for software handshake request
|
|
* 0x1 for enable, 0x0 for disable
|
|
*/
|
|
uint64_t swhs_req_dst_we : 1;
|
|
/**
|
|
* Bit 2 is software handshake single request for channel destination
|
|
* 0x1 for destination peripheral requesr for a single dma transfer
|
|
* 0x0 for destination peripheral is not requesting
|
|
* for a single transfer
|
|
*/
|
|
uint64_t swhs_sglreq_dst : 1;
|
|
/**
|
|
* Bit 3 is write enable bit for software handshake
|
|
* single request for channle destination
|
|
* 0x1 for enable write, 0x0 for disable write
|
|
*/
|
|
uint64_t swhs_sglreq_dst_we : 1;
|
|
/**
|
|
* Bit 4 software handshake last request for channel dstination
|
|
* 0x1 for current transfer is last transfer
|
|
* 0x0 for current transfer is not the last transfer
|
|
*/
|
|
uint64_t swhs_lst_dst : 1;
|
|
/**
|
|
* Bit 5 is write enable bit for software handshake last request
|
|
* 0x1 for enable, 0x0 for disable
|
|
*/
|
|
uint64_t swhs_lst_dst_we : 1;
|
|
/* Bits [63:6] is reserved */
|
|
uint64_t rsvd : 58;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_swhsdst_u
|
|
{
|
|
struct dmac_ch_swhsdst_t swhsdst;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_blk_tfr_resumereq_t
|
|
{
|
|
/**
|
|
* Bit 0 is block transfer resume request bit
|
|
* 0x1 for request for resuming
|
|
* 0x0 for no request to resume
|
|
*/
|
|
uint64_t blk_tfr_resumereq : 1;
|
|
/* Bits [63:1] is reserved */
|
|
uint64_t rsvd : 63;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_blk_tfr_resumereq_u
|
|
{
|
|
struct dmac_ch_blk_tfr_resumereq_t blk_tfr_resumereq;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_intstatus_enable_t
|
|
{
|
|
/* Bit 0 is block transfer done interrupt status enable */
|
|
uint64_t enable_block_tfr_done_intstatus : 1;
|
|
/* DMA transfer done interrupt status enable */
|
|
uint64_t enable_dma_tfr_done_intstat : 1;
|
|
/* Bit 2 reserved */
|
|
uint64_t rsvd1 : 1;
|
|
/* Bit 3 source transaction complete status enable */
|
|
uint64_t enable_src_transcomp_intstat : 1;
|
|
/* Bit 4 destination transaction complete */
|
|
uint64_t enable_dst_transcomp_intstat : 1;
|
|
/* Bit 5 Source Decode Error Status Enable */
|
|
uint64_t enable_src_dec_err_intstat : 1;
|
|
/* Bit 6 Destination Decode Error Status Enable */
|
|
uint64_t enable_dst_dec_err_intstat : 1;
|
|
/* Bit 7 Source Slave Error Status Enable */
|
|
uint64_t enable_src_slv_err_intstat : 1;
|
|
/* Bit 8 Destination Slave Error Status Enable */
|
|
uint64_t enable_dst_slv_err_intstat : 1;
|
|
/* Bit 9 LLI Read Decode Error Status Enable */
|
|
uint64_t enable_lli_rd_dec_err_intstat : 1;
|
|
/* Bit 10 LLI WRITE Decode Error Status Enable */
|
|
uint64_t enable_lli_wr_dec_err_intstat : 1;
|
|
/* Bit 11 LLI Read Slave Error Status Enable */
|
|
uint64_t enable_lli_rd_slv_err_intstat : 1;
|
|
/* Bit 12 LLI WRITE Slave Error Status Enable */
|
|
uint64_t enable_lli_wr_slv_err_intstat : 1;
|
|
uint64_t rsvd2 : 51;
|
|
};
|
|
|
|
union dmac_ch_intstatus_enable_u
|
|
{
|
|
struct dmac_ch_intstatus_enable_t ch_intstatus_enable;
|
|
uint64_t data;
|
|
};
|
|
|
|
struct dmac_ch_intclear_t
|
|
{
|
|
/* Bit 0 block transfer done interrupt clear bit.*/
|
|
uint64_t blk_tfr_done_intstat : 1;
|
|
/* Bit 1 DMA transfer done interrupt clear bit */
|
|
uint64_t dma_tfr_done_intstat : 1;
|
|
/* Bit 2 is reserved */
|
|
uint64_t resv1 : 1;
|
|
uint64_t resv2 : 61;
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
union dmac_ch_intclear_u
|
|
{
|
|
uint64_t data;
|
|
struct dmac_ch_intclear_t intclear;
|
|
};
|
|
|
|
struct dmac_channel_t
|
|
{
|
|
/* (0x100) SAR Address Register */
|
|
uint64_t sar;
|
|
/* (0x108) DAR Address Register */
|
|
uint64_t dar;
|
|
/* (0x110) Block Transfer Size Register */
|
|
uint64_t block_ts;
|
|
/* (0x118) Control Register */
|
|
uint64_t ctl;
|
|
/* (0x120) Configure Register */
|
|
uint64_t cfg;
|
|
/* (0x128) Linked List Pointer register */
|
|
uint64_t llp;
|
|
/* (0x130) Channelx Status Register */
|
|
uint64_t status;
|
|
/* (0x138) Channelx Software handshake Source Register */
|
|
uint64_t swhssrc;
|
|
/* (0x140) Channelx Software handshake Destination Register */
|
|
uint64_t swhsdst;
|
|
/* (0x148) Channelx Block Transfer Resume Request Register */
|
|
uint64_t blk_tfr;
|
|
/* (0x150) Channelx AXI ID Register */
|
|
uint64_t axi_id;
|
|
/* (0x158) Channelx AXI QOS Register */
|
|
uint64_t axi_qos;
|
|
/* Reserved address */
|
|
uint64_t reserved1[4];
|
|
/* (0x180) Interrupt Status Enable Register */
|
|
uint64_t intstatus_en;
|
|
/* (0x188) Channelx Interrupt Status Register */
|
|
uint64_t intstatus;
|
|
/* (0x190) Interrupt Siganl Enable Register */
|
|
uint64_t intsignal_en;
|
|
/* (0x198) Interrupt Clear Register */
|
|
uint64_t intclear;
|
|
uint64_t reserved2[12];
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
struct dmac_t
|
|
{
|
|
/* (0x00) DMAC ID Rgister */
|
|
uint64_t id;
|
|
/* (0x08) DMAC COMPVER Register */
|
|
uint64_t compver;
|
|
/* (0x10) DMAC Configure Register */
|
|
uint64_t cfg;
|
|
/* (0x18) Channel Enable Register */
|
|
uint64_t chen;
|
|
uint64_t reserved1[2];
|
|
/* (0x30) DMAC Interrupt Status Register */
|
|
uint64_t intstatus;
|
|
/* (0x38) DMAC Common register Interrupt Status Register */
|
|
uint64_t com_intclear;
|
|
/* (0x40) DMAC Common Interrupt Enable Register */
|
|
uint64_t com_intstatus_en;
|
|
/* (0x48) DMAC Common Interrupt Signal Enable Register */
|
|
uint64_t com_intsignal_en;
|
|
/* (0x50) DMAC Common Interrupt Status */
|
|
uint64_t com_intstatus;
|
|
/* (0x58) DMAC Reset register */
|
|
uint64_t reset;
|
|
uint64_t reserved2[20];
|
|
struct dmac_channel_t channel[DMAC_CHANNEL_COUNT];
|
|
} __attribute__((packed, aligned(8)));
|
|
|
|
struct dmac_channel_config_t
|
|
{
|
|
uint64_t sar;
|
|
uint64_t dar;
|
|
uint8_t ctl_sms;
|
|
uint8_t ctl_dms;
|
|
uint8_t ctl_src_msize;
|
|
uint8_t ctl_drc_msize;
|
|
uint8_t ctl_sinc;
|
|
uint8_t ctl_dinc;
|
|
uint8_t ctl_src_tr_width;
|
|
uint8_t ctl_dst_tr_width;
|
|
uint8_t ctl_ioc_blktfr;
|
|
uint8_t ctl_src_stat_en;
|
|
uint8_t ctl_dst_stat_en;
|
|
uint8_t cfg_dst_per;
|
|
uint8_t cfg_src_per;
|
|
uint8_t cfg_src_hs_pol;
|
|
uint8_t cfg_dst_hs_pol;
|
|
uint8_t cfg_hs_sel_src;
|
|
uint8_t cfg_hs_sel_dst;
|
|
uint64_t cfg_src_multblk_type;
|
|
uint64_t cfg_dst_multblk_type;
|
|
uint64_t llp_loc;
|
|
uint8_t llp_lms;
|
|
uint64_t ctl_block_ts;
|
|
uint8_t ctl_tt_fc;
|
|
uint8_t cfg_protctl;
|
|
uint8_t cfg_fifo_mode;
|
|
uint8_t cfg_fcmode;
|
|
uint8_t cfg_lock_ch_l;
|
|
uint8_t cfg_ch_prior;
|
|
};
|
|
|
|
#define LIST_ENTRY(ptr, type, member) \
|
|
((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
|
|
|
|
struct list_head_t
|
|
{
|
|
struct list_head_t *next, *prev;
|
|
};
|
|
|
|
/**
|
|
* @brief Dmac.data/dw_dmac_lli_item
|
|
*
|
|
* @desc This structure is used when creating Linked List Items.
|
|
*
|
|
* @see dw_dmac_addLliItem()
|
|
*/
|
|
struct dmac_lli_item_t
|
|
{
|
|
uint64_t sar;
|
|
uint64_t dar;
|
|
uint64_t ch_block_ts;
|
|
uint64_t llp;
|
|
uint64_t ctl;
|
|
uint64_t sstat;
|
|
uint64_t dstat;
|
|
uint64_t resv;
|
|
} __attribute__((packed, aligned(64)));
|
|
|
|
extern volatile struct dmac_t *const dmac;
|
|
|
|
/**
|
|
* @brief Dmac initialize
|
|
*/
|
|
void dmac_init(void);
|
|
|
|
/**
|
|
* @brief Read dmac id
|
|
*
|
|
* @return Dmac id
|
|
*/
|
|
uint64_t dmac_read_id(void);
|
|
|
|
/**
|
|
* @brief Read dmac component version
|
|
*
|
|
* @return Dmac version
|
|
*/
|
|
uint64_t dmac_read_version(void);
|
|
|
|
/**
|
|
* @brief Read AXI channel id
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*
|
|
* @return channel AXI ID data
|
|
*/
|
|
uint64_t dmac_read_channel_id(dmac_channel_number ch);
|
|
|
|
/**
|
|
* @brief Set channle configure
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] cfg_param The configuration parameter
|
|
*
|
|
* @return result
|
|
* - 0 Success
|
|
* - Other Fail
|
|
*/
|
|
int dmac_set_channel_config(dmac_channel_number channel_num,
|
|
struct dmac_channel_config_t *cfg_param);
|
|
|
|
/**
|
|
* @brief Get channel configure param
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[out] cfg_param The configuration parameter
|
|
*
|
|
* @return result
|
|
* - 0 Success
|
|
* - Other Fail
|
|
*/
|
|
int dmac_get_channel_config(dmac_channel_number channel_num,
|
|
struct dmac_channel_config_t *cfg_param);
|
|
|
|
/**
|
|
* @brief Enable dmac source transaction complete interrupt
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void src_transaction_complete_int_enable(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Enable dmac channel
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void dmac_channel_enable(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Enable dmac
|
|
*/
|
|
void dmac_enable(void);
|
|
|
|
/**
|
|
* @brief Enable dmac channel interrupt status
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void dmac_enable_channel_interrupt_status(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Disable dmac channel interrupt status
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void dmac_disable_channel_interrupt_status(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Check whether channel is busy
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*
|
|
* @return result
|
|
* - 0 Not busy
|
|
* - 1 Busy
|
|
*/
|
|
int32_t dmac_check_channel_busy(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Clear interrupt status
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void dmac_chanel_interrupt_clear(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Create link list item
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] LLI_row_num The lli row number
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* @param[in] LLI_last_row The lli last row
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* @param[out] lli_item The lli item
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* @param[in] cfg_param The configuration parameter
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*/
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void dmac_link_list_item(dmac_channel_number channel_num, uint8_t lli_row_num,
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int8_t lli_last_row, struct dmac_lli_item_t *lli_item,
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struct dmac_channel_config_t *cfg_param);
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|
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/**
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* @brief linked list mode list addr entry,
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* descriptor table must be 64 byte aligned
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*
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* @param[in] channel_num The channel number
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* @param[in] addr The address
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*/
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void dmac_set_linked_list_addr_point(dmac_channel_number channel_num,
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uint64_t *addr);
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|
|
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/**
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* @brief Set flow control
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*
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* @param[in] channel_num The channel number
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* @param[in] flow_control The flow control
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*/
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void dmac_set_flow_control(dmac_channel_number channel_num,
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enum dmac_transfer_flow flow_control);
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|
|
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/**
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* @brief Set multitransfer type and handshake
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*
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* @param[in] channel_num The channel number
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* @param[in] transfer_type The transfer type
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* @param[in] handshak_select The handshake select
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|
*/
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void dmac_set_destination_transfer_control(dmac_channel_number channel_num,
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enum dmac_multiblk_transfer_type transfer_type,
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enum dmac_sw_hw_hs_select handshak_select);
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|
|
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/**
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* @brief Set multitransfer type and handshak
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|
*
|
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* @param[in] channel_num The channel number
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* @param[in] transfer_type The transfer type
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* @param[in] handshak_select The handshake select
|
|
*/
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void dmac_set_source_transfer_control(dmac_channel_number channel_num,
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enum dmac_multiblk_transfer_type transfer_type,
|
|
enum dmac_sw_hw_hs_select handshak_select);
|
|
|
|
/**
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|
* @brief Set destination's master,address mode, transfer width and transfer length
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] master_select The master select
|
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* @param[in] address_mode The address mode
|
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* @param[in] tr_width The tr width
|
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* @param[in] burst_length The burst length
|
|
*/
|
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void dmac_master_control(dmac_channel_number channel_num,
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enum dmac_master_number master_select,
|
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enum dmac_address_increment address_mode,
|
|
enum dmac_transfer_width tr_width,
|
|
enum dmac_burst_trans_length burst_length);
|
|
|
|
/**
|
|
* @brief Set source's master,address mode, transfer width and transfer length
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] master_select The master select
|
|
* @param[in] address_mode The address mode
|
|
* @param[in] tr_width The transfer width
|
|
* @param[in] burst_length The burst transfer length
|
|
*/
|
|
void dmac_source_control(dmac_channel_number channel_num,
|
|
enum dmac_master_number master_select,
|
|
enum dmac_address_increment address_mode,
|
|
enum dmac_transfer_width tr_width,
|
|
enum dmac_burst_trans_length burst_length);
|
|
|
|
/**
|
|
* @brief Set block transfer size
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] block_size The block size
|
|
*/
|
|
void dmac_set_block_ts(dmac_channel_number channel_num, uint32_t block_size);
|
|
|
|
/**
|
|
* @brief Set dmac address
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param src_addr The source address
|
|
* @param dst_src The destination source
|
|
*/
|
|
void dmac_set_address(dmac_channel_number channel_num, uint64_t src_addr,
|
|
uint64_t dst_addr);
|
|
|
|
/**
|
|
* @brief Disable channel
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void dmac_channel_disable(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Update dmac shadow register
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] last_block The last block
|
|
* @param[in] cfg_param The configuration parameter
|
|
*/
|
|
void dmac_update_shandow_register(dmac_channel_number channel_num, int8_t last_block,
|
|
struct dmac_channel_config_t *cfg_param);
|
|
|
|
/**
|
|
* @brief Set shadow register invalid flag, used for first block transfer, after configure
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
*/
|
|
void dmac_set_shadow_invalid_flag(dmac_channel_number channel_num);
|
|
|
|
/**
|
|
* @brief Set dmac channel parameters
|
|
*
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] src The source address
|
|
* @param[in] dest The destination address
|
|
* @param[in] src_inc Whether the source address auto increment
|
|
* @param[in] dest_inc Whether the destination address auto increment
|
|
* @param[in] dmac_msize The dmac burst transfer length
|
|
* @param[in] dmac_trans_width The dmac transfer width
|
|
* @param[in] blockSize The block size
|
|
*
|
|
* @return result
|
|
* - 0 Success
|
|
* - Other Fail
|
|
*/
|
|
int dmac_set_channel_param(dmac_channel_number channel_num,
|
|
void *src, void *dest, enum dmac_address_increment src_inc, enum dmac_address_increment dest_inc,
|
|
enum dmac_burst_trans_length dmac_msize,
|
|
enum dmac_transfer_width dmac_trans_width,
|
|
uint32_t blockSize);
|
|
|
|
/**
|
|
* @brief Set dmac param
|
|
*
|
|
* @param[in] channel_num Dmac channel
|
|
* @param[in] src Dmac source
|
|
* @param[in] dest Dmac dest
|
|
* @param[in] src_inc Source address increase or not
|
|
* @param[in] dest_inc Dest address increase or not
|
|
* @param[in] dmac_msize Dmac burst length
|
|
* @param[in] dmac_trans_width Dmac transfer data width
|
|
* @param[in] blockSize Dmac transfer length
|
|
*
|
|
*/
|
|
void dmac_set_single_mode(dmac_channel_number channel_num,
|
|
void *src, void *dest, enum dmac_address_increment src_inc, enum dmac_address_increment dest_inc,
|
|
enum dmac_burst_trans_length dmac_msize,
|
|
enum dmac_transfer_width dmac_trans_width,
|
|
uint32_t blockSize);
|
|
|
|
/**
|
|
* @brief Wait for dmac work done
|
|
*
|
|
* @param[in] channel_num Dmac channel
|
|
*
|
|
*/
|
|
void dmac_wait_done(dmac_channel_number channel_num);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _DRIVER_DMAC_H */
|