268 lines
7.1 KiB
C
268 lines
7.1 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_GPIOHS_H
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#define _DRIVER_GPIOHS_H
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#include <stdint.h>
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#include "platform.h"
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#include <stddef.h>
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#include "gpio_common.h"
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#include "plic.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/* Register address offsets */
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#define GPIOHS_INPUT_VAL (0x00)
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#define GPIOHS_INPUT_EN (0x04)
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#define GPIOHS_OUTPUT_EN (0x08)
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#define GPIOHS_OUTPUT_VAL (0x0C)
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#define GPIOHS_PULLUP_EN (0x10)
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#define GPIOHS_DRIVE (0x14)
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#define GPIOHS_RISE_IE (0x18)
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#define GPIOHS_RISE_IP (0x1C)
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#define GPIOHS_FALL_IE (0x20)
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#define GPIOHS_FALL_IP (0x24)
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#define GPIOHS_HIGH_IE (0x28)
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#define GPIOHS_HIGH_IP (0x2C)
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#define GPIOHS_LOW_IE (0x30)
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#define GPIOHS_LOW_IP (0x34)
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#define GPIOHS_IOF_EN (0x38)
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#define GPIOHS_IOF_SEL (0x3C)
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#define GPIOHS_OUTPUT_XOR (0x40)
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/* clang-format on */
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/**
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* @brief GPIO bits raw object
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*/
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struct gpiohs_raw_t
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{
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/* Address offset 0x00 */
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uint32_t input_val;
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/* Address offset 0x04 */
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uint32_t input_en;
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/* Address offset 0x08 */
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uint32_t output_en;
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/* Address offset 0x0c */
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uint32_t output_val;
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/* Address offset 0x10 */
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uint32_t pullup_en;
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/* Address offset 0x14 */
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uint32_t drive;
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/* Address offset 0x18 */
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uint32_t rise_ie;
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/* Address offset 0x1c */
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uint32_t rise_ip;
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/* Address offset 0x20 */
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uint32_t fall_ie;
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/* Address offset 0x24 */
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uint32_t fall_ip;
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/* Address offset 0x28 */
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uint32_t high_ie;
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/* Address offset 0x2c */
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uint32_t high_ip;
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/* Address offset 0x30 */
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uint32_t low_ie;
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/* Address offset 0x34 */
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uint32_t low_ip;
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/* Address offset 0x38 */
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uint32_t iof_en;
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/* Address offset 0x3c */
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uint32_t iof_sel;
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/* Address offset 0x40 */
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uint32_t output_xor;
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} __attribute__((packed, aligned(4)));
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/**
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* @brief GPIO bits object
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*/
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typedef struct
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{
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uint32_t b0 : 1;
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uint32_t b1 : 1;
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uint32_t b2 : 1;
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uint32_t b3 : 1;
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uint32_t b4 : 1;
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uint32_t b5 : 1;
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uint32_t b6 : 1;
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uint32_t b7 : 1;
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uint32_t b8 : 1;
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uint32_t b9 : 1;
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uint32_t b10 : 1;
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uint32_t b11 : 1;
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uint32_t b12 : 1;
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uint32_t b13 : 1;
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uint32_t b14 : 1;
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uint32_t b15 : 1;
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uint32_t b16 : 1;
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uint32_t b17 : 1;
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uint32_t b18 : 1;
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uint32_t b19 : 1;
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uint32_t b20 : 1;
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uint32_t b21 : 1;
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uint32_t b22 : 1;
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uint32_t b23 : 1;
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uint32_t b24 : 1;
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uint32_t b25 : 1;
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uint32_t b26 : 1;
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uint32_t b27 : 1;
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uint32_t b28 : 1;
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uint32_t b29 : 1;
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uint32_t b30 : 1;
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uint32_t b31 : 1;
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} __attribute__((packed, aligned(4))) gpiohs_bits_t;
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/**
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* @brief GPIO bits multi access union
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*/
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typedef union
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{
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/* 32x1 bit mode */
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uint32_t u32[1];
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/* 16x2 bit mode */
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uint16_t u16[2];
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/* 8x4 bit mode */
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uint8_t u8[4];
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/* 1 bit mode */
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gpiohs_bits_t bits;
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} __attribute__((packed, aligned(4))) gpiohs_u32_t;
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/**
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* @brief GPIO object
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*
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* The GPIO controller is a peripheral device mapped in the
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* internal memory map, discoverable in the Configuration String.
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* It is responsible for low-level configuration of the actual
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* GPIO pads on the device (direction, pull up-enable, and drive
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* value), as well as selecting between various sources of the
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* controls for these signals. The GPIO controller allows seperate
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* configuration of each of N GPIO bits.
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*
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* Once the interrupt is pending, it will remain set until a 1 is
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* written to the *_ip register at that bit.
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*/
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typedef struct
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{
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/* Address offset 0x00, Input Values */
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gpiohs_u32_t input_val;
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/* Address offset 0x04, Input enable */
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gpiohs_u32_t input_en;
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/* Address offset 0x08, Output enable */
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gpiohs_u32_t output_en;
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/* Address offset 0x0c, Onput Values */
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gpiohs_u32_t output_val;
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/* Address offset 0x10, Internal Pull-Ups enable */
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gpiohs_u32_t pullup_en;
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/* Address offset 0x14, Drive Strength */
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gpiohs_u32_t drive;
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/* Address offset 0x18, Rise interrupt enable */
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gpiohs_u32_t rise_ie;
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/* Address offset 0x1c, Rise interrupt pending */
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gpiohs_u32_t rise_ip;
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/* Address offset 0x20, Fall interrupt enable */
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gpiohs_u32_t fall_ie;
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/* Address offset 0x24, Fall interrupt pending */
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gpiohs_u32_t fall_ip;
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/* Address offset 0x28, High interrupt enable */
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gpiohs_u32_t high_ie;
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/* Address offset 0x2c, High interrupt pending */
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gpiohs_u32_t high_ip;
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/* Address offset 0x30, Low interrupt enable */
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gpiohs_u32_t low_ie;
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/* Address offset 0x34, Low interrupt pending */
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gpiohs_u32_t low_ip;
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/* Address offset 0x38, HW I/O Function enable */
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gpiohs_u32_t iof_en;
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/* Address offset 0x3c, HW I/O Function select */
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gpiohs_u32_t iof_sel;
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/* Address offset 0x40, Output XOR (invert) */
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gpiohs_u32_t output_xor;
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} __attribute__((packed, aligned(4))) gpiohs_t;
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/**
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* @brief GPIO High-speed object instanse
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*/
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extern volatile gpiohs_t *const gpiohs;
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/**
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* @brief Gpiohs initialize
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int gpiohs_init(void);
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/**
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* @brief Gpiohs pin initialize, map Pin number to Gpio function pin
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*
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* @param[in] pin_num Pin number
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* @param[in] gpio_pin Gpiohs pin
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*/
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void gpiohs_pin_init(size_t pin_num, size_t gpio_pin);
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/**
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* @brief Set Gpiohs drive mode
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*
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* @param[in] pin Gpiohs pin
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* @param[in] mode Gpiohs pin drive mode
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*/
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void gpiohs_set_drive_mode(size_t pin, gpio_drive_mode mode);
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/**
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* @brief Get Gpiohs pin value
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*
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* @param[in] pin Gpiohs pin
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* @return Pin value
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*
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* - GPIO_PV_Low Gpiohs pin low
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* - GPIO_PV_High Gpiohs pin high
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*/
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gpio_pin_value gpiohs_get_pin_value(size_t pin);
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/**
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* @brief Set Gpiohs pin value
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*
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* @param[in] pin Gpiohs pin
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* @param[in] value Gpiohs pin value
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*/
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void gpiohs_set_pin_value(size_t pin, gpio_pin_value value);
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/**
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* @brief Set Gpiohs pin edge for interrupt
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*
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* @param[in] pin Gpiohs pin
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* @param[in] edge Gpiohs pin edge type
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*/
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void gpiohs_set_pin_edge(size_t pin, gpio_pin_edge edge);
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/**
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* @brief Set Gpiohs pin interrupt
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*
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* @param[in] pin Gpiohs pin
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* @param[in] priority Gpiohs pin interrupt priority
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* @param[in] func Gpiohs pin interrupt service routine
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*/
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void gpiohs_set_irq(size_t pin, uint32_t priority, void(*func)());
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_GPIOHS_H */
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