435 lines
17 KiB
C
435 lines
17 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_I2C_H
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#define _DRIVER_I2C_H
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#include <stdint.h>
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#include <stddef.h>
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#include "dmac.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I2C_MAX_NUM 3
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/* clang-format off */
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struct i2c_t
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{
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/* I2C Control Register (0x00) */
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volatile uint32_t con;
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/* I2C Target Address Register (0x04) */
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volatile uint32_t tar;
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/* I2C Slave Address Register (0x08) */
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volatile uint32_t sar;
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/* reserved (0x0c) */
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volatile uint32_t resv1;
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/* I2C Data Buffer and Command Register (0x10) */
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volatile uint32_t data_cmd;
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/* I2C Standard Speed Clock SCL High Count Register (0x14) */
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volatile uint32_t ss_scl_hcnt;
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/* I2C Standard Speed Clock SCL Low Count Register (0x18) */
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volatile uint32_t ss_scl_lcnt;
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/* reserverd (0x1c-0x28) */
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volatile uint32_t resv2[4];
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/* I2C Interrupt Status Register (0x2c) */
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volatile uint32_t intr_stat;
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/* I2C Interrupt Mask Register (0x30) */
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volatile uint32_t intr_mask;
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/* I2C Raw Interrupt Status Register (0x34) */
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volatile uint32_t raw_intr_stat;
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/* I2C Receive FIFO Threshold Register (0x38) */
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volatile uint32_t rx_tl;
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/* I2C Transmit FIFO Threshold Register (0x3c) */
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volatile uint32_t tx_tl;
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/* I2C Clear Combined and Individual Interrupt Register (0x40) */
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volatile uint32_t clr_intr;
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/* I2C Clear RX_UNDER Interrupt Register (0x44) */
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volatile uint32_t clr_rx_under;
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/* I2C Clear RX_OVER Interrupt Register (0x48) */
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volatile uint32_t clr_rx_over;
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/* I2C Clear TX_OVER Interrupt Register (0x4c) */
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volatile uint32_t clr_tx_over;
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/* I2C Clear RD_REQ Interrupt Register (0x50) */
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volatile uint32_t clr_rd_req;
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/* I2C Clear TX_ABRT Interrupt Register (0x54) */
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volatile uint32_t clr_tx_abrt;
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/* I2C Clear RX_DONE Interrupt Register (0x58) */
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volatile uint32_t clr_rx_done;
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/* I2C Clear ACTIVITY Interrupt Register (0x5c) */
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volatile uint32_t clr_activity;
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/* I2C Clear STOP_DET Interrupt Register (0x60) */
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volatile uint32_t clr_stop_det;
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/* I2C Clear START_DET Interrupt Register (0x64) */
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volatile uint32_t clr_start_det;
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/* I2C Clear GEN_CALL Interrupt Register (0x68) */
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volatile uint32_t clr_gen_call;
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/* I2C Enable Register (0x6c) */
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volatile uint32_t enable;
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/* I2C Status Register (0x70) */
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volatile uint32_t status;
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/* I2C Transmit FIFO Level Register (0x74) */
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volatile uint32_t txflr;
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/* I2C Receive FIFO Level Register (0x78) */
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volatile uint32_t rxflr;
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/* I2C SDA Hold Time Length Register (0x7c) */
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volatile uint32_t sda_hold;
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/* I2C Transmit Abort Source Register (0x80) */
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volatile uint32_t tx_abrt_source;
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/* reserved (0x84) */
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volatile uint32_t resv3;
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/* I2C DMA Control Register (0x88) */
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volatile uint32_t dma_cr;
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/* I2C DMA Transmit Data Level Register (0x8c) */
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volatile uint32_t dma_tdlr;
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/* I2C DMA Receive Data Level Register (0x90) */
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volatile uint32_t dma_rdlr;
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/* I2C SDA Setup Register (0x94) */
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volatile uint32_t sda_setup;
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/* I2C ACK General Call Register (0x98) */
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volatile uint32_t general_call;
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/* I2C Enable Status Register (0x9c) */
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volatile uint32_t enable_status;
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/* I2C SS, FS or FM+ spike suppression limit (0xa0) */
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volatile uint32_t fs_spklen;
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/* reserved (0xa4-0xf0) */
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volatile uint32_t resv4[20];
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/* I2C Component Parameter Register 1 (0xf4) */
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volatile uint32_t comp_param_1;
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/* I2C Component Version Register (0xf8) */
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volatile uint32_t comp_version;
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/* I2C Component Type Register (0xfc) */
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volatile uint32_t comp_type;
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} __attribute__((packed, aligned(4)));
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/* I2C Control Register*/
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#define I2C_CON_MASTER_MODE 0x00000001U
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#define I2C_CON_SPEED_MASK 0x00000006U
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#define I2C_CON_SPEED(x) ((x) << 1)
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#define I2C_CON_10BITADDR_SLAVE 0x00000008U
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#define I2C_CON_RESTART_EN 0x00000020U
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#define I2C_CON_SLAVE_DISABLE 0x00000040U
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#define I2C_CON_STOP_DET_IFADDRESSED 0x00000080U
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#define I2C_CON_TX_EMPTY_CTRL 0x00000100U
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/* I2C Target Address Register*/
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#define I2C_TAR_ADDRESS_MASK 0x000003FFU
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#define I2C_TAR_ADDRESS(x) ((x) << 0)
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#define I2C_TAR_GC_OR_START 0x00000400U
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#define I2C_TAR_SPECIAL 0x00000800U
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#define I2C_TAR_10BITADDR_MASTER 0x00001000U
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/* I2C Slave Address Register*/
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#define I2C_SAR_ADDRESS_MASK 0x000003FFU
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#define I2C_SAR_ADDRESS(x) ((x) << 0)
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/* I2C Rx/Tx Data Buffer and Command Register*/
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#define I2C_DATA_CMD_CMD 0x00000100U
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#define I2C_DATA_CMD_DATA_MASK 0x000000FFU
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#define I2C_DATA_CMD_DATA(x) ((x) << 0)
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/* Standard Speed I2C Clock SCL High Count Register*/
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#define I2C_SS_SCL_HCNT_COUNT_MASK 0x0000FFFFU
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#define I2C_SS_SCL_HCNT_COUNT(x) ((x) << 0)
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/* Standard Speed I2C Clock SCL Low Count Register*/
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#define I2C_SS_SCL_LCNT_COUNT_MASK 0x0000FFFFU
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#define I2C_SS_SCL_LCNT_COUNT(x) ((x) << 0)
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/* I2C Interrupt Status Register*/
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#define I2C_INTR_STAT_RX_UNDER 0x00000001U
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#define I2C_INTR_STAT_RX_OVER 0x00000002U
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#define I2C_INTR_STAT_RX_FULL 0x00000004U
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#define I2C_INTR_STAT_TX_OVER 0x00000008U
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#define I2C_INTR_STAT_TX_EMPTY 0x00000010U
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#define I2C_INTR_STAT_RD_REQ 0x00000020U
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#define I2C_INTR_STAT_TX_ABRT 0x00000040U
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#define I2C_INTR_STAT_RX_DONE 0x00000080U
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#define I2C_INTR_STAT_ACTIVITY 0x00000100U
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#define I2C_INTR_STAT_STOP_DET 0x00000200U
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#define I2C_INTR_STAT_START_DET 0x00000400U
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#define I2C_INTR_STAT_GEN_CALL 0x00000800U
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/* I2C Interrupt Mask Register*/
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#define I2C_INTR_MASK_RX_UNDER 0x00000001U
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#define I2C_INTR_MASK_RX_OVER 0x00000002U
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#define I2C_INTR_MASK_RX_FULL 0x00000004U
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#define I2C_INTR_MASK_TX_OVER 0x00000008U
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#define I2C_INTR_MASK_TX_EMPTY 0x00000010U
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#define I2C_INTR_MASK_RD_REQ 0x00000020U
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#define I2C_INTR_MASK_TX_ABRT 0x00000040U
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#define I2C_INTR_MASK_RX_DONE 0x00000080U
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#define I2C_INTR_MASK_ACTIVITY 0x00000100U
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#define I2C_INTR_MASK_STOP_DET 0x00000200U
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#define I2C_INTR_MASK_START_DET 0x00000400U
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#define I2C_INTR_MASK_GEN_CALL 0x00000800U
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/* I2C Raw Interrupt Status Register*/
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#define I2C_RAW_INTR_MASK_RX_UNDER 0x00000001U
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#define I2C_RAW_INTR_MASK_RX_OVER 0x00000002U
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#define I2C_RAW_INTR_MASK_RX_FULL 0x00000004U
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#define I2C_RAW_INTR_MASK_TX_OVER 0x00000008U
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#define I2C_RAW_INTR_MASK_TX_EMPTY 0x00000010U
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#define I2C_RAW_INTR_MASK_RD_REQ 0x00000020U
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#define I2C_RAW_INTR_MASK_TX_ABRT 0x00000040U
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#define I2C_RAW_INTR_MASK_RX_DONE 0x00000080U
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#define I2C_RAW_INTR_MASK_ACTIVITY 0x00000100U
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#define I2C_RAW_INTR_MASK_STOP_DET 0x00000200U
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#define I2C_RAW_INTR_MASK_START_DET 0x00000400U
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#define I2C_RAW_INTR_MASK_GEN_CALL 0x00000800U
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/* I2C Receive FIFO Threshold Register*/
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#define I2C_RX_TL_VALUE_MASK 0x00000007U
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#define I2C_RX_TL_VALUE(x) ((x) << 0)
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/* I2C Transmit FIFO Threshold Register*/
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#define I2C_TX_TL_VALUE_MASK 0x00000007U
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#define I2C_TX_TL_VALUE(x) ((x) << 0)
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/* Clear Combined and Individual Interrupt Register*/
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#define I2C_CLR_INTR_CLR 0x00000001U
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/* Clear RX_UNDER Interrupt Register*/
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#define I2C_CLR_RX_UNDER_CLR 0x00000001U
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/* Clear RX_OVER Interrupt Register*/
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#define I2C_CLR_RX_OVER_CLR 0x00000001U
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/* Clear TX_OVER Interrupt Register*/
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#define I2C_CLR_TX_OVER_CLR 0x00000001U
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/* Clear RD_REQ Interrupt Register*/
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#define I2C_CLR_RD_REQ_CLR 0x00000001U
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/* Clear TX_ABRT Interrupt Register*/
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#define I2C_CLR_TX_ABRT_CLR 0x00000001U
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/* Clear RX_DONE Interrupt Register*/
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#define I2C_CLR_RX_DONE_CLR 0x00000001U
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/* Clear ACTIVITY Interrupt Register*/
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#define I2C_CLR_ACTIVITY_CLR 0x00000001U
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/* Clear STOP_DET Interrupt Register*/
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#define I2C_CLR_STOP_DET_CLR 0x00000001U
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/* Clear START_DET Interrupt Register*/
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#define I2C_CLR_START_DET_CLR 0x00000001U
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/* Clear GEN_CALL Interrupt Register*/
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#define I2C_CLR_GEN_CALL_CLR 0x00000001U
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/* I2C Enable Register*/
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#define I2C_ENABLE_ENABLE 0x00000001U
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#define I2C_ENABLE_ABORT 0x00000002U
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#define I2C_ENABLE_TX_CMD_BLOCK 0x00000004U
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/* I2C Status Register*/
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#define I2C_STATUS_ACTIVITY 0x00000001U
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#define I2C_STATUS_TFNF 0x00000002U
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#define I2C_STATUS_TFE 0x00000004U
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#define I2C_STATUS_RFNE 0x00000008U
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#define I2C_STATUS_RFF 0x00000010U
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#define I2C_STATUS_MST_ACTIVITY 0x00000020U
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#define I2C_STATUS_SLV_ACTIVITY 0x00000040U
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/* I2C Transmit FIFO Level Register*/
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#define I2C_TXFLR_VALUE_MASK 0x00000007U
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#define I2C_TXFLR_VALUE(x) ((x) << 0)
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/* I2C Receive FIFO Level Register*/
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#define I2C_RXFLR_VALUE_MASK 0x00000007U
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#define I2C_RXFLR_VALUE(x) ((x) << 0)
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/* I2C SDA Hold Time Length Register*/
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#define I2C_SDA_HOLD_TX_MASK 0x0000FFFFU
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#define I2C_SDA_HOLD_TX(x) ((x) << 0)
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#define I2C_SDA_HOLD_RX_MASK 0x00FF0000U
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#define I2C_SDA_HOLD_RX(x) ((x) << 16)
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/* I2C Transmit Abort Source Register*/
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#define I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK 0x00000001U
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#define I2C_TX_ABRT_SOURCE_10B_ADDR1_NOACK 0x00000002U
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#define I2C_TX_ABRT_SOURCE_10B_ADDR2_NOACK 0x00000004U
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#define I2C_TX_ABRT_SOURCE_TXDATA_NOACK 0x00000008U
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#define I2C_TX_ABRT_SOURCE_GCALL_NOACK 0x00000010U
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#define I2C_TX_ABRT_SOURCE_GCALL_READ 0x00000020U
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#define I2C_TX_ABRT_SOURCE_HS_ACKDET 0x00000040U
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#define I2C_TX_ABRT_SOURCE_SBYTE_ACKDET 0x00000080U
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#define I2C_TX_ABRT_SOURCE_HS_NORSTRT 0x00000100U
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#define I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT 0x00000200U
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#define I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT 0x00000400U
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#define I2C_TX_ABRT_SOURCE_MASTER_DIS 0x00000800U
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#define I2C_TX_ABRT_SOURCE_MST_ARBLOST 0x00001000U
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#define I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO 0x00002000U
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#define I2C_TX_ABRT_SOURCE_SLV_ARBLOST 0x00004000U
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#define I2C_TX_ABRT_SOURCE_SLVRD_INTX 0x00008000U
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#define I2C_TX_ABRT_SOURCE_USER_ABRT 0x00010000U
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/* DMA Control Register*/
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#define I2C_DMA_CR_RDMAE 0x00000001U
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#define I2C_DMA_CR_TDMAE 0x00000002U
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/* DMA Transmit Data Level Register*/
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#define I2C_DMA_TDLR_VALUE_MASK 0x00000007U
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#define I2C_DMA_TDLR_VALUE(x) ((x) << 0)
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/* DMA Receive Data Level Register*/
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#define I2C_DMA_RDLR_VALUE_MASK 0x00000007U
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#define I2C_DMA_RDLR_VALUE(x) ((x) << 0)
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/* I2C SDA Setup Register*/
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#define I2C_SDA_SETUP_VALUE_MASK 0x000000FFU
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#define I2C_SDA_SETUP_VALUE(x) ((x) << 0)
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/* I2C ACK General Call Register*/
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#define I2C_ACK_GENERAL_CALL_ENABLE 0x00000001U
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/* I2C Enable Status Register*/
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#define I2C_ENABLE_STATUS_IC_ENABLE 0x00000001U
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#define I2C_ENABLE_STATUS_SLV_DIS_BUSY 0x00000002U
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#define I2C_ENABLE_STATUS_SLV_RX_DATA_LOST 0x00000004U
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/* I2C SS, FS or FM+ spike suppression limit*/
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#define I2C_FS_SPKLEN_VALUE_MASK 0x000000FFU
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#define I2C_FS_SPKLEN_VALUE(x) ((x) << 0)
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/* Component Parameter Register 1*/
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#define I2C_COMP_PARAM1_APB_DATA_WIDTH 0x00000003U
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#define I2C_COMP_PARAM1_MAX_SPEED_MODE 0x0000000CU
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#define I2C_COMP_PARAM1_HC_COUNT_VALUES 0x00000010U
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#define I2C_COMP_PARAM1_INTR_IO 0x00000020U
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#define I2C_COMP_PARAM1_HAS_DMA 0x00000040U
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#define I2C_COMP_PARAM1_ENCODED_PARAMS 0x00000080U
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#define I2C_COMP_PARAM1_RX_BUFFER_DEPTH 0x0000FF00U
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#define I2C_COMP_PARAM1_TX_BUFFER_DEPTH 0x00FF0000U
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/* I2C Component Version Register*/
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#define I2C_COMP_VERSION_VALUE 0xFFFFFFFFU
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/* I2C Component Type Register*/
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#define I2C_COMP_TYPE_VALUE 0xFFFFFFFFU
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/* clang-format on */
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extern volatile struct i2c_t *const i2c[3];
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typedef enum
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{
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I2C_BS_STANDARD,
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I2C_BS_FAST,
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I2C_BS_HIGHSPEED
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} i2c_bus_speed_mode;
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/**
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* @brief I2c init
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*
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* @param[in] sel i2c bus
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* @param[in] clk_pin i2c clk pin
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* @param[in] data_pin i2c data pin
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*/
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void i2c_init(uint8_t sel, int clk_pin, int data_pin);
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/**
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* @brief I2c pin init
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*
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* @param[in] sel i2c bus
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* @param[in] clk_pin i2c clk pin
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* @param[in] data_pin i2c data pin
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*/
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void i2c_pin_init(uint8_t sel, int clk_pin, int data_pin);
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/**
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* @brief I2c clk init
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*
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* @param[in] sel i2c bus
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*/
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void i2c_clk_init(uint8_t sel);
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/**
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* @brief I2c set param
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*
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* @param[in] sel i2c bus
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* @param[in] slaveAddress i2c slave address
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* @param[in] address_width address width 7bit or 10bit
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* @param[in] bus_speed_mode i2c rate
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*/
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void i2c_config(uint8_t sel, size_t slaveAddress, size_t address_width,
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i2c_bus_speed_mode bus_speed_mode);
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/**
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* @brief I2c send data
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*
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* @param[in] sel i2c bus
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* @param[in] reg i2c slave reg address
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* @param[in] data_buf send data
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* @param[in] length send length
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int i2c_write_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length);
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/**
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* @brief I2c receive data
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*
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* @param[in] sel i2c bus
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* @param[in] reg i2c slave reg address
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* @param[in] data_buf receive data
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* @param[in] length receive length
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int i2c_read_reg(uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length);
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/**
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* @brief I2c send data by dma
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*
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* @param[in] channel_num dma channel
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* @param[in] sel i2c bus
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* @param[in] reg i2c slave reg address
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* @param[in] data_buf send data
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* @param[in] length send length
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int i2c_write_reg_dma(dmac_channel_number channel_num, uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length);
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/**
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* @brief I2c receive data
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*
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* @param[in] channel_num dma channel
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* @param[in] sel i2c bus
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* @param[in] reg i2c slave reg address
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* @param[in] data_buf receive data
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* @param[in] length receive length
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*
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* @return result
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* - 0 Success
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* - Other Fail
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*/
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int i2c_read_reg_dma(dmac_channel_number w_channel_num, dmac_channel_number r_channel_num,
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uint8_t sel, uint8_t reg, uint8_t *data_buf, uint8_t length);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_I2C_H */
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