450 lines
14 KiB
C
450 lines
14 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_SPI_H
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#define _DRIVER_SPI_H
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#include <stdint.h>
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#include <stddef.h>
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#include "dmac.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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struct spi_t {
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/* SPI Control Register 0 (0x00)*/
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volatile uint32_t ctrlr0;
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/* SPI Control Register 1 (0x04)*/
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volatile uint32_t ctrlr1;
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/* SPI Enable Register (0x08)*/
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volatile uint32_t ssienr;
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/* SPI Microwire Control Register (0x0c)*/
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volatile uint32_t mwcr;
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/* SPI Slave Enable Register (0x10)*/
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volatile uint32_t ser;
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/* SPI Baud Rate Select (0x14)*/
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volatile uint32_t baudr;
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/* SPI Transmit FIFO Threshold Level (0x18)*/
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volatile uint32_t txftlr;
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/* SPI Receive FIFO Threshold Level (0x1c)*/
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volatile uint32_t rxftlr;
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/* SPI Transmit FIFO Level Register (0x20)*/
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volatile uint32_t txflr;
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/* SPI Receive FIFO Level Register (0x24)*/
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volatile uint32_t rxflr;
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/* SPI Status Register (0x28)*/
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volatile uint32_t sr;
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/* SPI Interrupt Mask Register (0x2c)*/
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volatile uint32_t imr;
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/* SPI Interrupt Status Register (0x30)*/
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volatile uint32_t isr;
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/* SPI Raw Interrupt Status Register (0x34)*/
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volatile uint32_t risr;
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/* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38)*/
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volatile uint32_t txoicr;
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/* SPI Receive FIFO Overflow Interrupt Clear Register (0x3c)*/
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volatile uint32_t rxoicr;
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/* SPI Receive FIFO Underflow Interrupt Clear Register (0x40)*/
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volatile uint32_t rxuicr;
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/* SPI Multi-Master Interrupt Clear Register (0x44)*/
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volatile uint32_t msticr;
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/* SPI Interrupt Clear Register (0x48)*/
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volatile uint32_t icr;
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/* SPI DMA Control Register (0x4c)*/
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volatile uint32_t dmacr;
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/* SPI DMA Transmit Data Level (0x50)*/
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volatile uint32_t dmatdlr;
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/* SPI DMA Receive Data Level (0x54)*/
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volatile uint32_t dmardlr;
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/* SPI Identification Register (0x58)*/
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volatile uint32_t idr;
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/* SPI DWC_ssi component version (0x5c)*/
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volatile uint32_t ssic_version_id;
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/* SPI Data Register 0-36 (0x60 -- 0xec)*/
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volatile uint32_t dr[36];
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/* SPI RX Sample Delay Register (0xf0)*/
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volatile uint32_t rx_sample_delay;
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/* SPI SPI Control Register (0xf4)*/
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volatile uint32_t spi_ctrlr0;
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/* reserved (0xf8)*/
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volatile uint32_t resv;
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/* SPI XIP Mode bits (0xfc)*/
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volatile uint32_t xip_mode_bits;
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/* SPI XIP INCR transfer opcode (0x100)*/
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volatile uint32_t xip_incr_inst;
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/* SPI XIP WRAP transfer opcode (0x104)*/
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volatile uint32_t xip_wrap_inst;
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/* SPI XIP Control Register (0x108)*/
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volatile uint32_t xip_ctrl;
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/* SPI XIP Slave Enable Register (0x10c)*/
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volatile uint32_t xip_ser;
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/* SPI XIP Receive FIFO Overflow Interrupt Clear Register (0x110)*/
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volatile uint32_t xrxoicr;
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/* SPI XIP time out register for continuous transfers (0x114)*/
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volatile uint32_t xip_cnt_time_out;
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volatile uint32_t endian;
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} __attribute__((packed, aligned(4)));
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/* clang-format on */
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typedef enum
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{
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SPI_MODE_0,
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SPI_MODE_1,
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SPI_MODE_2,
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SPI_MODE_3,
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} spi_mode;
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typedef enum
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{
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SPI_FF_STANDARD,
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SPI_FF_DUAL,
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SPI_FF_QUAD,
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SPI_FF_OCTAL
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} spi_frame_format;
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typedef enum
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{
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SPI_AITM_STANDARD,
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SPI_AITM_ADDR_STANDARD,
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SPI_AITM_AS_FRAME_FORMAT
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} spi_addr_inst_trans_mode;
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typedef enum
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{
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SPI_TMOD_TRANS_RECV,
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SPI_TMOD_TRANS,
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SPI_TMOD_RECV,
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SPI_TMOD_EEROM
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}spi_transfer_mode;
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typedef enum _spi_transfer_width
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{
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SPI_TRANS_CHAR = 0x0,
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SPI_TRANS_SHORT = 0x1,
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SPI_TRANS_INT = 0x2,
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}spi_transfer_width;
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extern volatile struct spi_t *const spi[4];
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/**
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* @brief Spi initialize
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*
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* @param[in] spi_bus Spi bus number
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_init(uint8_t spi_bus);
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/**
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* @brief Spi master mode configuration
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] mode Spi mode
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* @param[in] frame_format Spi frame format
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* @param[in] data_bit_length Spi data bit length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_master_config(uint8_t spi_bus, spi_mode mode, spi_frame_format frame_format,
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size_t data_bit_length);
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/**
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* @brief Spi transmit configuration
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] instruction_length Instruction length
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* @param[in] address_length Address length
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* @param[in] wait_cycles Wait cycles
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* @param[in] trans_mode Spi transfer mode
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*
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*/
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void spi_trans_config(uint8_t spi_bus, size_t instruction_length, size_t address_length,
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size_t wait_cycles, spi_addr_inst_trans_mode trans_mode);
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/**
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* @brief Spi send data
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_send_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff,
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uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len);
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/**
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* @brief Spi receive data
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff,
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uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len);
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/**
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* @brief Spi special receive data
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_special_receive_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff,
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uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len);
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/**
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* @brief Spi special send data
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_special_send_data(uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff,
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uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len);
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/**
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* @brief Spi set transfer mode
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] tmod Spi tmod
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*
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*/
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void spi_set_tmod(uint8_t spi_bus, uint32_t tmod);
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/**
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* @brief Spi set frame format
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] spi_frf Spi frame format
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*
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*/
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void spi_set_frame_format(uint8_t spi_bus, uint32_t spi_frf);
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/**
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* @brief Spi get frame format
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*
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* @param[in] spi_bus Spi bus number
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*
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* @return frame foramt
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*/
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int spi_get_frame_format(uint8_t spi_bus);
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/**
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* @brief Spi set work mode
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] mode Spi work mode
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*
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*/
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void spi_set_work_mode(uint8_t spi_bus, spi_mode mode);
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/**
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* @brief Spi set frame size
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] dfs Spi frame size
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*
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*/
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void spi_set_frame_size(uint8_t spi_bus, uint32_t dfs);
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/**
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* @brief Spi set wait cycles
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] wcycles Spi wait cycles
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*
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*/
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void spi_set_wait_cycles(uint8_t spi_bus, uint32_t wcycles);
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/**
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* @brief Spi set instruction length
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] instruction_length Spi instruction length
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*
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*/
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void spi_set_inst_length(uint8_t spi_bus, uint32_t instruction_length);
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/**
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* @brief Spi set address length
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] address_length Spi address length
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*
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*/
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void spi_set_address_length(uint8_t spi_bus, uint32_t address_length);
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/**
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* @brief Spi set transfer mode
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*
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* @param[in] spi_bus Spi bus number
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* @param[in] trans_mode Spi tansfer mode
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*
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*/
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void spi_set_trans_mode(uint8_t spi_bus, spi_addr_inst_trans_mode trans_mode);
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/**
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* @brief Spi send data by dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_send_data_dma(dmac_channel_number channel_num, uint8_t spi_bus, uint32_t chip_sel,
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uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len);
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/**
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* @brief Spi receive data by dma
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*
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* @param[in] w_channel_num Dmac write channel number
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* @param[in] r_channel_num Dmac read channel number
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_receive_data_dma(dmac_channel_number w_channel_num, dmac_channel_number r_channel_num,
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uint8_t spi_bus, uint32_t chip_sel, uint8_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len);
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/**
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* @brief Spi special send data by dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_special_send_data_dma(dmac_channel_number channel_num,uint8_t spi_bus, uint32_t chip_sel,
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uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *tx_buff, uint32_t tx_len);
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/**
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* @brief Spi special receive data by dma
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*
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* @param[in] w_channel_num Dmac write channel number
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* @param[in] r_channel_num Dmac read channel number
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_special_receive_data_dma(dmac_channel_number w_channel_num, dmac_channel_number r_channel_num,
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uint8_t spi_bus, uint32_t chip_sel, uint32_t *cmd_buff, uint8_t cmd_len, uint8_t *rx_buff, uint32_t rx_len);
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/**
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* @brief Spi fill dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_fill_dma(dmac_channel_number channel_num,uint8_t spi_bus, uint32_t chip_sel,
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uint32_t *cmd_buff, uint32_t cmd_len);
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/**
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* @brief Spi normal send by dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_bus Spi bus number
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* @param[in] chip_sel Spi chip select
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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* @param[in] stw Spi transfer width
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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int spi_normal_send_dma(dmac_channel_number channel_num, uint8_t spi_bus, uint32_t chip_sel,
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void *tx_buff, uint32_t tx_len, spi_transfer_width stw);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_SPI_H */
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