190 lines
6.4 KiB
C
190 lines
6.4 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_WDT_H
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#define _DRIVER_WDT_H
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#include <stdint.h>
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#include <stddef.h>
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#include <plic.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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struct wdt_t
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{
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/* WDT Control Register (0x00) */
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volatile uint32_t cr;
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/* WDT Timeout Range Register (0x04) */
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volatile uint32_t torr;
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/* WDT Current Counter Value Register (0x08) */
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volatile uint32_t ccvr;
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/* WDT Counter Restart Register (0x0c) */
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volatile uint32_t crr;
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/* WDT Interrupt Status Register (0x10) */
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volatile uint32_t stat;
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/* WDT Interrupt Clear Register (0x14) */
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volatile uint32_t eoi;
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/* reserverd (0x18) */
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volatile uint32_t resv1;
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/* WDT Protection level Register (0x1c) */
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volatile uint32_t prot_level;
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/* reserved (0x20-0xe0) */
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volatile uint32_t resv4[49];
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/* WDT Component Parameters Register 5 (0xe4) */
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volatile uint32_t comp_param_5;
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/* WDT Component Parameters Register 4 (0xe8) */
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volatile uint32_t comp_param_4;
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/* WDT Component Parameters Register 3 (0xec) */
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volatile uint32_t comp_param_3;
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/* WDT Component Parameters Register 2 (0xf0) */
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volatile uint32_t comp_param_2;
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/* WDT Component Parameters Register 1 (0xf4) */
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volatile uint32_t comp_param_1;
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/* WDT Component Version Register (0xf8) */
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volatile uint32_t comp_version;
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/* WDT Component Type Register (0xfc) */
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volatile uint32_t comp_type;
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} __attribute__((packed, aligned(4)));
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#define WDT_RESET_ALL 0x00000000U
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#define WDT_RESET_CPU 0x00000001U
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/* WDT Control Register */
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#define WDT_CR_ENABLE 0x00000001U
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#define WDT_CR_RMOD_MASK 0x00000002U
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#define WDT_CR_RMOD_RESET 0x00000000U
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#define WDT_CR_RMOD_INTERRUPT 0x00000002U
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#define WDT_CR_RPL_MASK 0x0000001CU
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#define WDT_CR_RPL(x) ((x) << 2)
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/* WDT Timeout Range Register */
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#define WDT_TORR_TOP_MASK 0x000000FFU
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#define WDT_TORR_TOP(x) ((x) << 4 | (x) << 0)
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/* WDT Current Counter Value Register */
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#define WDT_CCVR_MASK 0xFFFFFFFFU
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/* WDT Counter Restart Register */
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#define WDT_CRR_MASK 0x00000076U
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/* WDT Interrupt Status Register */
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#define WDT_STAT_MASK 0x00000001U
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/* WDT Interrupt Clear Register */
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#define WDT_EOI_MASK 0x00000001U
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/* WDT Protection level Register */
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#define WDT_PROT_LEVEL_MASK 0x00000007U
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/* WDT Component Parameter Register 5 */
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#define WDT_COMP_PARAM_5_CP_WDT_USER_TOP_MAX_MASK 0xFFFFFFFFU
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/* WDT Component Parameter Register 4 */
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#define WDT_COMP_PARAM_4_CP_WDT_USER_TOP_INIT_MAX_MASK 0xFFFFFFFFU
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/* WDT Component Parameter Register 3 */
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#define WDT_COMP_PARAM_3_CD_WDT_TOP_RST_MASK 0xFFFFFFFFU
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/* WDT Component Parameter Register 2 */
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#define WDT_COMP_PARAM_3_CP_WDT_CNT_RST_MASK 0xFFFFFFFFU
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/* WDT Component Parameter Register 1 */
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#define WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MASK 0x00000001U
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#define WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MASK 0x00000002U
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#define WDT_COMP_PARAM_1_WDT_DUAL_TOP_MASK 0x00000004U
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#define WDT_COMP_PARAM_1_WDT_HC_RMOD_MASK 0x00000008U
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#define WDT_COMP_PARAM_1_WDT_HC_RPL_MASK 0x00000010U
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#define WDT_COMP_PARAM_1_WDT_HC_TOP_MASK 0x00000020U
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#define WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MASK 0x00000040U
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#define WDT_COMP_PARAM_1_WDT_PAUSE_MASK 0x00000080U
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#define WDT_COMP_PARAM_1_APB_DATA_WIDTH_MASK 0x00000300U
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#define WDT_COMP_PARAM_1_WDT_DFLT_RPL_MASK 0x00001C00U
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#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_MASK 0x000F0000U
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#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MASK 0x00F00000U
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#define WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MASK 0x1F000000U
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/* WDT Component Version Register */
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#define WDT_COMP_VERSION_MASK 0xFFFFFFFFU
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/* WDT Component Type Register */
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#define WDT_COMP_TYPE_MASK 0xFFFFFFFFU
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/* clang-format on */
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/**
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* @brief WDT object instanse
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*/
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extern volatile struct wdt_t *const wdt[2];
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/**
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* @brief Feed wdt
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*/
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void wdt_feed(uint8_t id);
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/**
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* @brief Enable wdt
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*
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* @param[in] id Wdt id 0 or 1
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*
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*/
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void wdt_enable(uint8_t id);
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/**
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* @brief Clear wdt interrupt
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*
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* @param[in] id Wdt id 0 or 1
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*
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*/
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void wdt_interrupt_clear(uint8_t id);
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/**
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* @brief Clear wdt interrupt
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*
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* @param[in] id Wdt id 0 or 1
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* @param[in] mode Set wdt work mode
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*
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*/
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void wdt_response_mode(uint8_t id, uint8_t mode);
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/**
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* @brief Set wdt timeout
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*
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* @param[in] id Wdt id 0 or 1
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* @param[in] timeout Wdt trigger time
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*
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*/
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void wdt_timeout_set(uint8_t id, uint8_t timeout);
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/**
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* @brief Start wdt
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*
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* @param[in] id Wdt id 0 or 1
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* @param[in] toms Wdt trigger time
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*
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*/
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int wdt_start(uint8_t id, size_t toms);
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/**
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* @brief Stop wdt
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*
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* @param[in] id Wdt id 0 or 1
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*
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*/
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void wdt_stop(uint8_t id);
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/**
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* @brief Set wdt interrupt function
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*
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* @param[in] id Wdt id 0 or 1
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* @param[in] on_irq Wdt interrupt function
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*
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*/
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void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_WDT_H */
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