116 lines
4.1 KiB
C
116 lines
4.1 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "nt35310.h"
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#include "sysctl.h"
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#include "fpioa.h"
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#include "gpiohs.h"
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#include "spi.h"
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#include "dmac.h"
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#include "plic.h"
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#include <common.h>
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#define __SPI_SYSCTL(x, y) SYSCTL_##x##_SPI##y
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#define _SPI_SYSCTL(x, y) __SPI_SYSCTL(x, y)
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#define SPI_SYSCTL(x) _SPI_SYSCTL(x, SPI_CHANNEL)
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#define __SPI_SS(x, y) FUNC_SPI##x##_SS##y
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#define _SPI_SS(x, y) __SPI_SS(x, y)
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#define SPI_SS _SPI_SS(SPI_CHANNEL, SPI_SLAVE_SELECT)
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#define __SPI(x, y) FUNC_SPI##x##_##y
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#define _SPI(x, y) __SPI(x, y)
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#define SPI(x) _SPI(SPI_CHANNEL, x)
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void init_dcx(void)
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{
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gpiohs_init();
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fpioa_set_function(DCX_IO, FUNC_GPIOHS0 + DCX_GPIONUM);/*dcx*/
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gpiohs_set_drive_mode(DCX_GPIONUM, GPIO_DM_Output);
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gpiohs_set_pin_value(DCX_GPIONUM, GPIO_PV_High);
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}
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void set_dcx_control(void)
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{
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gpiohs_set_pin_value(DCX_GPIONUM, GPIO_PV_Low);
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}
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void set_dcx_data(void)
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{
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gpiohs_set_pin_value(DCX_GPIONUM, GPIO_PV_High);
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}
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void pin_mux_init(void)
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{
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fpioa_set_function(31, SPI_SS);
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fpioa_set_function(32, SPI(SCLK));
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sysctl->misc.reserved0 = 1;
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}
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void tft_hard_init(void)
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{
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init_dcx();
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pin_mux_init();
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spi_master_config(SPI_CHANNEL, SPI_MODE_2, SPI_FF_OCTAL, 8);
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}
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void tft_write_command(uint8_t cmd)
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{
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set_dcx_control();
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spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS);
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spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL);
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spi_set_frame_size(SPI_CHANNEL, 8);
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spi_trans_config(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
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spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, (uint8_t *)(&cmd), 1,SPI_TRANS_CHAR);
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}
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void tft_write_byte(uint8_t *data_buf, uint32_t length)
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{
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set_dcx_data();
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spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS);
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spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL);
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spi_set_frame_size(SPI_CHANNEL, 8);
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spi_trans_config(SPI_CHANNEL, 8/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
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spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT, data_buf, length, SPI_TRANS_CHAR);
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}
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void tft_write_half(uint16_t *data_buf, uint32_t length)
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{
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set_dcx_data();
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spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS);
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spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL);
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spi_set_frame_size(SPI_CHANNEL, 16);
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spi_trans_config(SPI_CHANNEL, 16/*instrction length*/, 0/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
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spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_SHORT);
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}
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void tft_write_word(uint32_t *data_buf, uint32_t length, uint32_t flag)
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{
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set_dcx_data();
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spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS);
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spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL);
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spi_set_frame_size(SPI_CHANNEL, 32);
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spi_trans_config(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
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spi_normal_send_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length, SPI_TRANS_INT);
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}
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void tft_fill_data(uint32_t *data_buf, uint32_t length)
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{
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set_dcx_data();
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spi_set_tmod(SPI_CHANNEL, SPI_TMOD_TRANS);
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spi_set_frame_format(SPI_CHANNEL, SPI_FF_OCTAL);
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spi_set_frame_size(SPI_CHANNEL, 32);
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spi_trans_config(SPI_CHANNEL, 0/*instrction length*/, 32/*address length*/, 0/*wait cycles*/, SPI_AITM_AS_FRAME_FORMAT/*spi address trans mode*/);
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spi_fill_dma(DMAC_CHANNEL0, SPI_CHANNEL, 1 << SPI_SLAVE_SELECT,data_buf, length);
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}
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