521 lines
15 KiB
C
521 lines
15 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <math.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "apu.h"
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#include "syscalls.h"
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#include "sysctl.h"
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#define BEAFORMING_BASE_ADDR (0x50250200)
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#ifndef M_PI
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#define M_PI 3.14159265358979323846264338327950288
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#endif
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volatile apu_reg_t *const apu = (volatile apu_reg_t *)BEAFORMING_BASE_ADDR;
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/*
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Voice strength average value right shift factor. When performing sound direction detect,
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the average value of samples from different channels is required, this right shift factor
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is used to perform division.
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0x0: no right shift; 0x1: right shift by 1-bit;
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. . . . . .
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0xF: right shift by 15-bit.
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*/
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void apu_set_audio_gain(uint16_t gain)
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{
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apu_ch_cfg_t ch_cfg = apu->bf_ch_cfg_reg;
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ch_cfg.we_bf_target_dir = 0;
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ch_cfg.we_bf_sound_ch_en = 0;
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ch_cfg.we_data_src_mode = 0;
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ch_cfg.we_audio_gain = 1;
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ch_cfg.audio_gain = gain;
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apu->bf_ch_cfg_reg = ch_cfg;
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}
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/*set sampling shift*/
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void apu_set_smpl_shift(uint8_t smpl_shift)
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{
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apu_dwsz_cfg_t tmp = apu->bf_dwsz_cfg_reg;
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tmp.smpl_shift_bits = smpl_shift;
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apu->bf_dwsz_cfg_reg = tmp;
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}
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/*get sampling shift*/
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uint8_t apu_get_smpl_shift(void)
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{
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apu_dwsz_cfg_t tmp = apu->bf_dwsz_cfg_reg;
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return tmp.smpl_shift_bits;
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}
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/*
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* APU unit sound channel enable control bits. Bit 'x' corresponds to enable bit for sound
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* channel 'x' (x = 0, 1, 2, . . ., 7). APU sound channels are related with I2S host RX channels.
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* APU sound channel 0/1 correspond to the left/right channel of I2S RX0; APU channel 2/3 correspond
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* to left/right channels of I2S RX1; and things like that. Software write '1' to enable a sound
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* channel and hardware automatically clear the bit after the sample buffers used for direction
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* searching is filled full.
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* 0x1: writing '1' to enable the corresponding APU sound channel.
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*/
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void apu_set_channel_enabled(uint8_t channel_bit)
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{
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apu_ch_cfg_t ch_cfg;
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ch_cfg.we_audio_gain = 0;
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ch_cfg.we_bf_target_dir = 0;
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ch_cfg.we_bf_sound_ch_en = 1;
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ch_cfg.bf_sound_ch_en = channel_bit;
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apu->bf_ch_cfg_reg = ch_cfg;
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}
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/*
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* APU unit sound channel enable control bits. Bit 'x' corresponds to enable bit for sound
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* channel 'x' (x = 0, 1, 2, . . ., 7). APU sound channels are related with I2S host RX channels.
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* APU sound channel 0/1 correspond to the left/right channel of I2S RX0; APU channel 2/3 correspond
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* to left/right channels of I2S RX1; and things like that. Software write '1' to enable a sound
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* channel and hardware automatically clear the bit after the sample buffers used for direction
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* searching is filled full.
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* 0x1: writing '1' to enable the corresponding APU sound channel.
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*/
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void apu_channel_enable(uint8_t channel_bit)
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{
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apu_ch_cfg_t ch_cfg = apu->bf_ch_cfg_reg;
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ch_cfg.we_audio_gain = 0;
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ch_cfg.we_bf_target_dir = 0;
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ch_cfg.we_data_src_mode = 0;
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ch_cfg.we_bf_sound_ch_en = 1;
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ch_cfg.bf_sound_ch_en = channel_bit;
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apu->bf_ch_cfg_reg = ch_cfg;
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}
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/*
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* audio data source configure parameter. This parameter controls where the audio data source comes from.
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* 0x0: audio data directly sourcing from apu internal buffer;
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* 0x1: audio data sourcing from FFT result buffer.
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*/
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void apu_set_src_mode(uint8_t src_mode)
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{
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apu_ch_cfg_t ch_cfg = apu->bf_ch_cfg_reg;
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ch_cfg.we_audio_gain = 0;
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ch_cfg.we_bf_target_dir = 0;
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ch_cfg.we_bf_sound_ch_en = 0;
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ch_cfg.we_data_src_mode = 1;
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ch_cfg.data_src_mode = src_mode;
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apu->bf_ch_cfg_reg = ch_cfg;
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}
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/*
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* I2S host beam-forming direction sample ibuffer read index configure register
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*/
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void apu_set_direction_delay(uint8_t dir_num, uint8_t *dir_bidx)
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{
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apu->bf_dir_bidx[dir_num][0] = (apu_dir_bidx_t){
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.dir_rd_idx0 = dir_bidx[0],
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.dir_rd_idx1 = dir_bidx[1],
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.dir_rd_idx2 = dir_bidx[2],
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.dir_rd_idx3 = dir_bidx[3]};
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apu->bf_dir_bidx[dir_num][1] = (apu_dir_bidx_t){
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.dir_rd_idx0 = dir_bidx[4],
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.dir_rd_idx1 = dir_bidx[5],
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.dir_rd_idx2 = dir_bidx[6],
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.dir_rd_idx3 = dir_bidx[7]};
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}
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/*
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* radius mic_num_a_circle: the num of mic per circle; center: 0: no center mic, 1:have center mic
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*/
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void apu_set_delay(float radius, uint8_t mic_num_a_circle, uint8_t center)
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{
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uint8_t offsets[16][8];
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int i, j;
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float seta[8], delay[8], hudu_jiao;
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float cm_tick = (float)SOUND_SPEED * 100 / I2S_FS; /*distance per tick (cm)*/
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float min;
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for(i = 0; i < mic_num_a_circle; ++i)
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{
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seta[i] = 360 * i / mic_num_a_circle;
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hudu_jiao = 2 * M_PI * seta[i] / 360;
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delay[i] = radius * (1 - cos(hudu_jiao)) / cm_tick;
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}
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if(center)
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delay[mic_num_a_circle] = radius / cm_tick;
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for(i = 0; i < mic_num_a_circle + center; ++i)
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{
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offsets[0][i] = (int)(delay[i] + 0.5);
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}
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for(; i < 8; i++)
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offsets[0][i] = 0;
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for(j = 1; j < DIRECTION_RES; ++j)
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{
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for(i = 0; i < mic_num_a_circle; ++i)
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{
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seta[i] -= 360 / DIRECTION_RES;
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hudu_jiao = 2 * M_PI * seta[i] / 360;
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delay[i] = radius * (1 - cos(hudu_jiao)) / cm_tick;
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}
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if(center)
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delay[mic_num_a_circle] = radius / cm_tick;
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min = 2 * radius;
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for(i = 0; i < mic_num_a_circle; ++i)
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{
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if(delay[i] < min)
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min = delay[i];
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}
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if(min)
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{
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for(i = 0; i < mic_num_a_circle + center; ++i)
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{
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delay[i] = delay[i] - min;
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}
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}
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for(i = 0; i < mic_num_a_circle + center; ++i)
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{
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offsets[j][i] = (int)(delay[i] + 0.5);
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}
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for(; i < 8; i++)
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offsets[0][i] = 0;
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}
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for(size_t i = 0; i < DIRECTION_RES; i++)
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{
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apu_set_direction_delay(i, offsets[i]);
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}
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}
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/*
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Sound direction searching enable bit. Software writes '1' to start sound direction searching function.
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When all the sound sample buffers are filled full, this bit is cleared by hardware (this sample buffers
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are used for direction detect only).
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0x1: enable direction searching.
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*/
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void apu_dir_enable(void)
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{
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apu_ctl_t bf_en_tmp = apu->bf_ctl_reg;
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bf_en_tmp.we_bf_dir_search_en = 1;
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bf_en_tmp.bf_dir_search_en = 1;
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apu->bf_ctl_reg = bf_en_tmp;
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}
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void apu_dir_reset(void)
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{
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apu_ctl_t bf_en_tmp = apu->bf_ctl_reg;
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bf_en_tmp.we_search_path_rst = 1;
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bf_en_tmp.search_path_reset = 1;
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apu->bf_ctl_reg = bf_en_tmp;
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}
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/*
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Valid voice sample stream generation enable bit. After sound direction searching is done, software can
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configure this bit to generate a stream of voice samples for voice recognition.
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0x1: enable output of voice sample stream.
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0x0: stop the voice samlpe stream output.
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*/
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void apu_voc_enable(uint8_t enable_flag)
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{
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apu_ctl_t bf_en_tmp = apu->bf_ctl_reg;
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bf_en_tmp.we_bf_stream_gen = 1;
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bf_en_tmp.bf_stream_gen_en = enable_flag;
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apu->bf_ctl_reg = bf_en_tmp;
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}
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void apu_voc_reset(void)
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{
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apu_ctl_t bf_en_tmp = apu->bf_ctl_reg;
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bf_en_tmp.we_voice_gen_path_rst = 1;
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bf_en_tmp.voice_gen_path_reset = 1;
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apu->bf_ctl_reg = bf_en_tmp;
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}
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/*
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Target direction select for valid voice output. When the source voice direaction searching
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is done, software can use this field to select one from 16 sound directions for the following
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voice recognition
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0x0: select sound direction 0; 0x1: select sound direction 1;
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. . . . . .
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0xF: select sound direction 15.
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*/
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void apu_voc_set_direction(en_bf_dir_t direction)
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{
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apu_ch_cfg_t ch_cfg = apu->bf_ch_cfg_reg;
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ch_cfg.we_bf_sound_ch_en = 0;
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ch_cfg.we_audio_gain = 0;
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ch_cfg.we_data_src_mode = 0;
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ch_cfg.we_bf_target_dir = 1;
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ch_cfg.bf_target_dir = direction;
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apu->bf_ch_cfg_reg = ch_cfg;
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apu_ctl_t bf_en_tmp = apu->bf_ctl_reg;
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bf_en_tmp.we_update_voice_dir = 1;
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bf_en_tmp.update_voice_dir = 1;
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apu->bf_ctl_reg = bf_en_tmp;
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}
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/*
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*I2S host beam-forming Filter FIR16 Coefficient Register
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*/
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void apu_dir_set_prev_fir(uint16_t *fir_coef)
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{
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uint8_t i = 0;
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for(i = 0; i < 9; i++)
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{
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apu->bf_pre_fir0_coef[i] =
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(apu_fir_coef_t){
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.fir_tap0 = fir_coef[i * 2],
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.fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]};
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}
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}
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void apu_dir_set_post_fir(uint16_t *fir_coef)
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{
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uint8_t i = 0;
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for(i = 0; i < 9; i++)
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{
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apu->bf_post_fir0_coef[i] =
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(apu_fir_coef_t){
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.fir_tap0 = fir_coef[i * 2],
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.fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]};
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}
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}
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void apu_voc_set_prev_fir(uint16_t *fir_coef)
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{
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uint8_t i = 0;
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for(i = 0; i < 9; i++)
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{
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apu->bf_pre_fir1_coef[i] =
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(apu_fir_coef_t){
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.fir_tap0 = fir_coef[i * 2],
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.fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]};
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}
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}
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void apu_voc_set_post_fir(uint16_t *fir_coef)
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{
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uint8_t i = 0;
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for(i = 0; i < 9; i++)
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{
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apu->bf_post_fir1_coef[i] =
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(apu_fir_coef_t){
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.fir_tap0 = fir_coef[i * 2],
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.fir_tap1 = i == 8 ? 0 : fir_coef[i * 2 + 1]};
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}
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}
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void apu_set_fft_shift_factor(uint8_t enable_flag, uint16_t shift_factor)
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{
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apu->bf_fft_cfg_reg =
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(apu_fft_cfg_t){
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.fft_enable = enable_flag,
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.fft_shift_factor = shift_factor};
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apu_ch_cfg_t ch_cfg = apu->bf_ch_cfg_reg;
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ch_cfg.we_data_src_mode = 1;
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ch_cfg.data_src_mode = enable_flag;
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apu->bf_ch_cfg_reg = ch_cfg;
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}
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void apu_dir_set_down_size(uint8_t dir_dwn_size)
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{
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apu_dwsz_cfg_t tmp = apu->bf_dwsz_cfg_reg;
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tmp.dir_dwn_siz_rate = dir_dwn_size;
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apu->bf_dwsz_cfg_reg = tmp;
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}
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void apu_dir_set_interrupt_mask(uint8_t dir_int_mask)
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{
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apu_int_mask_t tmp = apu->bf_int_mask_reg;
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tmp.dir_data_rdy_msk = dir_int_mask;
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apu->bf_int_mask_reg = tmp;
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}
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void apu_voc_set_down_size(uint8_t voc_dwn_size)
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{
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apu_dwsz_cfg_t tmp = apu->bf_dwsz_cfg_reg;
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tmp.voc_dwn_siz_rate = voc_dwn_size;
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apu->bf_dwsz_cfg_reg = tmp;
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}
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void apu_voc_set_interrupt_mask(uint8_t voc_int_mask)
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{
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apu_int_mask_t tmp = apu->bf_int_mask_reg;
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tmp.voc_buf_rdy_msk = voc_int_mask;
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apu->bf_int_mask_reg = tmp;
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}
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void apu_set_down_size(uint8_t dir_dwn_size, uint8_t voc_dwn_size)
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{
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apu_dwsz_cfg_t tmp = apu->bf_dwsz_cfg_reg;
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tmp.dir_dwn_siz_rate = dir_dwn_size;
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tmp.voc_dwn_siz_rate = voc_dwn_size;
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apu->bf_dwsz_cfg_reg = tmp;
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}
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void apu_set_interrupt_mask(uint8_t dir_int_mask, uint8_t voc_int_mask)
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{
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apu->bf_int_mask_reg =
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(apu_int_mask_t){
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.dir_data_rdy_msk = dir_int_mask,
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.voc_buf_rdy_msk = voc_int_mask};
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}
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void apu_dir_clear_int_state(void)
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{
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apu->bf_int_stat_reg =
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(apu_int_stat_t){
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.dir_search_data_rdy = 1};
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}
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void apu_voc_clear_int_state(void)
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{
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apu->bf_int_stat_reg =
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(apu_int_stat_t){
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.voc_buf_data_rdy = 1};
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}
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/* reset saturation_counter */
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void apu_voc_reset_saturation_counter(void)
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{
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apu->saturation_counter = 1 << 31;
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}
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/*get saturation counter*/
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/*heigh 16 bit is counter, low 16 bit is total.*/
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uint32_t apu_voc_get_saturation_counter(void)
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{
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return apu->saturation_counter;
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}
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/*set saturation limit*/
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void apu_voc_set_saturation_limit(uint16_t upper, uint16_t bottom)
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{
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apu->saturation_limits = (uint32_t)bottom << 16 | upper;
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}
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/*get saturation limit*/
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/*heigh 16 bit is counter, low 16 bit is total.*/
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uint32_t apu_voc_get_saturation_limit(void)
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{
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return apu->saturation_limits;
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}
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static void print_fir(const char *member_name, volatile apu_fir_coef_t *pfir)
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{
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printf(" for(int i = 0; i < 9; i++){\n");
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for(int i = 0; i < 9; i++)
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{
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apu_fir_coef_t fir = pfir[i];
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printf(" apu->%s[%d] = (apu_fir_coef_t){\n", member_name, i);
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printf(" .fir_tap0 = 0x%x,\n", fir.fir_tap0);
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printf(" .fir_tap1 = 0x%x\n", fir.fir_tap1);
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printf(" };\n");
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}
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printf(" }\n");
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}
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void apu_print_setting(void)
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{
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printf("void apu_setting(void) {\n");
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apu_ch_cfg_t bf_ch_cfg_reg = apu->bf_ch_cfg_reg;
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printf(" apu->bf_ch_cfg_reg = (apu_ch_cfg_t){\n");
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printf(" .we_audio_gain = 1, .we_bf_target_dir = 1, .we_bf_sound_ch_en = 1,\n");
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printf(" .audio_gain = 0x%x, .bf_target_dir = %d, .bf_sound_ch_en = %d, .data_src_mode = %d\n",
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bf_ch_cfg_reg.audio_gain, bf_ch_cfg_reg.bf_target_dir, bf_ch_cfg_reg.bf_sound_ch_en, bf_ch_cfg_reg.data_src_mode);
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printf(" };\n");
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|
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apu_ctl_t bf_ctl_reg = apu->bf_ctl_reg;
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|
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printf(" apu->bf_ctl_reg = (apu_ctl_t){\n");
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printf(" .we_bf_stream_gen = 1, .we_bf_dir_search_en = 1,\n");
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|
printf(" .bf_stream_gen_en = %d, .bf_dir_search_en = %d\n",
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bf_ctl_reg.bf_stream_gen_en, bf_ctl_reg.bf_dir_search_en);
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printf(" };\n");
|
|
|
|
printf(" for(int i = 0; i < 16; i++){\n");
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for(int i = 0; i < 16; i++)
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|
{
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apu_dir_bidx_t bidx0 = apu->bf_dir_bidx[i][0];
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apu_dir_bidx_t bidx1 = apu->bf_dir_bidx[i][1];
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|
|
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printf(" apu->bf_dir_bidx[%d][0] = (apu_dir_bidx_t){\n", i);
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printf(" .dir_rd_idx0 = 0x%x,\n", bidx0.dir_rd_idx0);
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|
printf(" .dir_rd_idx1 = 0x%x,\n", bidx0.dir_rd_idx1);
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|
printf(" .dir_rd_idx2 = 0x%x,\n", bidx0.dir_rd_idx2);
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|
printf(" .dir_rd_idx3 = 0x%x\n", bidx0.dir_rd_idx3);
|
|
printf(" };\n");
|
|
printf(" apu->bf_dir_bidx[%d][1] = (apu_dir_bidx_t){\n", i);
|
|
printf(" .dir_rd_idx0 = 0x%x,\n", bidx1.dir_rd_idx0);
|
|
printf(" .dir_rd_idx1 = 0x%x,\n", bidx1.dir_rd_idx1);
|
|
printf(" .dir_rd_idx2 = 0x%x,\n", bidx1.dir_rd_idx2);
|
|
printf(" .dir_rd_idx3 = 0x%x\n", bidx1.dir_rd_idx3);
|
|
printf(" };\n");
|
|
}
|
|
printf(" }\n");
|
|
|
|
print_fir("bf_pre_fir0_coef", apu->bf_pre_fir0_coef);
|
|
print_fir("bf_post_fir0_coef", apu->bf_post_fir0_coef);
|
|
print_fir("bf_pre_fir1_coef", apu->bf_pre_fir1_coef);
|
|
print_fir("bf_post_fir1_coef", apu->bf_post_fir1_coef);
|
|
|
|
apu_dwsz_cfg_t bf_dwsz_cfg_reg = apu->bf_dwsz_cfg_reg;
|
|
|
|
printf(" apu->bf_dwsz_cfg_reg = (apu_dwsz_cfg_t){\n");
|
|
printf(" .dir_dwn_siz_rate = %d, .voc_dwn_siz_rate = %d\n",
|
|
bf_dwsz_cfg_reg.dir_dwn_siz_rate, bf_dwsz_cfg_reg.voc_dwn_siz_rate);
|
|
printf(" };\n");
|
|
|
|
apu_fft_cfg_t bf_fft_cfg_reg = apu->bf_fft_cfg_reg;
|
|
|
|
printf(" apu->bf_fft_cfg_reg = (apu_fft_cfg_t){\n");
|
|
printf(" .fft_enable = %d, .fft_shift_factor = 0x%x\n",
|
|
bf_fft_cfg_reg.fft_enable, bf_fft_cfg_reg.fft_shift_factor);
|
|
printf(" };\n");
|
|
|
|
apu_int_mask_t bf_int_mask_reg = apu->bf_int_mask_reg;
|
|
|
|
printf(" apu->bf_int_mask_reg = (apu_int_mask_t){\n");
|
|
printf(" .dir_data_rdy_msk = %d, .voc_buf_rdy_msk = %d\n",
|
|
bf_int_mask_reg.dir_data_rdy_msk, bf_int_mask_reg.voc_buf_rdy_msk);
|
|
printf(" };\n");
|
|
|
|
printf("}\n");
|
|
}
|