802 lines
25 KiB
C
802 lines
25 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include <stddef.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "dmac.h"
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#include "fpioa.h"
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#include "plic.h"
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#include "stdlib.h"
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#include "sysctl.h"
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#include "utils.h"
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volatile dmac_t *const dmac = (dmac_t *)DMAC_BASE_ADDR;
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typedef struct _dmac_context
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{
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dmac_channel_number_t dmac_channel;
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plic_irq_callback_t callback;
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void *ctx;
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} dmac_context_t;
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dmac_context_t dmac_context[6];
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static int is_memory(uintptr_t address)
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{
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enum
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{
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mem_len = 6 * 1024 * 1024,
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mem_no_cache_len = 8 * 1024 * 1024,
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};
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return ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) || ((address >= 0x40000000) && (address < 0x40000000 + mem_no_cache_len)) || (address == 0x50450040);
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}
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uint64_t dmac_read_id(void)
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{
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return dmac->id;
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}
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uint64_t dmac_read_version(void)
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{
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return dmac->compver;
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}
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uint64_t dmac_read_channel_id(dmac_channel_number_t channel_num)
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{
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return dmac->channel[channel_num].axi_id;
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}
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static void dmac_enable(void)
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{
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dmac_cfg_u_t dmac_cfg;
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dmac_cfg.data = readq(&dmac->cfg);
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dmac_cfg.cfg.dmac_en = 1;
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dmac_cfg.cfg.int_en = 1;
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writeq(dmac_cfg.data, &dmac->cfg);
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}
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void dmac_disable(void)
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{
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dmac_cfg_u_t dmac_cfg;
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dmac_cfg.data = readq(&dmac->cfg);
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dmac_cfg.cfg.dmac_en = 0;
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dmac_cfg.cfg.int_en = 0;
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writeq(dmac_cfg.data, &dmac->cfg);
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}
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void src_transaction_complete_int_enable(dmac_channel_number_t channel_num)
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{
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dmac_ch_intstatus_enable_u_t ch_intstat;
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ch_intstat.data = readq(&dmac->channel[channel_num].intstatus_en);
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ch_intstat.ch_intstatus_enable.enable_src_transcomp_intstat = 1;
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writeq(ch_intstat.data, &dmac->channel[channel_num].intstatus_en);
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}
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void dmac_channel_enable(dmac_channel_number_t channel_num)
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{
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dmac_chen_u_t chen;
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chen.data = readq(&dmac->chen);
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switch(channel_num)
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{
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case DMAC_CHANNEL0:
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chen.dmac_chen.ch1_en = 1;
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chen.dmac_chen.ch1_en_we = 1;
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break;
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case DMAC_CHANNEL1:
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chen.dmac_chen.ch2_en = 1;
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chen.dmac_chen.ch2_en_we = 1;
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break;
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case DMAC_CHANNEL2:
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chen.dmac_chen.ch3_en = 1;
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chen.dmac_chen.ch3_en_we = 1;
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break;
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case DMAC_CHANNEL3:
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chen.dmac_chen.ch4_en = 1;
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chen.dmac_chen.ch4_en_we = 1;
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break;
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case DMAC_CHANNEL4:
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chen.dmac_chen.ch5_en = 1;
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chen.dmac_chen.ch5_en_we = 1;
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break;
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case DMAC_CHANNEL5:
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chen.dmac_chen.ch6_en = 1;
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chen.dmac_chen.ch6_en_we = 1;
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break;
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default:
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break;
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}
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writeq(chen.data, &dmac->chen);
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}
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void dmac_channel_disable(dmac_channel_number_t channel_num)
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{
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dmac_chen_u_t chen;
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chen.data = readq(&dmac->chen);
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switch(channel_num)
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{
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case DMAC_CHANNEL0:
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chen.dmac_chen.ch1_en = 0;
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chen.dmac_chen.ch1_en_we = 1;
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break;
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case DMAC_CHANNEL1:
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chen.dmac_chen.ch2_en = 0;
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chen.dmac_chen.ch2_en_we = 1;
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break;
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case DMAC_CHANNEL2:
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chen.dmac_chen.ch3_en = 0;
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chen.dmac_chen.ch3_en_we = 1;
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break;
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case DMAC_CHANNEL3:
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chen.dmac_chen.ch4_en = 0;
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chen.dmac_chen.ch4_en_we = 1;
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break;
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case DMAC_CHANNEL4:
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chen.dmac_chen.ch5_en = 0;
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chen.dmac_chen.ch5_en_we = 1;
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break;
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case DMAC_CHANNEL5:
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chen.dmac_chen.ch6_en = 0;
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chen.dmac_chen.ch6_en_we = 1;
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break;
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default:
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break;
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}
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writeq(chen.data, &dmac->chen);
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}
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int32_t dmac_check_channel_busy(dmac_channel_number_t channel_num)
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{
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int32_t ret = 0;
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dmac_chen_u_t chen_u;
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chen_u.data = readq(&dmac->chen);
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switch(channel_num)
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{
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case DMAC_CHANNEL0:
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if(chen_u.dmac_chen.ch1_en == 1)
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ret = 1;
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break;
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case DMAC_CHANNEL1:
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if(chen_u.dmac_chen.ch2_en == 1)
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ret = 1;
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break;
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case DMAC_CHANNEL2:
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if(chen_u.dmac_chen.ch3_en == 1)
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ret = 1;
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break;
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case DMAC_CHANNEL3:
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if(chen_u.dmac_chen.ch4_en == 1)
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ret = 1;
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break;
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case DMAC_CHANNEL4:
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if(chen_u.dmac_chen.ch5_en == 1)
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ret = 1;
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break;
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case DMAC_CHANNEL5:
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if(chen_u.dmac_chen.ch6_en == 1)
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ret = 1;
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break;
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default:
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break;
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}
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writeq(chen_u.data, &dmac->chen);
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return ret;
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}
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int32_t dmac_set_list_master_select(dmac_channel_number_t channel_num,
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dmac_src_dst_select_t sd_sel, dmac_master_number_t mst_num)
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{
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int32_t ret = 0;
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uint64_t tmp = 0;
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dmac_ch_ctl_u_t ctl;
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ctl.data = readq(&dmac->channel[channel_num].ctl);
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ret = dmac_check_channel_busy(channel_num);
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if(ret == 0)
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{
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if(sd_sel == DMAC_SRC || sd_sel == DMAC_SRC_DST)
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ctl.ch_ctl.sms = mst_num;
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if(sd_sel == DMAC_DST || sd_sel == DMAC_SRC_DST)
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ctl.ch_ctl.dms = mst_num;
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tmp |= *(uint64_t *)&dmac->channel[channel_num].ctl;
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writeq(ctl.data, &dmac->channel[channel_num].ctl);
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}
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return ret;
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}
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void dmac_enable_common_interrupt_status(void)
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{
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dmac_commonreg_intstatus_enable_u_t intstatus;
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intstatus.data = readq(&dmac->com_intstatus_en);
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intstatus.intstatus_enable.enable_slvif_dec_err_intstat = 1;
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intstatus.intstatus_enable.enable_slvif_wr2ro_err_intstat = 1;
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intstatus.intstatus_enable.enable_slvif_rd2wo_err_intstat = 1;
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intstatus.intstatus_enable.enable_slvif_wronhold_err_intstat = 1;
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intstatus.intstatus_enable.enable_slvif_undefinedreg_dec_err_intstat = 1;
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writeq(intstatus.data, &dmac->com_intstatus_en);
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}
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void dmac_enable_common_interrupt_signal(void)
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{
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dmac_commonreg_intsignal_enable_u_t intsignal;
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intsignal.data = readq(&dmac->com_intsignal_en);
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intsignal.intsignal_enable.enable_slvif_dec_err_intsignal = 1;
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intsignal.intsignal_enable.enable_slvif_wr2ro_err_intsignal = 1;
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intsignal.intsignal_enable.enable_slvif_rd2wo_err_intsignal = 1;
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intsignal.intsignal_enable.enable_slvif_wronhold_err_intsignal = 1;
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intsignal.intsignal_enable.enable_slvif_undefinedreg_dec_err_intsignal = 1;
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writeq(intsignal.data, &dmac->com_intsignal_en);
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}
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static void dmac_enable_channel_interrupt(dmac_channel_number_t channel_num)
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{
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writeq(0xffffffff, &dmac->channel[channel_num].intclear);
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writeq(0x2, &dmac->channel[channel_num].intstatus_en);
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}
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void dmac_disable_channel_interrupt(dmac_channel_number_t channel_num)
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{
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writeq(0, &dmac->channel[channel_num].intstatus_en);
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}
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static void dmac_chanel_interrupt_clear(dmac_channel_number_t channel_num)
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{
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writeq(0xffffffff, &dmac->channel[channel_num].intclear);
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}
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int dmac_set_channel_config(dmac_channel_number_t channel_num,
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dmac_channel_config_t *cfg_param)
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{
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dmac_ch_ctl_u_t ctl;
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dmac_ch_cfg_u_t cfg;
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dmac_ch_llp_u_t ch_llp;
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if(cfg_param->ctl_sms > DMAC_MASTER2)
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return -1;
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if(cfg_param->ctl_dms > DMAC_MASTER2)
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return -1;
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if(cfg_param->ctl_src_msize > DMAC_MSIZE_256)
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return -1;
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if(cfg_param->ctl_drc_msize > DMAC_MSIZE_256)
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return -1;
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/**
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* cfg register must configure before ts_block and
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* sar dar register
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*/
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cfg.data = readq(&dmac->channel[channel_num].cfg);
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cfg.ch_cfg.hs_sel_src = cfg_param->cfg_hs_sel_src;
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cfg.ch_cfg.hs_sel_dst = cfg_param->cfg_hs_sel_dst;
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cfg.ch_cfg.src_hwhs_pol = cfg_param->cfg_src_hs_pol;
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cfg.ch_cfg.dst_hwhs_pol = cfg_param->cfg_dst_hs_pol;
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cfg.ch_cfg.src_per = cfg_param->cfg_src_per;
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cfg.ch_cfg.dst_per = cfg_param->cfg_dst_per;
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cfg.ch_cfg.ch_prior = cfg_param->cfg_ch_prior;
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cfg.ch_cfg.tt_fc = cfg_param->ctl_tt_fc;
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cfg.ch_cfg.src_multblk_type = cfg_param->cfg_src_multblk_type;
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cfg.ch_cfg.dst_multblk_type = cfg_param->cfg_dst_multblk_type;
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writeq(cfg.data, &dmac->channel[channel_num].cfg);
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ctl.data = readq(&dmac->channel[channel_num].ctl);
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ctl.ch_ctl.sms = cfg_param->ctl_sms;
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ctl.ch_ctl.dms = cfg_param->ctl_dms;
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/* master select */
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ctl.ch_ctl.sinc = cfg_param->ctl_sinc;
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ctl.ch_ctl.dinc = cfg_param->ctl_dinc;
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/* address incrememt */
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ctl.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width;
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ctl.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width;
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/* transfer width */
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ctl.ch_ctl.src_msize = cfg_param->ctl_src_msize;
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ctl.ch_ctl.dst_msize = cfg_param->ctl_drc_msize;
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/* Burst transaction length */
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ctl.ch_ctl.ioc_blktfr = cfg_param->ctl_ioc_blktfr;
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/* interrupt on completion of block transfer */
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/* 0x1 enable BLOCK_TFR_DONE_IntStat field */
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writeq(cfg_param->ctl_block_ts, &dmac->channel[channel_num].block_ts);
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/* the number of (blcok_ts +1) data of width SRC_TR_WIDTF to be */
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/* transferred in a dma block transfer */
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dmac->channel[channel_num].sar = cfg_param->sar;
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dmac->channel[channel_num].dar = cfg_param->dar;
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ch_llp.data = readq(&dmac->channel[channel_num].llp);
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ch_llp.llp.loc = cfg_param->llp_loc;
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ch_llp.llp.lms = cfg_param->llp_lms;
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writeq(ch_llp.data, &dmac->channel[channel_num].llp);
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writeq(ctl.data, &dmac->channel[channel_num].ctl);
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readq(&dmac->channel[channel_num].swhssrc);
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return 0;
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}
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int dmac_set_channel_param(dmac_channel_number_t channel_num,
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const void *src, void *dest, dmac_address_increment_t src_inc, dmac_address_increment_t dest_inc,
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dmac_burst_trans_length_t dmac_burst_size,
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dmac_transfer_width_t dmac_trans_width,
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uint32_t blockSize)
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{
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dmac_ch_ctl_u_t ctl;
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dmac_ch_cfg_u_t cfg_u;
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int mem_type_src = is_memory((uintptr_t)src), mem_type_dest = is_memory((uintptr_t)dest);
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dmac_transfer_flow_t flow_control;
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if(mem_type_src == 0 && mem_type_dest == 0)
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{
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flow_control = DMAC_PRF2PRF_DMA;
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} else if(mem_type_src == 1 && mem_type_dest == 0)
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flow_control = DMAC_MEM2PRF_DMA;
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else if(mem_type_src == 0 && mem_type_dest == 1)
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flow_control = DMAC_PRF2MEM_DMA;
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else
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flow_control = DMAC_MEM2MEM_DMA;
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/**
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* cfg register must configure before ts_block and
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* sar dar register
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*/
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cfg_u.data = readq(&dmac->channel[channel_num].cfg);
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cfg_u.ch_cfg.tt_fc = flow_control;
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cfg_u.ch_cfg.hs_sel_src = mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
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cfg_u.ch_cfg.hs_sel_dst = mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
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cfg_u.ch_cfg.src_per = channel_num;
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cfg_u.ch_cfg.dst_per = channel_num;
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cfg_u.ch_cfg.src_multblk_type = 0;
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cfg_u.ch_cfg.dst_multblk_type = 0;
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writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
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dmac->channel[channel_num].sar = (uint64_t)src;
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dmac->channel[channel_num].dar = (uint64_t)dest;
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ctl.data = readq(&dmac->channel[channel_num].ctl);
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ctl.ch_ctl.sms = DMAC_MASTER1;
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ctl.ch_ctl.dms = DMAC_MASTER2;
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/* master select */
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ctl.ch_ctl.sinc = src_inc;
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ctl.ch_ctl.dinc = dest_inc;
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/* address incrememt */
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ctl.ch_ctl.src_tr_width = dmac_trans_width;
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ctl.ch_ctl.dst_tr_width = dmac_trans_width;
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/* transfer width */
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ctl.ch_ctl.src_msize = dmac_burst_size;
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ctl.ch_ctl.dst_msize = dmac_burst_size;
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writeq(ctl.data, &dmac->channel[channel_num].ctl);
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writeq(blockSize - 1, &dmac->channel[channel_num].block_ts);
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/*the number of (blcok_ts +1) data of width SRC_TR_WIDTF to be */
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/* transferred in a dma block transfer */
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return 0;
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}
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int dmac_get_channel_config(dmac_channel_number_t channel_num,
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dmac_channel_config_t *cfg_param)
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{
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dmac_ch_ctl_u_t ctl;
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dmac_ch_cfg_u_t cfg;
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dmac_ch_llp_u_t ch_llp;
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if(cfg_param == 0)
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return -1;
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if(channel_num < DMAC_CHANNEL0 ||
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channel_num > DMAC_CHANNEL3)
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return -1;
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ctl.data = readq(&dmac->channel[channel_num].ctl);
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cfg_param->ctl_sms = ctl.ch_ctl.sms;
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cfg_param->ctl_dms = ctl.ch_ctl.dms;
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cfg_param->ctl_sinc = ctl.ch_ctl.sinc;
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cfg_param->ctl_dinc = ctl.ch_ctl.dinc;
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cfg_param->ctl_src_tr_width = ctl.ch_ctl.src_tr_width;
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cfg_param->ctl_dst_tr_width = ctl.ch_ctl.dst_tr_width;
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cfg_param->ctl_src_msize = ctl.ch_ctl.src_msize;
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cfg_param->ctl_drc_msize = ctl.ch_ctl.dst_msize;
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cfg_param->ctl_ioc_blktfr = ctl.ch_ctl.ioc_blktfr;
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cfg.data = readq(&dmac->channel[channel_num].cfg);
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cfg_param->cfg_hs_sel_src = cfg.ch_cfg.hs_sel_src;
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cfg_param->cfg_hs_sel_dst = cfg.ch_cfg.hs_sel_dst;
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cfg_param->cfg_src_hs_pol = cfg.ch_cfg.src_hwhs_pol;
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cfg_param->cfg_dst_hs_pol = cfg.ch_cfg.dst_hwhs_pol;
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cfg_param->cfg_src_per = cfg.ch_cfg.src_per;
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cfg_param->cfg_dst_per = cfg.ch_cfg.dst_per;
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cfg_param->cfg_ch_prior = cfg.ch_cfg.ch_prior;
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cfg_param->cfg_src_multblk_type = cfg.ch_cfg.src_multblk_type;
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cfg_param->cfg_dst_multblk_type = cfg.ch_cfg.dst_multblk_type;
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cfg_param->sar = dmac->channel[channel_num].sar;
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cfg_param->dar = dmac->channel[channel_num].dar;
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ch_llp.data = readq(&dmac->channel[channel_num].llp);
|
|
cfg_param->llp_loc = ch_llp.llp.loc;
|
|
cfg_param->llp_lms = ch_llp.llp.lms;
|
|
|
|
cfg_param->ctl_block_ts = readq(&dmac->channel[channel_num].block_ts);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void dmac_set_address(dmac_channel_number_t channel_num, uint64_t src_addr,
|
|
uint64_t dst_addr)
|
|
{
|
|
writeq(src_addr, &dmac->channel[channel_num].sar);
|
|
writeq(dst_addr, &dmac->channel[channel_num].dar);
|
|
}
|
|
|
|
void dmac_set_block_ts(dmac_channel_number_t channel_num,
|
|
uint32_t block_size)
|
|
{
|
|
uint32_t block_ts;
|
|
|
|
block_ts = block_size & 0x3fffff;
|
|
writeq(block_ts, &dmac->channel[channel_num].block_ts);
|
|
}
|
|
|
|
void dmac_source_control(dmac_channel_number_t channel_num,
|
|
dmac_master_number_t master_select,
|
|
dmac_address_increment_t address_mode,
|
|
dmac_transfer_width_t tr_width,
|
|
dmac_burst_trans_length_t burst_length)
|
|
{
|
|
dmac_ch_ctl_u_t ctl_u;
|
|
|
|
ctl_u.data = readq(&dmac->channel[channel_num].ctl);
|
|
ctl_u.ch_ctl.sms = master_select;
|
|
ctl_u.ch_ctl.sinc = address_mode;
|
|
ctl_u.ch_ctl.src_tr_width = tr_width;
|
|
ctl_u.ch_ctl.src_msize = burst_length;
|
|
|
|
writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
|
|
}
|
|
|
|
void dmac_master_control(dmac_channel_number_t channel_num,
|
|
dmac_master_number_t master_select,
|
|
dmac_address_increment_t address_mode,
|
|
dmac_transfer_width_t tr_width,
|
|
dmac_burst_trans_length_t burst_length)
|
|
{
|
|
dmac_ch_ctl_u_t ctl_u;
|
|
|
|
ctl_u.data = readq(&dmac->channel[channel_num].ctl);
|
|
ctl_u.ch_ctl.dms = master_select;
|
|
ctl_u.ch_ctl.dinc = address_mode;
|
|
ctl_u.ch_ctl.dst_tr_width = tr_width;
|
|
ctl_u.ch_ctl.dst_msize = burst_length;
|
|
|
|
writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
|
|
}
|
|
|
|
void dmac_set_source_transfer_control(dmac_channel_number_t channel_num,
|
|
dmac_multiblk_transfer_type_t transfer_type,
|
|
dmac_sw_hw_hs_select_t handshak_select)
|
|
{
|
|
dmac_ch_cfg_u_t cfg_u;
|
|
|
|
cfg_u.data = readq(&dmac->channel[channel_num].cfg);
|
|
cfg_u.ch_cfg.src_multblk_type = transfer_type;
|
|
cfg_u.ch_cfg.hs_sel_src = handshak_select;
|
|
|
|
writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
|
|
}
|
|
|
|
void dmac_set_destination_transfer_control(dmac_channel_number_t channel_num,
|
|
dmac_multiblk_transfer_type_t transfer_type,
|
|
dmac_sw_hw_hs_select_t handshak_select)
|
|
{
|
|
dmac_ch_cfg_u_t cfg_u;
|
|
|
|
cfg_u.data = readq(&dmac->channel[channel_num].cfg);
|
|
cfg_u.ch_cfg.dst_multblk_type = transfer_type;
|
|
cfg_u.ch_cfg.hs_sel_dst = handshak_select;
|
|
|
|
writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
|
|
}
|
|
|
|
void dmac_set_flow_control(dmac_channel_number_t channel_num,
|
|
dmac_transfer_flow_t flow_control)
|
|
{
|
|
dmac_ch_cfg_u_t cfg_u;
|
|
|
|
cfg_u.data = readq(&dmac->channel[channel_num].cfg);
|
|
cfg_u.ch_cfg.tt_fc = flow_control;
|
|
|
|
writeq(cfg_u.data, &dmac->channel[channel_num].cfg);
|
|
}
|
|
|
|
void dmac_set_linked_list_addr_point(dmac_channel_number_t channel_num,
|
|
uint64_t *addr)
|
|
{
|
|
dmac_ch_llp_u_t llp_u;
|
|
|
|
llp_u.data = readq(&dmac->channel[channel_num].llp);
|
|
/* Cast pointer to uint64_t */
|
|
llp_u.llp.loc = (uint64_t)addr;
|
|
writeq(llp_u.data, &dmac->channel[channel_num].llp);
|
|
}
|
|
|
|
void dmac_init(void)
|
|
{
|
|
uint64_t tmp;
|
|
dmac_commonreg_intclear_u_t intclear;
|
|
dmac_cfg_u_t dmac_cfg;
|
|
dmac_reset_u_t dmac_reset;
|
|
|
|
sysctl_clock_enable(SYSCTL_CLOCK_DMA);
|
|
|
|
dmac_reset.data = readq(&dmac->reset);
|
|
dmac_reset.reset.rst = 1;
|
|
writeq(dmac_reset.data, &dmac->reset);
|
|
while(dmac_reset.reset.rst)
|
|
dmac_reset.data = readq(&dmac->reset);
|
|
|
|
/*reset dmac */
|
|
|
|
intclear.data = readq(&dmac->com_intclear);
|
|
intclear.com_intclear.cear_slvif_dec_err_intstat = 1;
|
|
intclear.com_intclear.clear_slvif_wr2ro_err_intstat = 1;
|
|
intclear.com_intclear.clear_slvif_rd2wo_err_intstat = 1;
|
|
intclear.com_intclear.clear_slvif_wronhold_err_intstat = 1;
|
|
intclear.com_intclear.clear_slvif_undefinedreg_dec_err_intstat = 1;
|
|
writeq(intclear.data, &dmac->com_intclear);
|
|
/* clear common register interrupt */
|
|
|
|
dmac_cfg.data = readq(&dmac->cfg);
|
|
dmac_cfg.cfg.dmac_en = 0;
|
|
dmac_cfg.cfg.int_en = 0;
|
|
writeq(dmac_cfg.data, &dmac->cfg);
|
|
/* disable dmac and disable interrupt */
|
|
|
|
while(readq(&dmac->cfg))
|
|
;
|
|
tmp = readq(&dmac->chen);
|
|
tmp &= ~0xf;
|
|
writeq(tmp, &dmac->chen);
|
|
/* disable all channel before configure */
|
|
dmac_enable();
|
|
}
|
|
|
|
static void list_add(struct list_head_t *new, struct list_head_t *prev,
|
|
struct list_head_t *next)
|
|
{
|
|
next->prev = new;
|
|
new->next = next;
|
|
new->prev = prev;
|
|
prev->next = new;
|
|
}
|
|
|
|
void list_add_tail(struct list_head_t *new, struct list_head_t *head)
|
|
{
|
|
list_add(new, head->prev, head);
|
|
}
|
|
|
|
void INIT_LIST_HEAD(struct list_head_t *list)
|
|
{
|
|
list->next = list;
|
|
list->prev = list;
|
|
}
|
|
|
|
void dmac_link_list_item(dmac_channel_number_t channel_num,
|
|
uint8_t LLI_row_num, int8_t LLI_last_row,
|
|
dmac_lli_item_t *lli_item,
|
|
dmac_channel_config_t *cfg_param)
|
|
{
|
|
dmac_ch_ctl_u_t ctl;
|
|
dmac_ch_llp_u_t llp_u;
|
|
|
|
lli_item[LLI_row_num].sar = cfg_param->sar;
|
|
lli_item[LLI_row_num].dar = cfg_param->dar;
|
|
|
|
ctl.data = readq(&dmac->channel[channel_num].ctl);
|
|
ctl.ch_ctl.sms = cfg_param->ctl_sms;
|
|
ctl.ch_ctl.dms = cfg_param->ctl_dms;
|
|
ctl.ch_ctl.sinc = cfg_param->ctl_sinc;
|
|
ctl.ch_ctl.dinc = cfg_param->ctl_dinc;
|
|
ctl.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width;
|
|
ctl.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width;
|
|
ctl.ch_ctl.src_msize = cfg_param->ctl_src_msize;
|
|
ctl.ch_ctl.dst_msize = cfg_param->ctl_drc_msize;
|
|
ctl.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en;
|
|
ctl.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en;
|
|
|
|
if(LLI_last_row != LAST_ROW)
|
|
{
|
|
ctl.ch_ctl.shadowreg_or_lli_valid = 1;
|
|
ctl.ch_ctl.shadowreg_or_lli_last = 0;
|
|
} else
|
|
{
|
|
ctl.ch_ctl.shadowreg_or_lli_valid = 1;
|
|
ctl.ch_ctl.shadowreg_or_lli_last = 1;
|
|
}
|
|
|
|
lli_item[LLI_row_num].ctl = ctl.data;
|
|
|
|
lli_item[LLI_row_num].ch_block_ts = cfg_param->ctl_block_ts;
|
|
lli_item[LLI_row_num].sstat = 0;
|
|
lli_item[LLI_row_num].dstat = 0;
|
|
|
|
llp_u.data = readq(&dmac->channel[channel_num].llp);
|
|
|
|
if(LLI_last_row != LAST_ROW)
|
|
llp_u.llp.loc = ((uint64_t)&lli_item[LLI_row_num + 1]) >> 6;
|
|
else
|
|
llp_u.llp.loc = 0;
|
|
|
|
lli_item[LLI_row_num].llp = llp_u.data;
|
|
}
|
|
|
|
void dmac_update_shandow_register(dmac_channel_number_t channel_num,
|
|
int8_t last_block, dmac_channel_config_t *cfg_param)
|
|
{
|
|
dmac_ch_ctl_u_t ctl_u;
|
|
|
|
do
|
|
{
|
|
ctl_u.data = readq(&dmac->channel[channel_num].ctl);
|
|
} while(ctl_u.ch_ctl.shadowreg_or_lli_valid);
|
|
|
|
writeq(cfg_param->sar, &dmac->channel[channel_num].sar);
|
|
writeq(cfg_param->dar, &dmac->channel[channel_num].dar);
|
|
writeq(cfg_param->ctl_block_ts, &dmac->channel[channel_num].block_ts);
|
|
|
|
ctl_u.ch_ctl.sms = cfg_param->ctl_sms;
|
|
ctl_u.ch_ctl.dms = cfg_param->ctl_dms;
|
|
ctl_u.ch_ctl.sinc = cfg_param->ctl_sinc;
|
|
ctl_u.ch_ctl.dinc = cfg_param->ctl_dinc;
|
|
ctl_u.ch_ctl.src_tr_width = cfg_param->ctl_src_tr_width;
|
|
ctl_u.ch_ctl.dst_tr_width = cfg_param->ctl_dst_tr_width;
|
|
ctl_u.ch_ctl.src_msize = cfg_param->ctl_src_msize;
|
|
ctl_u.ch_ctl.dst_msize = cfg_param->ctl_drc_msize;
|
|
ctl_u.ch_ctl.src_stat_en = cfg_param->ctl_src_stat_en;
|
|
ctl_u.ch_ctl.dst_stat_en = cfg_param->ctl_dst_stat_en;
|
|
if(last_block != LAST_ROW)
|
|
{
|
|
ctl_u.ch_ctl.shadowreg_or_lli_valid = 1;
|
|
ctl_u.ch_ctl.shadowreg_or_lli_last = 0;
|
|
} else
|
|
{
|
|
ctl_u.ch_ctl.shadowreg_or_lli_valid = 1;
|
|
ctl_u.ch_ctl.shadowreg_or_lli_last = 1;
|
|
}
|
|
|
|
writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
|
|
writeq(0, &dmac->channel[channel_num].blk_tfr);
|
|
}
|
|
|
|
void dmac_set_shadow_invalid_flag(dmac_channel_number_t channel_num)
|
|
{
|
|
dmac_ch_ctl_u_t ctl_u;
|
|
|
|
ctl_u.data = readq(&dmac->channel[channel_num].ctl);
|
|
ctl_u.ch_ctl.shadowreg_or_lli_valid = 1;
|
|
ctl_u.ch_ctl.shadowreg_or_lli_last = 0;
|
|
writeq(ctl_u.data, &dmac->channel[channel_num].ctl);
|
|
}
|
|
|
|
void dmac_set_single_mode(dmac_channel_number_t channel_num,
|
|
const void *src, void *dest, dmac_address_increment_t src_inc,
|
|
dmac_address_increment_t dest_inc,
|
|
dmac_burst_trans_length_t dmac_burst_size,
|
|
dmac_transfer_width_t dmac_trans_width,
|
|
size_t block_size)
|
|
{
|
|
dmac_chanel_interrupt_clear(channel_num);
|
|
dmac_channel_disable(channel_num);
|
|
dmac_wait_idle(channel_num);
|
|
dmac_set_channel_param(channel_num, src, dest, src_inc, dest_inc,
|
|
dmac_burst_size, dmac_trans_width, block_size);
|
|
dmac_enable();
|
|
dmac_channel_enable(channel_num);
|
|
}
|
|
|
|
int dmac_is_done(dmac_channel_number_t channel_num)
|
|
{
|
|
if(readq(&dmac->channel[channel_num].intstatus) & 0x2)
|
|
return 1;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
void dmac_wait_done(dmac_channel_number_t channel_num)
|
|
{
|
|
dmac_wait_idle(channel_num);
|
|
}
|
|
|
|
int dmac_is_idle(dmac_channel_number_t channel_num)
|
|
{
|
|
dmac_chen_u_t chen;
|
|
chen.data = readq(&dmac->chen);
|
|
if((chen.data >> channel_num) & 0x1UL)
|
|
return 0;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
void dmac_wait_idle(dmac_channel_number_t channel_num)
|
|
{
|
|
while(!dmac_is_idle(channel_num))
|
|
;
|
|
dmac_chanel_interrupt_clear(channel_num); /* clear interrupt */
|
|
}
|
|
|
|
void dmac_set_src_dest_length(dmac_channel_number_t channel_num, const void *src, void *dest, size_t len)
|
|
{
|
|
if(src != NULL)
|
|
dmac->channel[channel_num].sar = (uint64_t)src;
|
|
if(dest != NULL)
|
|
dmac->channel[channel_num].dar = (uint64_t)dest;
|
|
if(len > 0)
|
|
dmac_set_block_ts(channel_num, len - 1);
|
|
dmac_channel_enable(channel_num);
|
|
}
|
|
|
|
static int dmac_irq_callback(void *ctx)
|
|
{
|
|
dmac_context_t *v_dmac_context = (dmac_context_t *)(ctx);
|
|
dmac_channel_number_t v_dmac_channel = v_dmac_context->dmac_channel;
|
|
dmac_chanel_interrupt_clear(v_dmac_channel);
|
|
if(v_dmac_context->callback != NULL)
|
|
v_dmac_context->callback(v_dmac_context->ctx);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void dmac_irq_register(dmac_channel_number_t channel_num, plic_irq_callback_t dmac_callback, void *ctx, uint32_t priority)
|
|
{
|
|
dmac_context[channel_num].dmac_channel = channel_num;
|
|
dmac_context[channel_num].callback = dmac_callback;
|
|
dmac_context[channel_num].ctx = ctx;
|
|
dmac_enable_channel_interrupt(channel_num);
|
|
plic_set_priority(IRQN_DMA0_INTERRUPT + channel_num, priority);
|
|
plic_irq_register(IRQN_DMA0_INTERRUPT + channel_num, dmac_irq_callback, &dmac_context[channel_num]);
|
|
plic_irq_enable(IRQN_DMA0_INTERRUPT + channel_num);
|
|
}
|
|
|
|
void __attribute__((weak, alias("dmac_irq_register"))) dmac_set_irq(dmac_channel_number_t channel_num, plic_irq_callback_t dmac_callback, void *ctx, uint32_t priority);
|
|
|
|
void dmac_irq_unregister(dmac_channel_number_t channel_num)
|
|
{
|
|
dmac_context[channel_num].callback = NULL;
|
|
dmac_context[channel_num].ctx = NULL;
|
|
dmac_disable_channel_interrupt(channel_num);
|
|
plic_irq_unregister(IRQN_DMA0_INTERRUPT + channel_num);
|
|
}
|
|
|
|
void __attribute__((weak, alias("dmac_irq_unregister"))) dmac_free_irq(dmac_channel_number_t channel_num);
|