270 lines
7.3 KiB
C
270 lines
7.3 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_DVP_H
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#define _DRIVER_DVP_H
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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/**
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* @brief DVP object
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*/
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typedef struct _dvp
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{
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uint32_t dvp_cfg;
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uint32_t r_addr;
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uint32_t g_addr;
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uint32_t b_addr;
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uint32_t cmos_cfg;
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uint32_t sccb_cfg;
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uint32_t sccb_ctl;
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uint32_t axi;
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uint32_t sts;
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uint32_t reverse;
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uint32_t rgb_addr;
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} __attribute__((packed, aligned(4))) dvp_t;
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/* DVP Config Register */
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#define DVP_CFG_START_INT_ENABLE 0x00000001U
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#define DVP_CFG_FINISH_INT_ENABLE 0x00000002U
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#define DVP_CFG_AI_OUTPUT_ENABLE 0x00000004U
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#define DVP_CFG_DISPLAY_OUTPUT_ENABLE 0x00000008U
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#define DVP_CFG_AUTO_ENABLE 0x00000010U
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#define DVP_CFG_BURST_SIZE_4BEATS 0x00000100U
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#define DVP_CFG_FORMAT_MASK 0x00000600U
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#define DVP_CFG_RGB_FORMAT 0x00000000U
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#define DVP_CFG_YUV_FORMAT 0x00000200U
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#define DVP_CFG_Y_FORMAT 0x00000600U
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#define DVP_CFG_HREF_BURST_NUM_MASK 0x000FF000U
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#define DVP_CFG_HREF_BURST_NUM(x) ((x) << 12)
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#define DVP_CFG_LINE_NUM_MASK 0x3FF00000U
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#define DVP_CFG_LINE_NUM(x) ((x) << 20)
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/* DVP CMOS Config Register */
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#define DVP_CMOS_CLK_DIV_MASK 0x000000FFU
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#define DVP_CMOS_CLK_DIV(x) ((x) << 0)
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#define DVP_CMOS_CLK_ENABLE 0x00000100U
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#define DVP_CMOS_RESET 0x00010000U
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#define DVP_CMOS_POWER_DOWN 0x01000000U
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/* DVP SCCB Config Register */
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#define DVP_SCCB_BYTE_NUM_MASK 0x00000003U
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#define DVP_SCCB_BYTE_NUM_2 0x00000001U
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#define DVP_SCCB_BYTE_NUM_3 0x00000002U
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#define DVP_SCCB_BYTE_NUM_4 0x00000003U
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#define DVP_SCCB_SCL_LCNT_MASK 0x0000FF00U
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#define DVP_SCCB_SCL_LCNT(x) ((x) << 8)
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#define DVP_SCCB_SCL_HCNT_MASK 0x00FF0000U
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#define DVP_SCCB_SCL_HCNT(x) ((x) << 16)
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#define DVP_SCCB_RDATA_BYTE(x) ((x) >> 24)
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/* DVP SCCB Control Register */
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#define DVP_SCCB_WRITE_DATA_ENABLE 0x00000001U
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#define DVP_SCCB_DEVICE_ADDRESS(x) ((x) << 0)
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#define DVP_SCCB_REG_ADDRESS(x) ((x) << 8)
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#define DVP_SCCB_WDATA_BYTE0(x) ((x) << 16)
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#define DVP_SCCB_WDATA_BYTE1(x) ((x) << 24)
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/* DVP AXI Register */
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#define DVP_AXI_GM_MLEN_MASK 0x000000FFU
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#define DVP_AXI_GM_MLEN_1BYTE 0x00000000U
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#define DVP_AXI_GM_MLEN_4BYTE 0x00000003U
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/* DVP STS Register */
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#define DVP_STS_FRAME_START 0x00000001U
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#define DVP_STS_FRAME_START_WE 0x00000002U
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#define DVP_STS_FRAME_FINISH 0x00000100U
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#define DVP_STS_FRAME_FINISH_WE 0x00000200U
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#define DVP_STS_DVP_EN 0x00010000U
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#define DVP_STS_DVP_EN_WE 0x00020000U
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#define DVP_STS_SCCB_EN 0x01000000U
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#define DVP_STS_SCCB_EN_WE 0x02000000U
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/* clang-format on */
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typedef enum _dvp_output_mode
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{
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DVP_OUTPUT_AI,
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DVP_OUTPUT_DISPLAY,
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} dvp_output_mode_t;
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/**
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* @brief DVP object instance
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*/
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extern volatile dvp_t *const dvp;
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/**
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* @brief Initialize DVP
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*/
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void dvp_init(uint8_t reg_len);
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/**
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* @brief Set image format
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*
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* @param[in] format The image format
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*/
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void dvp_set_image_format(uint32_t format);
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/**
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* @brief Set image size
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*
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* @param[in] width The width of image
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* @param[in] height The height of image
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*/
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void dvp_set_image_size(uint32_t width, uint32_t height);
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/**
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* @brief Set the address of RGB for AI
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*
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* @param[in] r_addr The R address of RGB
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* @param[in] g_addr The G address of RGB
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* @param[in] b_addr The B address of RGB
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*/
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void dvp_set_ai_addr(uint32_t r_addr, uint32_t g_addr, uint32_t b_addr);
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/**
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* @brief Set the address of RGB for display
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*
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* @param[in] r_addr The R address of RGB
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* @param[in] g_addr The G address of RGB
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* @param[in] b_addr The B address of RGB
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*/
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void dvp_set_display_addr(uint32_t addr);
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/**
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* @brief The frame start transfer
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*/
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void dvp_start_frame(void);
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/**
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* @brief The DVP convert start
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*/
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void dvp_start_convert(void);
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/**
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* @brief The DVP convert finish
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*/
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void dvp_finish_convert(void);
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/**
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* @brief Get the image data
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*
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* @note The image data stored in the address of RGB
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*/
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void dvp_get_image(void);
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/**
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* @brief Use SCCB write register
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*
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* @param[in] dev_addr The device address
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* @param[in] reg_addr The register address
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* @param[in] reg_data The register data
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*/
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void dvp_sccb_send_data(uint8_t dev_addr, uint16_t reg_addr, uint8_t reg_data);
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/**
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* @brief Use SCCB read register
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*
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* @param[in] dev_addr The device address
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* @param[in] reg_addr The register address
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*
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* @return The register value
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*/
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uint8_t dvp_sccb_receive_data(uint8_t dev_addr, uint16_t reg_addr);
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/**
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* @brief Enable dvp burst
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*/
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void dvp_enable_burst(void);
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/**
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* @brief Disable dvp burst
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*/
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void dvp_disable_burst(void);
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/**
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* @brief Enable or disable dvp interrupt
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*
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* @param[in] interrupt Dvp interrupt
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* @param[in] status 0:disable 1:enable
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*
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*/
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void dvp_config_interrupt(uint32_t interrupt, uint8_t enable);
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/**
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* @brief Get dvp interrupt status
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*
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* @param[in] interrupt Dvp interrupt
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*
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*
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* @return Interrupt status
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* - 0 false
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* - 1 true
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*/
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int dvp_get_interrupt(uint32_t interrupt);
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/**
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* @brief Clear dvp interrupt status
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*
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* @param[in] interrupt Dvp interrupt
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*
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*/
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void dvp_clear_interrupt(uint32_t interrupt);
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/**
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* @brief Enable dvp auto mode
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*/
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void dvp_enable_auto(void);
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/**
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* @brief Disable dvp auto mode
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*/
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void dvp_disable_auto(void);
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/**
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* @brief Dvp ouput data enable or not
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*
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* @param[in] index 0:AI, 1:display
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* @param[in] enable 0:disable, 1:enable
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*
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*/
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void dvp_set_output_enable(dvp_output_mode_t index, int enable);
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/**
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* @brief Set sccb clock rate
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*
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* @param[in] clk_rate Sccb clock rate
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*
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* @return The real sccb clock rate
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*/
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uint32_t dvp_sccb_set_clk_rate(uint32_t clk_rate);
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/**
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* @brief Set xclk rate
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*
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* @param[in] clk_rate xclk rate
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*
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* @return The real xclk rate
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*/
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uint32_t dvp_set_xclk_rate(uint32_t xclk_rate);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_DVP_H */
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