783 lines
23 KiB
C
783 lines
23 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_I2S_H
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#define _DRIVER_I2S_H
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#include <stddef.h>
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#include <stdint.h>
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#include "bsp.h"
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#include "dmac.h"
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#include "io.h"
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#include "platform.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define I2S0_IN_D0 90
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#define I2S0_SCLK 88
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#define I2S0_WS 89
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typedef enum _i2s_device_number
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{
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I2S_DEVICE_0 = 0,
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I2S_DEVICE_1 = 1,
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I2S_DEVICE_2 = 2,
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I2S_DEVICE_MAX
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} i2s_device_number_t;
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typedef enum _i2s_channel_num
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{
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I2S_CHANNEL_0 = 0,
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I2S_CHANNEL_1 = 1,
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I2S_CHANNEL_2 = 2,
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I2S_CHANNEL_3 = 3
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} i2s_channel_num_t;
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typedef enum _i2s_transmit
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{
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I2S_TRANSMITTER = 0,
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I2S_RECEIVER = 1
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} i2s_transmit_t;
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typedef enum _i2s_work_mode
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{
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STANDARD_MODE = 1,
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RIGHT_JUSTIFYING_MODE = 2,
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LEFT_JUSTIFYING_MODE = 4
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} i2s_work_mode_t;
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typedef enum _sclk_gating_cycles
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{
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/* Clock gating is diable */
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NO_CLOCK_GATING = 0x0,
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/* Gating after 12 sclk cycles */
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CLOCK_CYCLES_12 = 0x1,
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/* Gating after 16 sclk cycles */
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CLOCK_CYCLES_16 = 0x2,
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/* Gating after 20 sclk cycles */
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CLOCK_CYCLES_20 = 0x3,
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/* Gating after 24 sclk cycles */
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CLOCK_CYCLES_24 = 0x4
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} i2s_sclk_gating_cycles_t;
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typedef enum _word_select_cycles
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{
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/* 16 sclk cycles */
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SCLK_CYCLES_16 = 0x0,
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/* 24 sclk cycles */
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SCLK_CYCLES_24 = 0x1,
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/* 32 sclk cycles */
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SCLK_CYCLES_32 = 0x2
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} i2s_word_select_cycles_t;
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typedef enum _word_length
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{
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/* Ignore the word length */
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IGNORE_WORD_LENGTH = 0x0,
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/* 12-bit data resolution of the receiver */
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RESOLUTION_12_BIT = 0x1,
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/* 16-bit data resolution of the receiver */
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RESOLUTION_16_BIT = 0x2,
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/* 20-bit data resolution of the receiver */
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RESOLUTION_20_BIT = 0x3,
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/* 24-bit data resolution of the receiver */
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RESOLUTION_24_BIT = 0x4,
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/* 32-bit data resolution of the receiver */
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RESOLUTION_32_BIT = 0x5
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} i2s_word_length_t;
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typedef enum _fifo_threshold
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{
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/* Interrupt trigger when FIFO level is 1 */
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TRIGGER_LEVEL_1 = 0x0,
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/* Interrupt trigger when FIFO level is 2 */
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TRIGGER_LEVEL_2 = 0x1,
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/* Interrupt trigger when FIFO level is 3 */
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TRIGGER_LEVEL_3 = 0x2,
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/* Interrupt trigger when FIFO level is 4 */
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TRIGGER_LEVEL_4 = 0x3,
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/* Interrupt trigger when FIFO level is 5 */
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TRIGGER_LEVEL_5 = 0x4,
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/* Interrupt trigger when FIFO level is 6 */
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TRIGGER_LEVEL_6 = 0x5,
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/* Interrupt trigger when FIFO level is 7 */
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TRIGGER_LEVEL_7 = 0x6,
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/* Interrupt trigger when FIFO level is 8 */
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TRIGGER_LEVEL_8 = 0x7,
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/* Interrupt trigger when FIFO level is 9 */
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TRIGGER_LEVEL_9 = 0x8,
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/* Interrupt trigger when FIFO level is 10 */
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TRIGGER_LEVEL_10 = 0x9,
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/* Interrupt trigger when FIFO level is 11 */
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TRIGGER_LEVEL_11 = 0xa,
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/* Interrupt trigger when FIFO level is 12 */
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TRIGGER_LEVEL_12 = 0xb,
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/* Interrupt trigger when FIFO level is 13 */
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TRIGGER_LEVEL_13 = 0xc,
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/* Interrupt trigger when FIFO level is 14 */
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TRIGGER_LEVEL_14 = 0xd,
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/* Interrupt trigger when FIFO level is 15 */
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TRIGGER_LEVEL_15 = 0xe,
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/* Interrupt trigger when FIFO level is 16 */
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TRIGGER_LEVEL_16 = 0xf
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} i2s_fifo_threshold_t;
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typedef struct _i2s_ier
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{
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/* Bit 0 is ien, 0 for disable i2s and 1 for enable i2s */
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uint32_t ien : 1;
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/* Bits [31:1] is reserved */
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uint32_t resv : 31;
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} __attribute__((packed, aligned(4))) i2s_ier_t;
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typedef union _ier_u
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{
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i2s_ier_t ier;
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uint32_t reg_data;
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} ier_t;
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typedef struct _i2s_irer
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{
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/* Bit 0 is receiver block enable,
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* 0 for receiver disable
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* 1 for receiver enable
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*/
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uint32_t rxen : 1;
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/* Bits [31:1] is reserved */
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uint32_t resv : 31;
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} __attribute__((packed, aligned(4))) i2s_irer_t;
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typedef union _irer_u
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{
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i2s_irer_t irer;
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uint32_t reg_data;
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} irer_t;
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typedef struct _i2s_iter
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{
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uint32_t txen : 1;
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/* Bit 0 is transmitter block enable,
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* 0 for transmitter disable
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* 1 for transmitter enable
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*/
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uint32_t resv : 31;
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/* Bits [31:1] is reserved */
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} __attribute__((packed, aligned(4))) i2s_iter_t;
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typedef union _iter_u
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{
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i2s_iter_t iter;
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uint32_t reg_data;
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} iter_t;
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typedef struct _i2s_cer
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{
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uint32_t clken : 1;
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/* Bit 0 is clock generation enable/disable,
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* 0 for clock generation disable,
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* 1 for clock generation enable
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*/
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uint32_t resv : 31;
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/* Bits [31:1] is reserved */
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} __attribute__((packed, aligned(4))) i2s_cer_t;
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typedef union _cer_u
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{
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i2s_cer_t cer;
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uint32_t reg_data;
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} cer_t;
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typedef struct _i2s_ccr
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{
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/* Bits [2:0] is used to program the gating of sclk,
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* 0x0 for clock gating is diable,
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* 0x1 for gating after 12 sclk cycles
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* 0x2 for gating after 16 sclk cycles
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* 0x3 for gating after 20 sclk cycles
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* 0x4 for gating after 24 sclk cycles
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*/
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uint32_t clk_gate : 3;
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/* Bits [4:3] used program the number of sclk cycles for which the
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* word select line stayd in the left aligned or right aligned mode.
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* 0x0 for 16sclk cycles, 0x1 for 24 sclk cycles 0x2 for 32 sclk
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* cycles
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*/
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uint32_t clk_word_size : 2;
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/* Bit[5:7] is alignment mode setting.
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* 0x1 for standard i2s format
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* 0x2 for right aligned format
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* 0x4 for left aligned format
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*/
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uint32_t align_mode : 3;
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/* Bit[8] is DMA transmit enable control */
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uint32_t dma_tx_en : 1;
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/* Bit[9] is DMA receive enable control */
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uint32_t dma_rx_en : 1;
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uint32_t dma_divide_16 : 1;
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/* Bit[10] split 32bit data to two 16 bit data and filled in left
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* and right channel. Used with dma_tx_en or dma_rx_en
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*/
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uint32_t sign_expand_en : 1;
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uint32_t resv : 20;
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/* Bits [31:11] is reseved */
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} __attribute__((packed, aligned(4))) i2s_ccr_t;
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typedef union _ccr_u
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{
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i2s_ccr_t ccr;
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uint32_t reg_data;
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} ccr_t;
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typedef struct _i2s_rxffr
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{
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uint32_t rxffr : 1;
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/* Bit 0 is receiver FIFO reset,
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* 0 for does not flush RX FIFO, 1 for flush RX FIFO
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*/
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uint32_t resv : 31;
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/* Bits [31:1] is reserved */
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} __attribute__((packed, aligned(4))) i2s_rxffr_t;
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typedef union _rxffr_u
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{
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i2s_rxffr_t rxffr;
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uint32_t reg_data;
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} rxffr_t;
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typedef struct _i2s_lrbrthr
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{
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uint32_t fifo : 16;
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/* Bits [15:0] if used data receive or transmit */
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uint32_t resv : 16;
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} i2s_lrbrthr_t;
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typedef union _lrbthr_u
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{
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i2s_lrbrthr_t buffer;
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uint32_t reg_data;
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} lrbthr_t;
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typedef struct _i2s_rthr
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{
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/* Bits [15:0] is right stereo data transmitted serially
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* from transmit channel input
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*/
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uint32_t rthrx : 16;
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/* Bits [31:16] is reserved */
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uint32_t resv : 16;
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} __attribute__((packed, aligned(4))) i2s_rthr_t;
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typedef union _rthr_u
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{
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i2s_rthr_t rthr;
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uint32_t reg_data;
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} rthr_t;
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typedef struct _i2s_rer
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{
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/* Bit 0 is receive channel enable/disable, 0 for receive channel disable,
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*1 for receive channel enable
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*/
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uint32_t rxchenx : 1;
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/* Bits [31:1] is reseved */
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uint32_t resv : 31;
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} __attribute__((packed, aligned(4))) i2s_rer_t;
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typedef union _rer_u
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{
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i2s_rer_t rer;
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uint32_t reg_data;
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} rer_t;
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typedef struct _i2s_ter
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{
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/* Bit 0 is transmit channel enable/disable, 0 for transmit channel disable,
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* 1 for transmit channel enable
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*/
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uint32_t txchenx : 1;
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/* Bits [31:1] is reseved */
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uint32_t resv : 31;
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} __attribute__((packed, aligned(4))) i2s_ter_t;
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typedef union _ter_u
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{
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i2s_ter_t ter;
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uint32_t reg_data;
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} ter_t;
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typedef struct _i2s_rcr_tcr
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{
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/* Bits [2:0] is used to program desired data resolution of
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* receiver/transmitter,
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* 0x0 for ignore the word length
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* 0x1 for 12-bit data resolution of the receiver/transmitter,
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* 0x2 for 16-bit data resolution of the receiver/transmitter,
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* 0x3 for 20-bit data resolution of the receiver/transmitter,
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* 0x4 for 24-bit data resolution of the receiver/transmitter,
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* 0x5 for 32-bit data resolution of the receiver/transmitter
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*/
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uint32_t wlen : 3;
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/* Bits [31:3] is reseved */
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uint32_t resv : 29;
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} __attribute__((packed, aligned(4))) i2s_rcr_tcr_t;
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typedef union _rcr_tcr_u
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{
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i2s_rcr_tcr_t rcr_tcr;
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uint32_t reg_data;
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} rcr_tcr_t;
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typedef struct _i2s_isr
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{
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/* Bit 0 is status of receiver data avaliable interrupt
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* 0x0 for RX FIFO trigger level not reached
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* 0x1 for RX FIFO trigger level is reached
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*/
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uint32_t rxda : 1;
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/* Bit 1 is status of data overrun interrupt for rx channel
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* 0x0 for RX FIFO write valid
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* 0x1 for RX FIFO write overrun
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*/
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uint32_t rxfo : 1;
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/* Bits [3:2] is reserved */
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uint32_t resv1 : 2;
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/* Bit 4 is status of transmit empty triger interrupt
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* 0x0 for TX FIFO triiger level is reach
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* 0x1 for TX FIFO trigger level is not reached
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*/
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uint32_t txfe : 1;
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/* BIt 5 is status of data overrun interrupt for the TX channel
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* 0x0 for TX FIFO write valid
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* 0x1 for TX FIFO write overrun
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*/
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uint32_t txfo : 1;
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/* BIts [31:6] is reserved */
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uint32_t resv2 : 26;
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} __attribute__((packed, aligned(4))) i2s_isr_t;
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typedef union _isr_u
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{
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i2s_isr_t isr;
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uint32_t reg_data;
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} isr_t;
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typedef struct _i2s_imr
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{
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/* Bit 0 is mask RX FIFO data available interrupt
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* 0x0 for unmask RX FIFO data available interrupt
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* 0x1 for mask RX FIFO data available interrupt
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*/
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uint32_t rxdam : 1;
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/* Bit 1 is mask RX FIFO overrun interrupt
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* 0x0 for unmask RX FIFO overrun interrupt
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* 0x1 for mask RX FIFO overrun interrupt
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*/
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uint32_t rxfom : 1;
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/* Bits [3:2] is reserved */
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uint32_t resv1 : 2;
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/* Bit 4 is mask TX FIFO empty interrupt,
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* 0x0 for unmask TX FIFO empty interrupt,
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* 0x1 for mask TX FIFO empty interrupt
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*/
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uint32_t txfem : 1;
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/* BIt 5 is mask TX FIFO overrun interrupt
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* 0x0 for mask TX FIFO overrun interrupt
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* 0x1 for unmash TX FIFO overrun interrupt
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*/
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uint32_t txfom : 1;
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/* Bits [31:6] is reserved */
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uint32_t resv2 : 26;
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} __attribute__((packed, aligned(4))) i2s_imr_t;
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typedef union _imr_u
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{
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i2s_imr_t imr;
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uint32_t reg_data;
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} imr_t;
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typedef struct _i2s_ror
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{
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/* Bit 0 is read this bit to clear RX FIFO data overrun interrupt
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* 0x0 for RX FIFO write valid,
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*0x1 for RX FIFO write overrun
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*/
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uint32_t rxcho : 1;
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/* Bits [31:1] is reserved */
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uint32_t resv : 31;
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} __attribute__((packed, aligned(4))) i2s_ror_t;
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typedef union _ror_u
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{
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i2s_ror_t ror;
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uint32_t reg_data;
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} ror_t;
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typedef struct _i2s_tor
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{
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/* Bit 0 is read this bit to clear TX FIFO data overrun interrupt
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* 0x0 for TX FIFO write valid,
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*0x1 for TX FIFO write overrun
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*/
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uint32_t txcho : 1;
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/* Bits [31:1] is reserved */
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uint32_t resv : 31;
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} __attribute__((packed, aligned(4))) i2s_tor_t;
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typedef union _tor_u
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{
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i2s_tor_t tor;
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uint32_t reg_data;
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} tor_t;
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typedef struct _i2s_rfcr
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{
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/* Bits [3:0] is used program the trigger level in the RX FIFO at
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* which the receiver data available interrupt generate,
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* 0x0 for interrupt trigger when FIFO level is 1,
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* 0x2 for interrupt trigger when FIFO level is 2,
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* 0x3 for interrupt trigger when FIFO level is 4,
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* 0x4 for interrupt trigger when FIFO level is 5,
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* 0x5 for interrupt trigger when FIFO level is 6,
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* 0x6 for interrupt trigger when FIFO level is 7,
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* 0x7 for interrupt trigger when FIFO level is 8,
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* 0x8 for interrupt trigger when FIFO level is 9,
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* 0x9 for interrupt trigger when FIFO level is 10,
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* 0xa for interrupt trigger when FIFO level is 11,
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* 0xb for interrupt trigger when FIFO level is 12,
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* 0xc for interrupt trigger when FIFO level is 13,
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* 0xd for interrupt trigger when FIFO level is 14,
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* 0xe for interrupt trigger when FIFO level is 15,
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* 0xf for interrupt trigger when FIFO level is 16
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*/
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uint32_t rxchdt : 4;
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/* Bits [31:4] is reserved */
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uint32_t rsvd_rfcrx : 28;
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} __attribute__((packed, aligned(4))) i2s_rfcr_t;
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typedef union _rfcr_u
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{
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i2s_rfcr_t rfcr;
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uint32_t reg_data;
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} rfcr_t;
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typedef struct _i2s_tfcr
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{
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/* Bits [3:0] is used program the trigger level in the TX FIFO at
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* which the receiver data available interrupt generate,
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* 0x0 for interrupt trigger when FIFO level is 1,
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* 0x2 for interrupt trigger when FIFO level is 2,
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* 0x3 for interrupt trigger when FIFO level is 4,
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* 0x4 for interrupt trigger when FIFO level is 5,
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* 0x5 for interrupt trigger when FIFO level is 6,
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* 0x6 for interrupt trigger when FIFO level is 7,
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* 0x7 for interrupt trigger when FIFO level is 8,
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* 0x8 for interrupt trigger when FIFO level is 9,
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* 0x9 for interrupt trigger when FIFO level is 10,
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* 0xa for interrupt trigger when FIFO level is 11,
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* 0xb for interrupt trigger when FIFO level is 12,
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* 0xc for interrupt trigger when FIFO level is 13,
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* 0xd for interrupt trigger when FIFO level is 14,
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* 0xe for interrupt trigger when FIFO level is 15,
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* 0xf for interrupt trigger when FIFO level is 16
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*/
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uint32_t txchet : 4;
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/* Bits [31:4] is reserved */
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uint32_t rsvd_tfcrx : 28;
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} __attribute__((packed, aligned(4))) i2s_tfcr_t;
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typedef union _tfcr_u
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{
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i2s_tfcr_t tfcr;
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uint32_t reg_data;
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} tfcr_t;
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typedef struct _i2s_rff
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{
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/* Bit 0 is receiver channel FIFO reset,
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* 0x0 for does not flush an individual RX FIFO,
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* 0x1 for flush an indiviadual RX FIFO
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*/
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uint32_t rxchfr : 1;
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/*< Bits [31:1] is reserved ,write only */
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uint32_t rsvd_rffx : 31;
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} __attribute__((packed, aligned(4))) i2s_rff_t;
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typedef union _rff_u
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{
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i2s_rff_t rff;
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uint32_t reg_data;
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} rff_t;
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typedef struct _i2s_tff
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{
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/* Bit 0 is transmit channel FIFO reset,
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* 0x0 for does not flush an individual TX FIFO,
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* 0x1 for flush an indiviadual TX FIFO
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*/
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uint32_t rtxchfr : 1;
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/*< Bits [31:1] is reserved ,write only */
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uint32_t rsvd_rffx : 31;
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} __attribute__((packed, aligned(4))) i2s_tff_t;
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typedef union tff_u
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{
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i2s_tff_t tff;
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uint32_t reg_data;
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} tff_t;
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typedef struct _i2s_channel
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{
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/* Left Receive or Left Transmit Register (0x20) */
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volatile uint32_t left_rxtx;
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/* Right Receive or Right Transmit Register (0x24) */
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volatile uint32_t right_rxtx;
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/* Receive Enable Register (0x28) */
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volatile uint32_t rer;
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/* Transmit Enable Register (0x2c) */
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volatile uint32_t ter;
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/* Receive Configuration Register (0x30) */
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volatile uint32_t rcr;
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/* Transmit Configuration Register (0x34) */
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volatile uint32_t tcr;
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/* Interrupt Status Register (0x38) */
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volatile uint32_t isr;
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/* Interrupt Mask Register (0x3c) */
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volatile uint32_t imr;
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/* Receive Overrun Register (0x40) */
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volatile uint32_t ror;
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/* Transmit Overrun Register (0x44) */
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volatile uint32_t tor;
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/* Receive FIFO Configuration Register (0x48) */
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volatile uint32_t rfcr;
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/* Transmit FIFO Configuration Register (0x4c) */
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volatile uint32_t tfcr;
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/* Receive FIFO Flush Register (0x50) */
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volatile uint32_t rff;
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/* Transmit FIFO Flush Register (0x54) */
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volatile uint32_t tff;
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/* reserved (0x58-0x5c) */
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volatile uint32_t reserved1[2];
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} __attribute__((packed, aligned(4))) i2s_channel_t;
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/****is* i2s.api/dw_i2s_portmap
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* NAME
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* i2s_t
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* DESCRIPTION
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* This is the structure used for accessing the i2s register
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* portmap.
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* EXAMPLE
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* struct i2s_t *portmap;
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* portmap = (struct dw_i2s_portmap *) DW_APB_I2S_BASE;
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* SOURCE
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*/
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typedef struct _i2s
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{
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/* I2S Enable Register (0x00) */
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volatile uint32_t ier;
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/* I2S Receiver Block Enable Register (0x04) */
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volatile uint32_t irer;
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/* I2S Transmitter Block Enable Register (0x08) */
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volatile uint32_t iter;
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/* Clock Enable Register (0x0c) */
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volatile uint32_t cer;
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/* Clock Configuration Register (0x10) */
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volatile uint32_t ccr;
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/* Receiver Block FIFO Reset Register (0x04) */
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volatile uint32_t rxffr;
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/* Transmitter Block FIFO Reset Register (0x18) */
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volatile uint32_t txffr;
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/* reserved (0x1c) */
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volatile uint32_t reserved1;
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volatile i2s_channel_t channel[4];
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/* reserved (0x118-0x1bc) */
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volatile uint32_t reserved2[40];
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/* Receiver Block DMA Register (0x1c0) */
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volatile uint32_t rxdma;
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/* Reset Receiver Block DMA Register (0x1c4) */
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volatile uint32_t rrxdma;
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/* Transmitter Block DMA Register (0x1c8) */
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volatile uint32_t txdma;
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/* Reset Transmitter Block DMA Register (0x1cc) */
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volatile uint32_t rtxdma;
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/* reserved (0x1d0-0x1ec) */
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volatile uint32_t reserved3[8];
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/* Component Parameter Register 2 (0x1f0) */
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volatile uint32_t i2s_comp_param_2;
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/* Component Parameter Register 1 (0x1f4) */
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volatile uint32_t i2s_comp_param_1;
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/* I2S Component Version Register (0x1f8) */
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volatile uint32_t i2s_comp_version_1;
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/* I2S Component Type Register (0x1fc) */
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volatile uint32_t i2s_comp_type;
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} __attribute__((packed, aligned(4))) i2s_t;
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typedef enum _i2s_transfer_mode
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{
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I2S_SEND,
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I2S_RECEIVE,
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} i2s_transfer_mode_t;
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typedef struct _i2s_data_t
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{
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dmac_channel_number_t tx_channel;
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dmac_channel_number_t rx_channel;
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uint32_t *tx_buf;
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size_t tx_len;
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uint32_t *rx_buf;
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size_t rx_len;
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i2s_transfer_mode_t transfer_mode;
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bool nowait_dma_idle;
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|
bool wait_dma_done;
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} i2s_data_t;
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|
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/**
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* @brief I2S object instance
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|
*/
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extern volatile i2s_t *const i2s[3];
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|
|
/**
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|
* @brief I2s init
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|
*
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* @param[in] device_num The device number
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* @param[in] rxtx_mode I2s work mode
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* @param[in] channel_mask Channel mask to which channel work
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*
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|
*/
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void i2s_init(i2s_device_number_t device_num, i2s_transmit_t rxtx_mode, uint32_t channel_mask);
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|
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/**
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* @brief Read pcm data from dma
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|
*
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|
* @param[in] device_num which of device
|
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* @param[in] buf save read data
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|
* @param[in] buf_len the length to read form i2s
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|
* @param[in] channel_num The dma channel number
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*
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|
* @return result
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* - 0 Success
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|
* - Other Fail
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|
*/
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void i2s_receive_data_dma(i2s_device_number_t device_num, uint32_t *buf, size_t buf_len,
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dmac_channel_number_t channel_num);
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|
|
|
/**
|
|
* @brief Write pcm data to channel_num channel by dma, first wait dmac done
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|
*
|
|
* @param[in] device_num which of device
|
|
* @param[in] pcm Send data
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|
* @param[in] buf_len Send data length
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|
* @param[in] channel_num dmac channel
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*
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|
*/
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void i2s_send_data_dma(i2s_device_number_t device_num, const void *buf, size_t buf_len, dmac_channel_number_t channel_num);
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|
|
/**
|
|
* @brief I2S receive channel configure
|
|
*
|
|
* @param[in] device_num The device number
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] word_length The word length
|
|
* @param[in] word_select_size The word select size
|
|
* @param[in] trigger_level The trigger level
|
|
*/
|
|
void i2s_rx_channel_config(i2s_device_number_t device_num,
|
|
i2s_channel_num_t channel_num,
|
|
i2s_word_length_t word_length,
|
|
i2s_word_select_cycles_t word_select_size,
|
|
i2s_fifo_threshold_t trigger_level,
|
|
i2s_work_mode_t word_mode);
|
|
|
|
/**
|
|
* @brief I2S transmit channel enable
|
|
*
|
|
* @param[in] device_num The device number
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] word_length The word length
|
|
* @param[in] word_select_size The word select size
|
|
* @param[in] trigger_level The trigger level
|
|
*/
|
|
void i2s_tx_channel_config(i2s_device_number_t device_num,
|
|
i2s_channel_num_t channel_num,
|
|
i2s_word_length_t word_length,
|
|
i2s_word_select_cycles_t word_select_size,
|
|
i2s_fifo_threshold_t trigger_level,
|
|
i2s_work_mode_t word_mode);
|
|
|
|
/**
|
|
* @brief Play PCM format audio
|
|
*
|
|
* @param[in] device_num The device number
|
|
* @param[in] channel_num The channel number
|
|
* @param[in] buf PCM data
|
|
* @param[in] buf_len PCM data length
|
|
* @param[in] frame Transmit amount once
|
|
* @param[in] bits_per_sample Sample bit length
|
|
* @param[in] track_num Track amount
|
|
*/
|
|
void i2s_play(i2s_device_number_t device_num, dmac_channel_number_t channel_num,
|
|
const uint8_t *buf, size_t buf_len, size_t frame, size_t bits_per_sample, uint8_t track_num);
|
|
|
|
/**
|
|
* @brief Play PCM format audio
|
|
*
|
|
* @param[in] device_num The device number
|
|
* @param[in] sample_rate The Sample rate
|
|
*
|
|
*
|
|
* @return The real sample rate
|
|
*/
|
|
uint32_t i2s_set_sample_rate(i2s_device_number_t device_num, uint32_t sample_rate);
|
|
|
|
/**
|
|
* @brief Set dma_divide_16 split 32bit data to two 16 bit data and filled in left
|
|
* and right channel. Used with dma_tx_en or dma_rx_en
|
|
*
|
|
* @param[in] device_num The device number
|
|
* @param[in] enable The value of dma_divide_16 0:disable 1:enable
|
|
*
|
|
* @return result
|
|
* - 0 Success
|
|
* - Other Fail
|
|
*/
|
|
int i2s_set_dma_divide_16(i2s_device_number_t device_num, uint32_t enable);
|
|
|
|
/**
|
|
* @brief Get dma_divide_16.
|
|
*
|
|
* @param[in] device_num The device number
|
|
*
|
|
* @return result
|
|
* - <0 Fail
|
|
* - other value of dma_divide_16
|
|
*/
|
|
int i2s_get_dma_divide_16(i2s_device_number_t device_num);
|
|
|
|
/**
|
|
* @brief I2s handle transfer data operations
|
|
*
|
|
* @param[in] device_num I2s device number
|
|
* @param[in] data I2s data information
|
|
* @param[in] cb I2s dma callback
|
|
*
|
|
*/
|
|
void i2s_handle_data_dma(i2s_device_number_t device_num, i2s_data_t data, plic_interrupt_t *cb);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|