484 lines
17 KiB
C
484 lines
17 KiB
C
/* Copyright 2018 Canaan Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef _DRIVER_SPI_H
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#define _DRIVER_SPI_H
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#include <stddef.h>
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#include <stdint.h>
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#include "dmac.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* clang-format off */
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typedef struct _spi
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{
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/* SPI Control Register 0 (0x00)*/
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volatile uint32_t ctrlr0;
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/* SPI Control Register 1 (0x04)*/
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volatile uint32_t ctrlr1;
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/* SPI Enable Register (0x08)*/
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volatile uint32_t ssienr;
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/* SPI Microwire Control Register (0x0c)*/
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volatile uint32_t mwcr;
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/* SPI Slave Enable Register (0x10)*/
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volatile uint32_t ser;
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/* SPI Baud Rate Select (0x14)*/
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volatile uint32_t baudr;
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/* SPI Transmit FIFO Threshold Level (0x18)*/
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volatile uint32_t txftlr;
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/* SPI Receive FIFO Threshold Level (0x1c)*/
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volatile uint32_t rxftlr;
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/* SPI Transmit FIFO Level Register (0x20)*/
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volatile uint32_t txflr;
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/* SPI Receive FIFO Level Register (0x24)*/
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volatile uint32_t rxflr;
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/* SPI Status Register (0x28)*/
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volatile uint32_t sr;
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/* SPI Interrupt Mask Register (0x2c)*/
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volatile uint32_t imr;
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/* SPI Interrupt Status Register (0x30)*/
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volatile uint32_t isr;
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/* SPI Raw Interrupt Status Register (0x34)*/
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volatile uint32_t risr;
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/* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38)*/
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volatile uint32_t txoicr;
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/* SPI Receive FIFO Overflow Interrupt Clear Register (0x3c)*/
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volatile uint32_t rxoicr;
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/* SPI Receive FIFO Underflow Interrupt Clear Register (0x40)*/
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volatile uint32_t rxuicr;
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/* SPI Multi-Master Interrupt Clear Register (0x44)*/
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volatile uint32_t msticr;
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/* SPI Interrupt Clear Register (0x48)*/
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volatile uint32_t icr;
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/* SPI DMA Control Register (0x4c)*/
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volatile uint32_t dmacr;
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/* SPI DMA Transmit Data Level (0x50)*/
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volatile uint32_t dmatdlr;
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/* SPI DMA Receive Data Level (0x54)*/
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volatile uint32_t dmardlr;
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/* SPI Identification Register (0x58)*/
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volatile uint32_t idr;
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/* SPI DWC_ssi component version (0x5c)*/
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volatile uint32_t ssic_version_id;
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/* SPI Data Register 0-36 (0x60 -- 0xec)*/
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volatile uint32_t dr[36];
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/* SPI RX Sample Delay Register (0xf0)*/
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volatile uint32_t rx_sample_delay;
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/* SPI SPI Control Register (0xf4)*/
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volatile uint32_t spi_ctrlr0;
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/* reserved (0xf8)*/
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volatile uint32_t resv;
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/* SPI XIP Mode bits (0xfc)*/
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volatile uint32_t xip_mode_bits;
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/* SPI XIP INCR transfer opcode (0x100)*/
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volatile uint32_t xip_incr_inst;
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/* SPI XIP WRAP transfer opcode (0x104)*/
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volatile uint32_t xip_wrap_inst;
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/* SPI XIP Control Register (0x108)*/
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volatile uint32_t xip_ctrl;
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/* SPI XIP Slave Enable Register (0x10c)*/
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volatile uint32_t xip_ser;
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/* SPI XIP Receive FIFO Overflow Interrupt Clear Register (0x110)*/
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volatile uint32_t xrxoicr;
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/* SPI XIP time out register for continuous transfers (0x114)*/
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volatile uint32_t xip_cnt_time_out;
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volatile uint32_t endian;
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} __attribute__((packed, aligned(4))) spi_t;
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/* clang-format on */
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typedef enum _spi_device_num
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{
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SPI_DEVICE_0,
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SPI_DEVICE_1,
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SPI_DEVICE_2,
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SPI_DEVICE_3,
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SPI_DEVICE_MAX,
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} spi_device_num_t;
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typedef enum _spi_work_mode
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{
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SPI_WORK_MODE_0,
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SPI_WORK_MODE_1,
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SPI_WORK_MODE_2,
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SPI_WORK_MODE_3,
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} spi_work_mode_t;
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typedef enum _spi_frame_format
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{
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SPI_FF_STANDARD,
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SPI_FF_DUAL,
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SPI_FF_QUAD,
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SPI_FF_OCTAL
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} spi_frame_format_t;
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typedef enum _spi_instruction_address_trans_mode
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{
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SPI_AITM_STANDARD,
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SPI_AITM_ADDR_STANDARD,
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SPI_AITM_AS_FRAME_FORMAT
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} spi_instruction_address_trans_mode_t;
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typedef enum _spi_transfer_mode
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{
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SPI_TMOD_TRANS_RECV,
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SPI_TMOD_TRANS,
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SPI_TMOD_RECV,
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SPI_TMOD_EEROM
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} spi_transfer_mode_t;
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typedef enum _spi_transfer_width
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{
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SPI_TRANS_CHAR = 0x1,
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SPI_TRANS_SHORT = 0x2,
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SPI_TRANS_INT = 0x4,
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} spi_transfer_width_t;
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typedef enum _spi_chip_select
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{
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SPI_CHIP_SELECT_0,
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SPI_CHIP_SELECT_1,
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SPI_CHIP_SELECT_2,
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SPI_CHIP_SELECT_3,
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SPI_CHIP_SELECT_MAX,
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} spi_chip_select_t;
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typedef enum
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{
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WRITE_CONFIG,
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READ_CONFIG,
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WRITE_DATA_BYTE,
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READ_DATA_BYTE,
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WRITE_DATA_BLOCK,
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READ_DATA_BLOCK,
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} spi_slave_command_e;
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typedef struct
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{
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uint8_t cmd;
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uint8_t err;
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uint32_t addr;
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uint32_t len;
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} spi_slave_command_t;
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typedef enum
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{
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IDLE,
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COMMAND,
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TRANSFER,
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} spi_slave_status_e;
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typedef int (*spi_slave_receive_callback_t)(void *ctx);
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typedef struct _spi_slave_instance
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{
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uint8_t int_pin;
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uint8_t ready_pin;
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dmac_channel_number_t dmac_channel;
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uint8_t dfs;
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uint8_t slv_oe;
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uint8_t work_mode;
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size_t data_bit_length;
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volatile spi_slave_status_e status;
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volatile spi_slave_command_t command;
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volatile uint8_t *config_ptr;
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uint32_t config_len;
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spi_slave_receive_callback_t callback;
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} spi_slave_instance_t;
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typedef struct _spi_data_t
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{
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dmac_channel_number_t tx_channel;
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dmac_channel_number_t rx_channel;
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uint32_t *tx_buf;
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size_t tx_len;
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uint32_t *rx_buf;
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size_t rx_len;
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spi_transfer_mode_t transfer_mode;
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bool fill_mode;
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} spi_data_t;
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extern volatile spi_t *const spi[4];
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/**
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* @brief Set spi configuration
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*
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* @param[in] spi_num Spi bus number
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* @param[in] mode Spi mode
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* @param[in] frame_format Spi frame format
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* @param[in] data_bit_length Spi data bit length
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* @param[in] endian 0:little-endian 1:big-endian
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*
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* @return Void
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*/
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void spi_init(spi_device_num_t spi_num, spi_work_mode_t work_mode, spi_frame_format_t frame_format,
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size_t data_bit_length, uint32_t endian);
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/**
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* @brief Set multiline configuration
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*
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* @param[in] spi_num Spi bus number
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* @param[in] instruction_length Instruction length
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* @param[in] address_length Address length
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* @param[in] wait_cycles Wait cycles
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* @param[in] instruction_address_trans_mode Spi transfer mode
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*
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*/
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void spi_init_non_standard(spi_device_num_t spi_num, uint32_t instruction_length, uint32_t address_length,
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uint32_t wait_cycles, spi_instruction_address_trans_mode_t instruction_address_trans_mode);
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/**
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* @brief Spi send data
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*
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_send_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff,
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size_t cmd_len, const uint8_t *tx_buff, size_t tx_len);
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/**
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* @brief Spi receive data
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*
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_receive_data_standard(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff,
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size_t cmd_len, uint8_t *rx_buff, size_t rx_len);
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/**
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* @brief Spi special receive data
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*
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_receive_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff,
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size_t cmd_len, uint8_t *rx_buff, size_t rx_len);
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/**
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* @brief Spi special send data
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*
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_send_data_multiple(spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff,
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size_t cmd_len, const uint8_t *tx_buff, size_t tx_len);
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/**
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* @brief Spi send data by dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_send_data_standard_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
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spi_chip_select_t chip_select,
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const uint8_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len);
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/**
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* @brief Spi receive data by dma
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*
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* @param[in] w_channel_num Dmac write channel number
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* @param[in] r_channel_num Dmac read channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_receive_data_standard_dma(dmac_channel_number_t dma_send_channel_num,
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dmac_channel_number_t dma_receive_channel_num,
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spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint8_t *cmd_buff,
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size_t cmd_len, uint8_t *rx_buff, size_t rx_len);
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/**
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* @brief Spi special send data by dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_send_data_multiple_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
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spi_chip_select_t chip_select,
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const uint32_t *cmd_buff, size_t cmd_len, const uint8_t *tx_buff, size_t tx_len);
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/**
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* @brief Spi special receive data by dma
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*
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* @param[in] dma_send_channel_num Dmac write channel number
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* @param[in] dma_receive_channel_num Dmac read channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] cmd_buff Spi command buffer point
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* @param[in] cmd_len Spi command length
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* @param[in] rx_buff Spi receive buffer point
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* @param[in] rx_len Spi receive buffer length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_receive_data_multiple_dma(dmac_channel_number_t dma_send_channel_num,
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dmac_channel_number_t dma_receive_channel_num,
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spi_device_num_t spi_num, spi_chip_select_t chip_select, const uint32_t *cmd_buff,
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size_t cmd_len, uint8_t *rx_buff, size_t rx_len);
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/**
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* @brief Spi fill dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] tx_buff Spi command buffer point
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* @param[in] tx_len Spi command length
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_fill_data_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num, spi_chip_select_t chip_select,
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const uint32_t *tx_buff, size_t tx_len);
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/**
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* @brief Spi normal send by dma
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*
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* @param[in] channel_num Dmac channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] tx_buff Spi transmit buffer point
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* @param[in] tx_len Spi transmit buffer length
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* @param[in] stw Spi transfer width
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*
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* @return Result
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* - 0 Success
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* - Other Fail
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*/
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void spi_send_data_normal_dma(dmac_channel_number_t channel_num, spi_device_num_t spi_num,
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spi_chip_select_t chip_select,
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const void *tx_buff, size_t tx_len, spi_transfer_width_t spi_transfer_width);
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/**
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* @brief Spi normal send by dma
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*
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* @param[in] spi_num Spi bus number
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* @param[in] spi_clk Spi clock rate
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*
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* @return The real spi clock rate
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*/
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uint32_t spi_set_clk_rate(spi_device_num_t spi_num, uint32_t spi_clk);
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/**
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* @brief Spi full duplex send receive data by dma
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*
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* @param[in] dma_send_channel_num Dmac write channel number
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* @param[in] dma_receive_channel_num Dmac read channel number
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] tx_buf Spi send buffer
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* @param[in] tx_len Spi send buffer length
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* @param[in] rx_buf Spi receive buffer
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* @param[in] rx_len Spi receive buffer length
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*
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*/
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void spi_dup_send_receive_data_dma(dmac_channel_number_t dma_send_channel_num,
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dmac_channel_number_t dma_receive_channel_num,
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spi_device_num_t spi_num, spi_chip_select_t chip_select,
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const uint8_t *tx_buf, size_t tx_len, uint8_t *rx_buf, size_t rx_len);
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/**
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* @brief Set spi slave configuration
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*
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* @param[in] int_pin SPI master starts sending data interrupt.
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* @param[in] ready_pin SPI slave ready.
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* @param[in] dmac_channel Dmac channel number for block.
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* @param[in] data_bit_length Spi data bit length
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* @param[in] data SPI slave device data buffer.
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* @param[in] len The length of SPI slave device data buffer.
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* @param[in] callback Callback of spi slave.
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*
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* @return Void
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*/
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void spi_slave_config(uint8_t int_pin, uint8_t ready_pin, dmac_channel_number_t dmac_channel, size_t data_bit_length, uint8_t *data, uint32_t len, spi_slave_receive_callback_t callback);
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/**
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* @brief Spi handle transfer data operations
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*
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* @param[in] spi_num Spi bus number
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* @param[in] chip_select Spi chip select
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* @param[in] data Spi transfer data information
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* @param[in] cb Spi DMA callback
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*
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*/
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void spi_handle_data_dma(spi_device_num_t spi_num, spi_chip_select_t chip_select, spi_data_t data, plic_interrupt_t *cb);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _DRIVER_SPI_H */
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