first commit
commit
fce79b293d
|
@ -0,0 +1,15 @@
|
|||
autom4te.cache
|
||||
build
|
||||
build_i
|
||||
config.log
|
||||
config.status
|
||||
Makefile
|
||||
.DS_Store
|
||||
!/regression/Makefile
|
||||
.vs
|
||||
.vscode
|
||||
CMakeSettings.json
|
||||
.idea
|
||||
*.tar
|
||||
*.tar.*
|
||||
cmake-build-*
|
|
@ -0,0 +1,7 @@
|
|||
Changelog for Kendryte K210
|
||||
======
|
||||
|
||||
## 0.1.0
|
||||
|
||||
Kendryte K210 first SDK with FreeRTOS, have fun.
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
### This file is used for build example projects.
|
||||
|
||||
# set this will supress some warnings
|
||||
set(BUILDING_SDK "yes" CACHE INTERNAL "")
|
||||
|
||||
# basic config
|
||||
if (NOT PROJ)
|
||||
message(FATAL_ERROR "PROJ must be set. e.g. -DPROJ=hello_world")
|
||||
else()
|
||||
message("PROJ = ${PROJ}")
|
||||
endif ()
|
||||
cmake_minimum_required(VERSION 3.0)
|
||||
include(./cmake/common.cmake)
|
||||
project(${PROJ})
|
||||
|
||||
# config self use headers
|
||||
header_directories(${SDK_ROOT}/lib)
|
||||
# build library first
|
||||
add_subdirectory(lib SDK)
|
||||
|
||||
# TODO
|
||||
#add_subdirectory(third_party)
|
||||
|
||||
# compile project
|
||||
add_source_files(src/${PROJ}/*.c src/${PROJ}/*.s src/${PROJ}/*.S src/${PROJ}/*.cpp)
|
||||
include(./cmake/executable.cmake)
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
cmake_minimum_required(VERSION 3.0)
|
||||
|
||||
## Required Variable: (if you do not use Kendryte IDE)
|
||||
# -DTOOLCHAIN=/path/to/rsicv/toolchain/bin
|
||||
# -DSDK=/path/to/SDK (the folder of this example file)
|
||||
|
||||
## Include the SDK library
|
||||
include("${SDK}/cmake/common.cmake")
|
||||
|
||||
## Use SDK library API to add source files
|
||||
add_source_files(src/hello_world/main.c)
|
||||
|
||||
# other cmake instructions
|
||||
|
||||
## Use SDK builder to build this project
|
||||
include("${SDK}/cmake/executable.cmake")
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
|
||||
Apache License
|
||||
Version 2.0, January 2004
|
||||
http://www.apache.org/licenses/
|
||||
|
||||
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
|
||||
|
||||
1. Definitions.
|
||||
|
||||
"License" shall mean the terms and conditions for use, reproduction,
|
||||
and distribution as defined by Sections 1 through 9 of this document.
|
||||
|
||||
"Licensor" shall mean the copyright owner or entity authorized by
|
||||
the copyright owner that is granting the License.
|
||||
|
||||
"Legal Entity" shall mean the union of the acting entity and all
|
||||
other entities that control, are controlled by, or are under common
|
||||
control with that entity. For the purposes of this definition,
|
||||
"control" means (i) the power, direct or indirect, to cause the
|
||||
direction or management of such entity, whether by contract or
|
||||
otherwise, or (ii) ownership of fifty percent (50%) or more of the
|
||||
outstanding shares, or (iii) beneficial ownership of such entity.
|
||||
|
||||
"You" (or "Your") shall mean an individual or Legal Entity
|
||||
exercising permissions granted by this License.
|
||||
|
||||
"Source" form shall mean the preferred form for making modifications,
|
||||
including but not limited to software source code, documentation
|
||||
source, and configuration files.
|
||||
|
||||
"Object" form shall mean any form resulting from mechanical
|
||||
transformation or translation of a Source form, including but
|
||||
not limited to compiled object code, generated documentation,
|
||||
and conversions to other media types.
|
||||
|
||||
"Work" shall mean the work of authorship, whether in Source or
|
||||
Object form, made available under the License, as indicated by a
|
||||
copyright notice that is included in or attached to the work
|
||||
(an example is provided in the Appendix below).
|
||||
|
||||
"Derivative Works" shall mean any work, whether in Source or Object
|
||||
form, that is based on (or derived from) the Work and for which the
|
||||
editorial revisions, annotations, elaborations, or other modifications
|
||||
represent, as a whole, an original work of authorship. For the purposes
|
||||
of this License, Derivative Works shall not include works that remain
|
||||
separable from, or merely link (or bind by name) to the interfaces of,
|
||||
the Work and Derivative Works thereof.
|
||||
|
||||
"Contribution" shall mean any work of authorship, including
|
||||
the original version of the Work and any modifications or additions
|
||||
to that Work or Derivative Works thereof, that is intentionally
|
||||
submitted to Licensor for inclusion in the Work by the copyright owner
|
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or by an individual or Legal Entity authorized to submit on behalf of
|
||||
the copyright owner. For the purposes of this definition, "submitted"
|
||||
means any form of electronic, verbal, or written communication sent
|
||||
to the Licensor or its representatives, including but not limited to
|
||||
communication on electronic mailing lists, source code control systems,
|
||||
and issue tracking systems that are managed by, or on behalf of, the
|
||||
Licensor for the purpose of discussing and improving the Work, but
|
||||
excluding communication that is conspicuously marked or otherwise
|
||||
designated in writing by the copyright owner as "Not a Contribution."
|
||||
|
||||
"Contributor" shall mean Licensor and any individual or Legal Entity
|
||||
on behalf of whom a Contribution has been received by Licensor and
|
||||
subsequently incorporated within the Work.
|
||||
|
||||
2. Grant of Copyright License. Subject to the terms and conditions of
|
||||
this License, each Contributor hereby grants to You a perpetual,
|
||||
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
copyright license to reproduce, prepare Derivative Works of,
|
||||
publicly display, publicly perform, sublicense, and distribute the
|
||||
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||||
|
||||
3. Grant of Patent License. Subject to the terms and conditions of
|
||||
this License, each Contributor hereby grants to You a perpetual,
|
||||
worldwide, non-exclusive, no-charge, royalty-free, irrevocable
|
||||
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|
||||
use, offer to sell, sell, import, and otherwise transfer the Work,
|
||||
where such license applies only to those patent claims licensable
|
||||
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|
||||
Contribution(s) alone or by combination of their Contribution(s)
|
||||
with the Work to which such Contribution(s) was submitted. If You
|
||||
institute patent litigation against any entity (including a
|
||||
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|
||||
or a Contribution incorporated within the Work constitutes direct
|
||||
or contributory patent infringement, then any patent licenses
|
||||
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|
||||
as of the date such litigation is filed.
|
||||
|
||||
4. Redistribution. You may reproduce and distribute copies of the
|
||||
Work or Derivative Works thereof in any medium, with or without
|
||||
modifications, and in Source or Object form, provided that You
|
||||
meet the following conditions:
|
||||
|
||||
(a) You must give any other recipients of the Work or
|
||||
Derivative Works a copy of this License; and
|
||||
|
||||
(b) You must cause any modified files to carry prominent notices
|
||||
stating that You changed the files; and
|
||||
|
||||
(c) You must retain, in the Source form of any Derivative Works
|
||||
that You distribute, all copyright, patent, trademark, and
|
||||
attribution notices from the Source form of the Work,
|
||||
excluding those notices that do not pertain to any part of
|
||||
the Derivative Works; and
|
||||
|
||||
(d) If the Work includes a "NOTICE" text file as part of its
|
||||
distribution, then any Derivative Works that You distribute must
|
||||
include a readable copy of the attribution notices contained
|
||||
within such NOTICE file, excluding those notices that do not
|
||||
pertain to any part of the Derivative Works, in at least one
|
||||
of the following places: within a NOTICE text file distributed
|
||||
as part of the Derivative Works; within the Source form or
|
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documentation, if provided along with the Derivative Works; or,
|
||||
within a display generated by the Derivative Works, if and
|
||||
wherever such third-party notices normally appear. The contents
|
||||
of the NOTICE file are for informational purposes only and
|
||||
do not modify the License. You may add Your own attribution
|
||||
notices within Derivative Works that You distribute, alongside
|
||||
or as an addendum to the NOTICE text from the Work, provided
|
||||
that such additional attribution notices cannot be construed
|
||||
as modifying the License.
|
||||
|
||||
You may add Your own copyright statement to Your modifications and
|
||||
may provide additional or different license terms and conditions
|
||||
for use, reproduction, or distribution of Your modifications, or
|
||||
for any such Derivative Works as a whole, provided Your use,
|
||||
reproduction, and distribution of the Work otherwise complies with
|
||||
the conditions stated in this License.
|
||||
|
||||
5. Submission of Contributions. Unless You explicitly state otherwise,
|
||||
any Contribution intentionally submitted for inclusion in the Work
|
||||
by You to the Licensor shall be under the terms and conditions of
|
||||
this License, without any additional terms or conditions.
|
||||
Notwithstanding the above, nothing herein shall supersede or modify
|
||||
the terms of any separate license agreement you may have executed
|
||||
with Licensor regarding such Contributions.
|
||||
|
||||
6. Trademarks. This License does not grant permission to use the trade
|
||||
names, trademarks, service marks, or product names of the Licensor,
|
||||
except as required for reasonable and customary use in describing the
|
||||
origin of the Work and reproducing the content of the NOTICE file.
|
||||
|
||||
7. Disclaimer of Warranty. Unless required by applicable law or
|
||||
agreed to in writing, Licensor provides the Work (and each
|
||||
Contributor provides its Contributions) on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
|
||||
implied, including, without limitation, any warranties or conditions
|
||||
of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
|
||||
PARTICULAR PURPOSE. You are solely responsible for determining the
|
||||
appropriateness of using or redistributing the Work and assume any
|
||||
risks associated with Your exercise of permissions under this License.
|
||||
|
||||
8. Limitation of Liability. In no event and under no legal theory,
|
||||
whether in tort (including negligence), contract, or otherwise,
|
||||
unless required by applicable law (such as deliberate and grossly
|
||||
negligent acts) or agreed to in writing, shall any Contributor be
|
||||
liable to You for damages, including any direct, indirect, special,
|
||||
incidental, or consequential damages of any character arising as a
|
||||
result of this License or out of the use or inability to use the
|
||||
Work (including but not limited to damages for loss of goodwill,
|
||||
work stoppage, computer failure or malfunction, or any and all
|
||||
other commercial damages or losses), even if such Contributor
|
||||
has been advised of the possibility of such damages.
|
||||
|
||||
9. Accepting Warranty or Additional Liability. While redistributing
|
||||
the Work or Derivative Works thereof, You may choose to offer,
|
||||
and charge a fee for, acceptance of support, warranty, indemnity,
|
||||
or other liability obligations and/or rights consistent with this
|
||||
License. However, in accepting such obligations, You may act only
|
||||
on Your own behalf and on Your sole responsibility, not on behalf
|
||||
of any other Contributor, and only if You agree to indemnify,
|
||||
defend, and hold each Contributor harmless for any liability
|
||||
incurred by, or claims asserted against, such Contributor by reason
|
||||
of your accepting any such warranty or additional liability.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
APPENDIX: How to apply the Apache License to your work.
|
||||
|
||||
To apply the Apache License to your work, attach the following
|
||||
boilerplate notice, with the fields enclosed by brackets "[]"
|
||||
replaced with your own identifying information. (Don't include
|
||||
the brackets!) The text should be enclosed in the appropriate
|
||||
comment syntax for the file format. We also recommend that a
|
||||
file or class name and description of purpose be included on the
|
||||
same "printed page" as the copyright notice for easier
|
||||
identification within third-party archives.
|
||||
|
||||
Copyright 2018 Canaan Inc.
|
||||
|
||||
Licensed under the Apache License, Version 2.0 (the "License");
|
||||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
|
@ -0,0 +1,23 @@
|
|||
Kendryte K210 SDK
|
||||
======
|
||||
|
||||
This SDK is for Kendryte K210 which contains FreeRTOS support.
|
||||
If you have any questions, please be free to contact us.
|
||||
|
||||
# Usage
|
||||
|
||||
If you want to start a new project, for instance, `hello_world`, you only need to:
|
||||
|
||||
`mkdir` your project in `src/`, `cd src && mkdir hello_world`, then put your codes in it, and build it.
|
||||
|
||||
```shell
|
||||
mkdir build && cd build
|
||||
cmake .. -DPROJ=<ProjectName> -DTOOLCHAIN=/opt/riscv-toolchain/bin && make
|
||||
```
|
||||
|
||||
You will get 2 key files, `hello_world` and `hello_world.bin`.
|
||||
|
||||
1. If you are using JLink to run or debug your program, use `hello_world`
|
||||
2. If you want to flash it in UOG, using `hello_world.bin`, then using flash-tool(s) burn <ProjectName>.bin to your flash.
|
||||
|
||||
This is very important, don't make a mistake in files.
|
|
@ -0,0 +1,31 @@
|
|||
### This file is used for build library standalone.
|
||||
|
||||
# set this will supress some warnings
|
||||
set(BUILDING_SDK "yes" CACHE INTERNAL "")
|
||||
|
||||
# basic config
|
||||
cmake_minimum_required(VERSION 3.0)
|
||||
include(./common.cmake)
|
||||
project(kendryte)
|
||||
|
||||
# config self use headers
|
||||
header_directories(../lib)
|
||||
# build library first
|
||||
add_subdirectory(../lib SDK)
|
||||
|
||||
# copy utils files
|
||||
install(DIRECTORY
|
||||
../lds
|
||||
../utils
|
||||
../cmake
|
||||
DESTINATION ${CMAKE_BINARY_DIR}/archive
|
||||
PATTERN "CMakeLists.txt" EXCLUDE
|
||||
PATTERN ".c" EXCLUDE
|
||||
)
|
||||
install(DIRECTORY
|
||||
../lib
|
||||
DESTINATION ${CMAKE_BINARY_DIR}/archive
|
||||
)
|
||||
|
||||
# show information
|
||||
include(./dump-config.cmake)
|
|
@ -0,0 +1,43 @@
|
|||
cmake_minimum_required(VERSION 3.0)
|
||||
cmake_policy(VERSION 3.10)
|
||||
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/macros.cmake)
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/macros.internal.cmake)
|
||||
|
||||
global_set(CMAKE_C_COMPILER_WORKS 1)
|
||||
global_set(CMAKE_CXX_COMPILER_WORKS 1)
|
||||
|
||||
global_set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE)
|
||||
|
||||
global_set(CMAKE_SYSTEM_NAME "Generic")
|
||||
if (NOT CMAKE_BUILD_TYPE)
|
||||
global_set(CMAKE_BUILD_TYPE Debug)
|
||||
else ()
|
||||
# if ((NOT CMAKE_BUILD_TYPE STREQUAL "Debug") AND (NOT CMAKE_BUILD_TYPE STREQUAL "Release"))
|
||||
# message(FATAL_ERROR "CMAKE_BUILD_TYPE must either be Debug or Release instead of ${CMAKE_BUILD_TYPE}")
|
||||
# endif ()
|
||||
endif ()
|
||||
|
||||
# - Debug & Release
|
||||
IF (CMAKE_BUILD_TYPE STREQUAL Debug)
|
||||
add_definitions(-DDEBUG=1)
|
||||
ENDIF ()
|
||||
|
||||
# definitions in macros
|
||||
add_definitions(-DCONFIG_LOG_LEVEL=LOG_INFO -DCONFIG_LOG_ENABLE -DCONFIG_LOG_COLORS -DLOG_KERNEL -D__riscv64)
|
||||
|
||||
if (NOT SDK_ROOT)
|
||||
get_filename_component(_SDK_ROOT ${CMAKE_CURRENT_LIST_DIR} DIRECTORY)
|
||||
global_set(SDK_ROOT ${_SDK_ROOT})
|
||||
endif ()
|
||||
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/toolchain.cmake)
|
||||
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/compile-flags.cmake)
|
||||
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/fix-9985.cmake)
|
||||
|
||||
#add_source_files(${CMAKE_CURRENT_LIST_DIR}/../lib/bsp/crt.S)
|
||||
|
||||
removeDuplicateSubstring(${CMAKE_C_FLAGS} CMAKE_C_FLAGS)
|
||||
removeDuplicateSubstring(${CMAKE_CXX_FLAGS} CMAKE_CXX_FLAGS)
|
|
@ -0,0 +1,50 @@
|
|||
add_compile_flags(LD
|
||||
-nostartfiles
|
||||
-static
|
||||
-Wl,--gc-sections
|
||||
-Wl,-static
|
||||
-Wl,--start-group
|
||||
-Wl,--whole-archive
|
||||
-Wl,--no-whole-archive
|
||||
-Wl,--end-group
|
||||
-Wl,-EL
|
||||
"-T \"${SDK_ROOT}/lds/kendryte.ld\""
|
||||
)
|
||||
|
||||
# C Flags Settings
|
||||
add_compile_flags(BOTH
|
||||
-mcmodel=medany
|
||||
-fno-common
|
||||
-ffunction-sections
|
||||
-fdata-sections
|
||||
-fstrict-volatile-bitfields
|
||||
-Os
|
||||
-ggdb
|
||||
)
|
||||
|
||||
add_compile_flags(C -std=gnu11)
|
||||
add_compile_flags(CXX -std=gnu++17)
|
||||
|
||||
if (BUILDING_SDK)
|
||||
add_compile_flags(BOTH
|
||||
-Wall
|
||||
-Werror=all
|
||||
-Wno-error=unused-function
|
||||
-Wno-error=unused-but-set-variable
|
||||
-Wno-error=unused-variable
|
||||
-Wno-error=deprecated-declarations
|
||||
-Wno-error=maybe-uninitialized
|
||||
-Wextra
|
||||
-Werror=frame-larger-than=65536
|
||||
-Wno-unused-parameter
|
||||
-Wno-unused-function
|
||||
-Wno-implicit-fallthrough
|
||||
-Wno-sign-compare
|
||||
-Wno-error=missing-braces
|
||||
)
|
||||
|
||||
add_compile_flags(C -Wno-old-style-declaration)
|
||||
else ()
|
||||
add_compile_flags(BOTH -L"${SDK_ROOT}/include/")
|
||||
endif ()
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
message("")
|
||||
message("Project: ${PROJECT_NAME}")
|
||||
message(" LIST_FILE=${CMAKE_PARENT_LIST_FILE}")
|
||||
message(" TOOLCHAIN=${TOOLCHAIN}")
|
||||
message(" KENDRYTE_IDE=${KENDRYTE_IDE}")
|
||||
message(" BUILDING_SDK=${BUILDING_SDK}")
|
||||
message("")
|
||||
message(" CMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE}")
|
||||
message(" CMAKE_C_COMPILER=${CMAKE_C_COMPILER}")
|
||||
message(" CMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER}")
|
||||
message(" CMAKE_LINKER=${CMAKE_LINKER}")
|
||||
message(" CMAKE_OBJCOPY=${CMAKE_OBJCOPY}")
|
||||
message(" CMAKE_MAKE_PROGRAM=${CMAKE_MAKE_PROGRAM}")
|
||||
message("")
|
||||
message(" CMAKE_C_FLAGS=${CMAKE_C_FLAGS}")
|
||||
message(" CMAKE_CXX_FLAGS=${CMAKE_CXX_FLAGS}")
|
||||
message(" LDFLAGS=${LDFLAGS}")
|
||||
message(" CMAKE_BINARY_DIR=${CMAKE_BINARY_DIR}")
|
||||
message("Makefile created.")
|
||||
message("")
|
||||
message("")
|
|
@ -0,0 +1,59 @@
|
|||
|
||||
message("CMAKE_MAKE_PROGRAM=${CMAKE_MAKE_PROGRAM}")
|
||||
message("_TC_MAKE=${_TC_MAKE}")
|
||||
if (_TC_MAKE)
|
||||
global_set(CMAKE_MAKE_PROGRAM "${_TC_MAKE}")
|
||||
endif()
|
||||
|
||||
if (NOT BUILDING_SDK)
|
||||
if(EXISTS ${SDK_ROOT}/libkendryte.a)
|
||||
header_directories(${SDK_ROOT}/include)
|
||||
add_library(kendryte STATIC IMPORTED)
|
||||
set_property(TARGET kendryte PROPERTY IMPORTED_LOCATION ${SDK_ROOT}/libkendryte.a)
|
||||
else()
|
||||
header_directories(${SDK_ROOT}/lib)
|
||||
add_subdirectory(${SDK_ROOT}/lib SDK)
|
||||
endif()
|
||||
endif ()
|
||||
|
||||
removeDuplicateSubstring(${CMAKE_C_FLAGS} CMAKE_C_FLAGS)
|
||||
removeDuplicateSubstring(${CMAKE_CXX_FLAGS} CMAKE_CXX_FLAGS)
|
||||
|
||||
message("SOURCE_FILES=${SOURCE_FILES}")
|
||||
add_executable(${PROJECT_NAME} ${SOURCE_FILES})
|
||||
# add_dependencies(${PROJECT_NAME} kendryte) # TODO: third_party
|
||||
# target_link_libraries(${PROJECT_NAME} kendryte) # TODO: third_party
|
||||
# link_directories(${CMAKE_BINARY_DIR})
|
||||
|
||||
set_target_properties(${PROJECT_NAME} PROPERTIES LINKER_LANGUAGE C)
|
||||
|
||||
EXECUTE_PROCESS(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crt0.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRT0_OBJ)
|
||||
EXECUTE_PROCESS(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crtbegin.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTBEGIN_OBJ)
|
||||
EXECUTE_PROCESS(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crtend.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTEND_OBJ)
|
||||
EXECUTE_PROCESS(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crti.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTI_OBJ)
|
||||
EXECUTE_PROCESS(COMMAND ${CMAKE_C_COMPILER} -print-file-name=crtn.o OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE CRTN_OBJ)
|
||||
|
||||
set(CMAKE_C_LINK_EXECUTABLE
|
||||
"<CMAKE_C_COMPILER> <FLAGS> <CMAKE_C_LINK_FLAGS> <LINK_FLAGS> ${CRTI_OBJ} ${CRTBEGIN_OBJ} <OBJECTS> ${CRTEND_OBJ} ${CRTN_OBJ} -o <TARGET> <LINK_LIBRARIES>")
|
||||
|
||||
set(CMAKE_CXX_LINK_EXECUTABLE
|
||||
"<CMAKE_CXX_COMPILER> <FLAGS> <CMAKE_CXX_LINK_FLAGS> <LINK_FLAGS> ${CRTI_OBJ} ${CRTBEGIN_OBJ} <OBJECTS> ${CRTEND_OBJ} ${CRTN_OBJ} -o <TARGET> <LINK_LIBRARIES>")
|
||||
|
||||
target_link_libraries(${PROJECT_NAME}
|
||||
-Wl,--start-group
|
||||
m kendryte
|
||||
-Wl,--end-group
|
||||
)
|
||||
|
||||
IF(SUFFIX)
|
||||
SET_TARGET_PROPERTIES(${PROJECT_NAME} PROPERTIES SUFFIX ${SUFFIX})
|
||||
ENDIF()
|
||||
|
||||
# Build target
|
||||
add_custom_command(TARGET ${PROJECT_NAME} POST_BUILD
|
||||
COMMAND ${CMAKE_OBJCOPY} --output-format=binary ${CMAKE_BINARY_DIR}/${PROJECT_NAME}${SUFFIX} ${CMAKE_BINARY_DIR}/${PROJECT_NAME}.bin
|
||||
DEPENDS ${PROJECT_NAME}
|
||||
COMMENT "Generating .bin file ...")
|
||||
|
||||
# show information
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/dump-config.cmake)
|
|
@ -0,0 +1,5 @@
|
|||
### http://www.cmake.org/Bug/view.php?id=9985
|
||||
string(REPLACE "-rdynamic" "" _C_FLAGS "${CMAKE_SHARED_LIBRARY_LINK_C_FLAGS}")
|
||||
string(REPLACE "-rdynamic" "" _CXX_FLAGS "${CMAKE_SHARED_LIBRARY_LINK_CXX_FLAGS}")
|
||||
global_set(CMAKE_SHARED_LIBRARY_LINK_C_FLAGS "${_C_FLAGS}")
|
||||
global_set(CMAKE_SHARED_LIBRARY_LINK_CXX_FLAGS "${_CXX_FLAGS}")
|
|
@ -0,0 +1,74 @@
|
|||
macro(global_set Name Value)
|
||||
# message("set ${Name} to ${Value}" ${ARGN})
|
||||
set(${Name} "${Value}" CACHE STRING "NoDesc" FORCE)
|
||||
endmacro()
|
||||
|
||||
macro(condition_set Name Value)
|
||||
if (NOT ${Name})
|
||||
global_set(${Name} ${Value})
|
||||
else ()
|
||||
# message("exists ${Name} is ${Value}" ${ARGN})
|
||||
endif ()
|
||||
endmacro()
|
||||
|
||||
|
||||
set(SOURCE_FILES "" CACHE STRING "Source Files" FORCE)
|
||||
macro(add_source_files)
|
||||
# message(" + add_source_files ${ARGN}")
|
||||
file(GLOB_RECURSE newlist ${ARGN})
|
||||
|
||||
foreach (filepath ${newlist})
|
||||
string(TOLOWER ${filepath} F)
|
||||
string(TOLOWER ${CMAKE_BINARY_DIR} M)
|
||||
string(FIND ${F} ${M} found)
|
||||
if (NOT found EQUAL 0)
|
||||
set(SOURCE_FILES ${SOURCE_FILES} ${filepath} CACHE STRING "Source Files" FORCE)
|
||||
endif ()
|
||||
endforeach ()
|
||||
endmacro()
|
||||
|
||||
function(JOIN VALUES GLUE OUTPUT)
|
||||
string(REGEX REPLACE "([^\\]|^);" "\\1${GLUE}" _TMP_STR "${VALUES}")
|
||||
string(REGEX REPLACE "[\\](.)" "\\1" _TMP_STR "${_TMP_STR}") #fixes escaping
|
||||
set(${OUTPUT} "${_TMP_STR}" PARENT_SCOPE)
|
||||
endfunction()
|
||||
|
||||
global_set(LDFLAGS "")
|
||||
global_set(CMAKE_EXE_LINKER_FLAGS "")
|
||||
global_set(CMAKE_SHARED_LINKER_FLAGS "")
|
||||
global_set(CMAKE_MODULE_LINKER_FLAGS "")
|
||||
|
||||
function(removeDuplicateSubstring stringIn stringOut)
|
||||
separate_arguments(stringIn)
|
||||
list(REMOVE_DUPLICATES stringIn)
|
||||
string(REPLACE ";" " " stringIn "${stringIn}")
|
||||
set(${stringOut} "${stringIn}" PARENT_SCOPE)
|
||||
endfunction()
|
||||
|
||||
macro(add_compile_flags WHERE)
|
||||
JOIN("${ARGN}" " " STRING_ARGS)
|
||||
if (${WHERE} STREQUAL C)
|
||||
global_set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${STRING_ARGS}")
|
||||
|
||||
elseif (${WHERE} STREQUAL CXX)
|
||||
global_set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${STRING_ARGS}")
|
||||
|
||||
elseif (${WHERE} STREQUAL LD)
|
||||
global_set(LDFLAGS "${LDFLAGS} ${STRING_ARGS}")
|
||||
global_set(CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${STRING_ARGS}")
|
||||
global_set(CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${STRING_ARGS}")
|
||||
global_set(CMAKE_MODULE_LINKER_FLAGS "${CMAKE_MODULE_LINKER_FLAGS} ${STRING_ARGS}")
|
||||
|
||||
elseif (${WHERE} STREQUAL BOTH)
|
||||
add_compile_flags(C ${ARGN})
|
||||
add_compile_flags(CXX ${ARGN})
|
||||
|
||||
elseif (${WHERE} STREQUAL ALL)
|
||||
add_compile_flags(C ${ARGN})
|
||||
add_compile_flags(CXX ${ARGN})
|
||||
add_compile_flags(LD ${ARGN})
|
||||
|
||||
else ()
|
||||
message(FATAL_ERROR "add_compile_flags - only support: C, CXX, BOTH, LD, ALL")
|
||||
endif ()
|
||||
endmacro()
|
|
@ -0,0 +1,12 @@
|
|||
# Add lib headers
|
||||
macro(header_directories parent)
|
||||
file(GLOB_RECURSE newList ${parent}/*.h)
|
||||
set(dir_list "")
|
||||
foreach (file_path ${newList})
|
||||
get_filename_component(dir_path ${file_path} DIRECTORY)
|
||||
set(dir_list ${dir_list} ${dir_path})
|
||||
endforeach ()
|
||||
list(REMOVE_DUPLICATES dir_list)
|
||||
|
||||
include_directories(${dir_list})
|
||||
endmacro()
|
|
@ -0,0 +1,44 @@
|
|||
if (NOT TOOLCHAIN)
|
||||
message(FATAL_ERROR "TOOLCHAIN must be set, to absolute path of kendryte-toolchain dist/bin folder.")
|
||||
endif ()
|
||||
|
||||
if (WIN32)
|
||||
set(EXT ".exe")
|
||||
else ()
|
||||
set(EXT "")
|
||||
endif ()
|
||||
|
||||
message(STATUS "Check for RISCV toolchain ...")
|
||||
|
||||
IF("${TOOLCHAIN}" STREQUAL "")
|
||||
message(STATUS "Using default RISCV toolchain")
|
||||
|
||||
global_set(CMAKE_C_COMPILER "riscv64-unknown-elf-gcc${EXT}")
|
||||
global_set(CMAKE_CXX_COMPILER "riscv64-unknown-elf-g++${EXT}")
|
||||
global_set(CMAKE_LINKER "riscv64-unknown-elf-ld${EXT}")
|
||||
global_set(CMAKE_AR "riscv64-unknown-elf-ar${EXT}")
|
||||
global_set(CMAKE_OBJCOPY "riscv64-unknown-elf-objcopy${EXT}")
|
||||
global_set(CMAKE_SIZE "riscv64-unknown-elf-size${EXT}")
|
||||
global_set(CMAKE_OBJDUMP "riscv64-unknown-elf-objdump${EXT}")
|
||||
ELSE()
|
||||
message(STATUS "Using ${TOOLCHAIN} RISCV toolchain")
|
||||
|
||||
global_set(CMAKE_C_COMPILER "${TOOLCHAIN}/riscv64-unknown-elf-gcc${EXT}")
|
||||
global_set(CMAKE_CXX_COMPILER "${TOOLCHAIN}/riscv64-unknown-elf-g++${EXT}")
|
||||
global_set(CMAKE_LINKER "${TOOLCHAIN}/riscv64-unknown-elf-ld${EXT}")
|
||||
global_set(CMAKE_AR "${TOOLCHAIN}/riscv64-unknown-elf-ar${EXT}")
|
||||
global_set(CMAKE_OBJCOPY "${TOOLCHAIN}/riscv64-unknown-elf-objcopy${EXT}")
|
||||
global_set(CMAKE_SIZE "${TOOLCHAIN}/riscv64-unknown-elf-size${EXT}")
|
||||
global_set(CMAKE_OBJDUMP "${TOOLCHAIN}/riscv64-unknown-elf-objdump${EXT}")
|
||||
ENDIF()
|
||||
|
||||
if (CMAKE_MAKE_PROGRAM)
|
||||
global_set(_TC_MAKE "${CMAKE_MAKE_PROGRAM}")
|
||||
endif()
|
||||
|
||||
get_filename_component(_BIN_DIR "${CMAKE_C_COMPILER}" DIRECTORY)
|
||||
if (NOT "${TOOLCHAIN}" STREQUAL "${_BIN_DIR}" AND NOT "${TOOLCHAIN}" STREQUAL "${_BIN_DIR}/")
|
||||
message("TOOLCHAIN is [${TOOLCHAIN}]")
|
||||
message("_BIN_DIR is [${_BIN_DIR}]")
|
||||
message(WARNING "CMAKE_C_COMPILER is not in kendryte-toolchain dist/bin folder.")
|
||||
endif ()
|
|
@ -0,0 +1,251 @@
|
|||
/*
|
||||
* The MEMORY command describes the location and size of blocks of memory
|
||||
* in the target. You can use it to describe which memory regions may be
|
||||
* used by the linker, and which memory regions it must avoid.
|
||||
*/
|
||||
MEMORY
|
||||
{
|
||||
/*
|
||||
* Memory with CPU cache.
|
||||
*6M CPU SRAM
|
||||
*/
|
||||
ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = (6 * 1024 * 1024)
|
||||
/*
|
||||
* Memory without CPU cache
|
||||
* 6M CPU SRAM
|
||||
*/
|
||||
ram_nocache (wxa!ri) : ORIGIN = 0x40000000, LENGTH = (6 * 1024 * 1024)
|
||||
}
|
||||
|
||||
PROVIDE( _rom_start = ORIGIN(rom) );
|
||||
PROVIDE( _rom_end = ORIGIN(rom) + LENGTH(rom) );
|
||||
PROVIDE( _ram_start = ORIGIN(ram) );
|
||||
PROVIDE( _ram_end = ORIGIN(ram) + LENGTH(ram) );
|
||||
PROVIDE( _io_start = 0x40000000 );
|
||||
PROVIDE( _io_end = _io_start + LENGTH(ram) );
|
||||
PROVIDE( _stack_size = 1 << 15 );
|
||||
|
||||
|
||||
/*
|
||||
* The OUTPUT_ARCH command specifies the machine architecture where the
|
||||
* argument is one of the names used in the Kendryte library.
|
||||
*/
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
|
||||
/*
|
||||
* The ENTRY command specifies the entry point (ie. first instruction to
|
||||
* execute). The symbol _start is defined in crt0.S
|
||||
*/
|
||||
ENTRY(_start)
|
||||
|
||||
/*
|
||||
* The GROUP command is special since the listed archives will be
|
||||
* searched repeatedly until there are no new undefined references. We
|
||||
* need this since -lc depends on -lgloss and -lgloss depends on -lc. I
|
||||
* thought gcc would automatically include -lgcc when needed, but
|
||||
* in this file includes it explicitly here and I was seeing link errors
|
||||
* without it.
|
||||
*/
|
||||
/* GROUP( -lc -lgloss -lgcc ) */
|
||||
|
||||
/*
|
||||
* The linker only pays attention to the PHDRS command when generating
|
||||
* an ELF output file. In other cases, the linker will simply ignore PHDRS.
|
||||
*/
|
||||
PHDRS
|
||||
{
|
||||
ram_ro PT_LOAD;
|
||||
ram_init PT_LOAD;
|
||||
ram PT_NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* This is where we specify how the input sections map to output
|
||||
* sections.
|
||||
*/
|
||||
SECTIONS
|
||||
{
|
||||
/* Program code segment, also known as a text segment */
|
||||
.text :
|
||||
{
|
||||
PROVIDE( _text = ABSOLUTE(.) );
|
||||
/* Initialization code segment */
|
||||
KEEP( *(.text.start) )
|
||||
*(.text.unlikely .text.unlikely.*)
|
||||
*(.text.startup .text.startup.*)
|
||||
/* Normal code segment */
|
||||
*(.text .text.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.gcc_except_table.*)
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _etext = ABSOLUTE(.) );
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
/* Read-only data segment */
|
||||
.rodata :
|
||||
{
|
||||
*(.rdata)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.r.*)
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
. = ALIGN(8);
|
||||
|
||||
/* Init array and fini array */
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
.ctors :
|
||||
{
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
.dtors :
|
||||
{
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
. = ALIGN(8);
|
||||
|
||||
.lalign :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _data_lma = . );
|
||||
} >ram AT>ram :ram_ro
|
||||
|
||||
.dalign :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _data = . );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
. = ALIGN(8);
|
||||
|
||||
/* .data, .sdata and .srodata segment */
|
||||
.data :
|
||||
{
|
||||
/* Writable data segment (.data segment) */
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
/* Have _gp point to middle of sdata/sbss to maximize displacement range */
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _gp = ABSOLUTE(.) + 0x800);
|
||||
/* Writable small data segment (.sdata segment) */
|
||||
*(.sdata .sdata.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
/* Read-only small data segment (.srodata segment) */
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
/* Align _edata to cache line size */
|
||||
. = ALIGN(64);
|
||||
PROVIDE( _edata = ABSOLUTE(.) );
|
||||
} >ram AT>ram :ram_init
|
||||
|
||||
/* .bss and .sbss segment */
|
||||
.bss :
|
||||
{
|
||||
PROVIDE( _bss = ABSOLUTE(.) );
|
||||
/* Writable uninitialized small data segment (.sbss segment)*/
|
||||
*(.sbss .sbss.*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
/* Uninitialized writeable data section (.bss segment)*/
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(8);
|
||||
PROVIDE( _ebss = ABSOLUTE(.) );
|
||||
} >ram AT>ram :ram
|
||||
|
||||
PROVIDE( _tls_data = ABSOLUTE(.) );
|
||||
/*
|
||||
* Thread Local Storage (TLS) are per-thread global variables.
|
||||
* Compilers such as GCC provide a __thread keyword to mark global
|
||||
* variables as per-thread. Support is required in the program loader
|
||||
* and thread creator.
|
||||
*/
|
||||
|
||||
/* Thread-local data segment, .tdata (initialized tls). */
|
||||
.tdata :
|
||||
{
|
||||
KEEP( *(.tdata.begin) )
|
||||
*(.tdata .tdata.*)
|
||||
*(.gnu.linkonce.td.*)
|
||||
KEEP( *(.tdata.end) )
|
||||
} >ram AT>ram :ram
|
||||
|
||||
/* Thread-local bss segment, .tbss (zero-initialized tls). */
|
||||
.tbss :
|
||||
{
|
||||
*(.tbss .tbss.*)
|
||||
*(.gnu.linkonce.tb.*)
|
||||
KEEP( *(.tbss.end) )
|
||||
} >ram AT>ram :ram
|
||||
|
||||
/*
|
||||
* End of uninitalized data segement
|
||||
*
|
||||
* Actually the stack needs 16B alignment, and it won't hurt to also slightly
|
||||
* increase the alignment to 32 or even 64 (cache line size).
|
||||
*
|
||||
* Align _heap_start to cache line size
|
||||
*/
|
||||
. = ALIGN(64);
|
||||
PROVIDE( _end = ABSOLUTE(.) );
|
||||
/* Leave 2 holes for stack & TLS, the size can set in kconfig */
|
||||
PROVIDE( _heap_start = ABSOLUTE(.) + _stack_size * 5 );
|
||||
PROVIDE( _tp0 = (_end + 63) & (-64) );
|
||||
PROVIDE( _tp1 = _tp0 + _stack_size );
|
||||
PROVIDE( _sp0 = _tp0 + _stack_size );
|
||||
PROVIDE( _sp1 = _tp1 + _stack_size );
|
||||
/* Heap end is at the end of memory, the memory size can set in kconfig */
|
||||
PROVIDE( _heap_end = _ram_end );
|
||||
}
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
#project(kendryte_drivers)
|
||||
|
||||
# create driver library
|
||||
FILE(GLOB_RECURSE LIB_SRC_NOASM
|
||||
"${CMAKE_CURRENT_LIST_DIR}/*.h"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/*.hpp"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/*.cpp"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/*.c"
|
||||
)
|
||||
|
||||
FILE(GLOB_RECURSE ASSEMBLY_FILES
|
||||
"${CMAKE_CURRENT_LIST_DIR}/*.s"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/*.S"
|
||||
)
|
||||
SET(LIB_SRC ${LIB_SRC_NOASM} ${ASSEMBLY_FILES})
|
||||
|
||||
include_directories(${CMAKE_CURRENT_LIST_DIR}/drivers/include ${CMAKE_CURRENT_LIST_DIR}/bsp/include)
|
||||
#
|
||||
#HEADER_DIRECTORIES(LIB_HEADERS)
|
||||
#
|
||||
#INCLUDE_DIRECTORIES(${LIB_HEADERS})
|
||||
|
||||
SET_PROPERTY(SOURCE ${ASSEMBLY_FILES} PROPERTY LANGUAGE C)
|
||||
SET_SOURCE_FILES_PROPERTIES(${ASSEMBLY_FILES} PROPERTIES COMPILE_FLAGS "-x assembler-with-cpp -D __riscv64")
|
||||
|
||||
#MESSAGE("CMAKE_C_FLAGS: ${CMAKE_C_FLAGS}")
|
||||
|
||||
ADD_LIBRARY(kendryte STATIC ${LIB_SRC})
|
||||
SET_TARGET_PROPERTIES(kendryte PROPERTIES LINKER_LANGUAGE C)
|
||||
|
||||
# find headers files to INSTALL
|
||||
file(GLOB_RECURSE LIB_HEADERS
|
||||
"../lib/*.h"
|
||||
"../lib/*.hpp"
|
||||
)
|
||||
|
||||
set_target_properties(kendryte PROPERTIES PUBLIC_HEADER "${LIB_HEADERS}")
|
||||
|
||||
# copy .a file and headers
|
||||
install(TARGETS kendryte
|
||||
EXPORT kendryte
|
||||
ARCHIVE
|
||||
DESTINATION ${CMAKE_BINARY_DIR}/archive
|
||||
PUBLIC_HEADER DESTINATION ${CMAKE_BINARY_DIR}/archive/include
|
||||
)
|
|
@ -0,0 +1,25 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <fpioa_cfg.h>
|
||||
|
||||
const fpioa_cfg_t g_fpioa_cfg =
|
||||
{
|
||||
.version = 1,
|
||||
.io_count = FPIOA_NUM_IO,
|
||||
.io_functions =
|
||||
{
|
||||
[0] = FUNC_JTAG_TCLK,
|
||||
}
|
||||
};
|
|
@ -0,0 +1,261 @@
|
|||
# Copyright 2018 Canaan Inc.
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
# include "encoding.h"
|
||||
|
||||
# define LREG ld
|
||||
# define SREG sd
|
||||
# define LFREG fld
|
||||
# define SFREG fsd
|
||||
# define REGBYTES 8
|
||||
# define STKSHIFT 15
|
||||
|
||||
.section .text.start, "ax", @progbits
|
||||
.globl _start
|
||||
_start:
|
||||
j 1f
|
||||
.word 0xdeadbeef
|
||||
1:
|
||||
csrw mideleg, 0
|
||||
csrw medeleg, 0
|
||||
csrw mie, 0
|
||||
csrw mip, 0
|
||||
la t0, trap_entry
|
||||
csrw mtvec, t0
|
||||
|
||||
# enable FPU and accelerator if present
|
||||
li t0, MSTATUS_FS
|
||||
csrs mstatus, t0
|
||||
|
||||
# initialize global pointer
|
||||
la gp, _gp
|
||||
|
||||
la tp, _end + 63
|
||||
and tp, tp, -64
|
||||
|
||||
# get core id
|
||||
csrr a0, mhartid
|
||||
|
||||
sll a2, a0, STKSHIFT
|
||||
add tp, tp, a2
|
||||
li t0, ((1 << STKSHIFT) * 3)
|
||||
add sp, t0, tp
|
||||
|
||||
j _init_bsp
|
||||
|
||||
.globl trap_entry
|
||||
.type trap_entry, @function
|
||||
.align 2
|
||||
trap_entry:
|
||||
addi sp, sp, -REGBYTES
|
||||
SREG t0, 0x0(sp)
|
||||
csrr t0, mcause
|
||||
bgez t0, .handle_other
|
||||
# Test soft interrupt
|
||||
slli t0, t0, 1
|
||||
addi t0, t0, -(IRQ_M_SOFT << 1)
|
||||
bnez t0, .handle_other
|
||||
# Interupt is soft interrupt
|
||||
# Get event
|
||||
addi sp, sp, -REGBYTES
|
||||
SREG t1, 0x0(sp)
|
||||
la t0, xCoreSyncEvents
|
||||
csrr t1, mhartid
|
||||
slli t1, t1, 3
|
||||
add t0, t0, t1
|
||||
LREG t1, 0x0(sp)
|
||||
addi sp, sp, REGBYTES
|
||||
# Test ContextSwitch event
|
||||
ld t0, 0x0(t0)
|
||||
addi t0, t0, -2 # CORE_SYNC_CONTEXT_SWITCH
|
||||
bnez t0, .handle_other
|
||||
|
||||
LREG t0, 0x0(sp)
|
||||
addi sp, sp, REGBYTES
|
||||
# Do not use jal here
|
||||
j xPortSysTickInt
|
||||
mret
|
||||
.handle_other:
|
||||
LREG t0, 0x0(sp)
|
||||
addi sp, sp, REGBYTES
|
||||
addi sp, sp, -64*REGBYTES
|
||||
|
||||
SREG x1, 1*REGBYTES(sp)
|
||||
SREG x2, 2*REGBYTES(sp)
|
||||
SREG x3, 3*REGBYTES(sp)
|
||||
SREG x4, 4*REGBYTES(sp)
|
||||
SREG x5, 5*REGBYTES(sp)
|
||||
SREG x6, 6*REGBYTES(sp)
|
||||
SREG x7, 7*REGBYTES(sp)
|
||||
SREG x8, 8*REGBYTES(sp)
|
||||
SREG x9, 9*REGBYTES(sp)
|
||||
SREG x10, 10*REGBYTES(sp)
|
||||
SREG x11, 11*REGBYTES(sp)
|
||||
SREG x12, 12*REGBYTES(sp)
|
||||
SREG x13, 13*REGBYTES(sp)
|
||||
SREG x14, 14*REGBYTES(sp)
|
||||
SREG x15, 15*REGBYTES(sp)
|
||||
SREG x16, 16*REGBYTES(sp)
|
||||
SREG x17, 17*REGBYTES(sp)
|
||||
SREG x18, 18*REGBYTES(sp)
|
||||
SREG x19, 19*REGBYTES(sp)
|
||||
SREG x20, 20*REGBYTES(sp)
|
||||
SREG x21, 21*REGBYTES(sp)
|
||||
SREG x22, 22*REGBYTES(sp)
|
||||
SREG x23, 23*REGBYTES(sp)
|
||||
SREG x24, 24*REGBYTES(sp)
|
||||
SREG x25, 25*REGBYTES(sp)
|
||||
SREG x26, 26*REGBYTES(sp)
|
||||
SREG x27, 27*REGBYTES(sp)
|
||||
SREG x28, 28*REGBYTES(sp)
|
||||
SREG x29, 29*REGBYTES(sp)
|
||||
SREG x30, 30*REGBYTES(sp)
|
||||
SREG x31, 31*REGBYTES(sp)
|
||||
|
||||
SFREG f0, ( 0 + 32)*REGBYTES(sp)
|
||||
SFREG f1, ( 1 + 32)*REGBYTES(sp)
|
||||
SFREG f2, ( 2 + 32)*REGBYTES(sp)
|
||||
SFREG f3, ( 3 + 32)*REGBYTES(sp)
|
||||
SFREG f4, ( 4 + 32)*REGBYTES(sp)
|
||||
SFREG f5, ( 5 + 32)*REGBYTES(sp)
|
||||
SFREG f6, ( 6 + 32)*REGBYTES(sp)
|
||||
SFREG f7, ( 7 + 32)*REGBYTES(sp)
|
||||
SFREG f8, ( 8 + 32)*REGBYTES(sp)
|
||||
SFREG f9, ( 9 + 32)*REGBYTES(sp)
|
||||
SFREG f10,( 10 + 32)*REGBYTES(sp)
|
||||
SFREG f11,( 11 + 32)*REGBYTES(sp)
|
||||
SFREG f12,( 12 + 32)*REGBYTES(sp)
|
||||
SFREG f13,( 13 + 32)*REGBYTES(sp)
|
||||
SFREG f14,( 14 + 32)*REGBYTES(sp)
|
||||
SFREG f15,( 15 + 32)*REGBYTES(sp)
|
||||
SFREG f16,( 16 + 32)*REGBYTES(sp)
|
||||
SFREG f17,( 17 + 32)*REGBYTES(sp)
|
||||
SFREG f18,( 18 + 32)*REGBYTES(sp)
|
||||
SFREG f19,( 19 + 32)*REGBYTES(sp)
|
||||
SFREG f20,( 20 + 32)*REGBYTES(sp)
|
||||
SFREG f21,( 21 + 32)*REGBYTES(sp)
|
||||
SFREG f22,( 22 + 32)*REGBYTES(sp)
|
||||
SFREG f23,( 23 + 32)*REGBYTES(sp)
|
||||
SFREG f24,( 24 + 32)*REGBYTES(sp)
|
||||
SFREG f25,( 25 + 32)*REGBYTES(sp)
|
||||
SFREG f26,( 26 + 32)*REGBYTES(sp)
|
||||
SFREG f27,( 27 + 32)*REGBYTES(sp)
|
||||
SFREG f28,( 28 + 32)*REGBYTES(sp)
|
||||
SFREG f29,( 29 + 32)*REGBYTES(sp)
|
||||
SFREG f30,( 30 + 32)*REGBYTES(sp)
|
||||
SFREG f31,( 31 + 32)*REGBYTES(sp)
|
||||
|
||||
csrr a0, mcause
|
||||
csrr a1, mepc
|
||||
mv a2, sp
|
||||
add a3, sp, 32*REGBYTES
|
||||
bgez a0, .handle_syscall
|
||||
.handle_irq:
|
||||
jal handle_irq
|
||||
j .restore
|
||||
.handle_syscall:
|
||||
jal handle_syscall
|
||||
.restore:
|
||||
# Remain in M-mode after eret
|
||||
li t0, MSTATUS_MPP
|
||||
csrs mstatus, t0
|
||||
csrw mepc, a0
|
||||
LREG x1, 1*REGBYTES(sp)
|
||||
LREG x2, 2*REGBYTES(sp)
|
||||
LREG x3, 3*REGBYTES(sp)
|
||||
LREG x4, 4*REGBYTES(sp)
|
||||
LREG x5, 5*REGBYTES(sp)
|
||||
LREG x6, 6*REGBYTES(sp)
|
||||
LREG x7, 7*REGBYTES(sp)
|
||||
LREG x8, 8*REGBYTES(sp)
|
||||
LREG x9, 9*REGBYTES(sp)
|
||||
LREG x10, 10*REGBYTES(sp)
|
||||
LREG x11, 11*REGBYTES(sp)
|
||||
LREG x12, 12*REGBYTES(sp)
|
||||
LREG x13, 13*REGBYTES(sp)
|
||||
LREG x14, 14*REGBYTES(sp)
|
||||
LREG x15, 15*REGBYTES(sp)
|
||||
LREG x16, 16*REGBYTES(sp)
|
||||
LREG x17, 17*REGBYTES(sp)
|
||||
LREG x18, 18*REGBYTES(sp)
|
||||
LREG x19, 19*REGBYTES(sp)
|
||||
LREG x20, 20*REGBYTES(sp)
|
||||
LREG x21, 21*REGBYTES(sp)
|
||||
LREG x22, 22*REGBYTES(sp)
|
||||
LREG x23, 23*REGBYTES(sp)
|
||||
LREG x24, 24*REGBYTES(sp)
|
||||
LREG x25, 25*REGBYTES(sp)
|
||||
LREG x26, 26*REGBYTES(sp)
|
||||
LREG x27, 27*REGBYTES(sp)
|
||||
LREG x28, 28*REGBYTES(sp)
|
||||
LREG x29, 29*REGBYTES(sp)
|
||||
LREG x30, 30*REGBYTES(sp)
|
||||
LREG x31, 31*REGBYTES(sp)
|
||||
|
||||
LFREG f0, ( 0 + 32)*REGBYTES(sp)
|
||||
LFREG f1, ( 1 + 32)*REGBYTES(sp)
|
||||
LFREG f2, ( 2 + 32)*REGBYTES(sp)
|
||||
LFREG f3, ( 3 + 32)*REGBYTES(sp)
|
||||
LFREG f4, ( 4 + 32)*REGBYTES(sp)
|
||||
LFREG f5, ( 5 + 32)*REGBYTES(sp)
|
||||
LFREG f6, ( 6 + 32)*REGBYTES(sp)
|
||||
LFREG f7, ( 7 + 32)*REGBYTES(sp)
|
||||
LFREG f8, ( 8 + 32)*REGBYTES(sp)
|
||||
LFREG f9, ( 9 + 32)*REGBYTES(sp)
|
||||
LFREG f10,( 10 + 32)*REGBYTES(sp)
|
||||
LFREG f11,( 11 + 32)*REGBYTES(sp)
|
||||
LFREG f12,( 12 + 32)*REGBYTES(sp)
|
||||
LFREG f13,( 13 + 32)*REGBYTES(sp)
|
||||
LFREG f14,( 14 + 32)*REGBYTES(sp)
|
||||
LFREG f15,( 15 + 32)*REGBYTES(sp)
|
||||
LFREG f16,( 16 + 32)*REGBYTES(sp)
|
||||
LFREG f17,( 17 + 32)*REGBYTES(sp)
|
||||
LFREG f18,( 18 + 32)*REGBYTES(sp)
|
||||
LFREG f19,( 19 + 32)*REGBYTES(sp)
|
||||
LFREG f20,( 20 + 32)*REGBYTES(sp)
|
||||
LFREG f21,( 21 + 32)*REGBYTES(sp)
|
||||
LFREG f22,( 22 + 32)*REGBYTES(sp)
|
||||
LFREG f23,( 23 + 32)*REGBYTES(sp)
|
||||
LFREG f24,( 24 + 32)*REGBYTES(sp)
|
||||
LFREG f25,( 25 + 32)*REGBYTES(sp)
|
||||
LFREG f26,( 26 + 32)*REGBYTES(sp)
|
||||
LFREG f27,( 27 + 32)*REGBYTES(sp)
|
||||
LFREG f28,( 28 + 32)*REGBYTES(sp)
|
||||
LFREG f29,( 29 + 32)*REGBYTES(sp)
|
||||
LFREG f30,( 30 + 32)*REGBYTES(sp)
|
||||
LFREG f31,( 31 + 32)*REGBYTES(sp)
|
||||
|
||||
addi sp, sp, 64*REGBYTES
|
||||
mret
|
||||
|
||||
.global _init
|
||||
.type _init, @function
|
||||
.global _fini
|
||||
.type _fini, @function
|
||||
_init:
|
||||
_fini:
|
||||
ret
|
||||
.size _init, .-_init
|
||||
.size _fini, .-_fini
|
||||
|
||||
.section ".tdata.begin"
|
||||
.globl _tdata_begin
|
||||
_tdata_begin:
|
||||
|
||||
.section ".tdata.end"
|
||||
.globl _tdata_end
|
||||
_tdata_end:
|
||||
|
||||
.section ".tbss.end"
|
||||
.globl _tbss_end
|
||||
_tbss_end:
|
|
@ -0,0 +1,542 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <aes.h>
|
||||
#include <driver.h>
|
||||
#include <hal.h>
|
||||
#include <io.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
|
||||
#define AES_USE_DMA 1
|
||||
#define AES_BASE_ADDR (0x50450000)
|
||||
#define COMMON_ENTRY \
|
||||
aes_dev_data* data = (aes_dev_data*)userdata; \
|
||||
volatile aes_t* aes = (volatile aes_t*)data->base_addr; \
|
||||
(void)aes;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uintptr_t base_addr;
|
||||
SemaphoreHandle_t free_mutex;
|
||||
|
||||
struct
|
||||
{
|
||||
uint32_t aes_hardware_tag[4];
|
||||
};
|
||||
} aes_dev_data;
|
||||
|
||||
static void aes_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_AES);
|
||||
sysctl_reset(SYSCTL_RESET_AES);
|
||||
data->free_mutex = xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
static int aes_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void aes_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void entry_exclusive(aes_dev_data* data)
|
||||
{
|
||||
configASSERT(xSemaphoreTake(data->free_mutex, portMAX_DELAY) == pdTRUE);
|
||||
}
|
||||
|
||||
static void exit_exclusive(aes_dev_data* data)
|
||||
{
|
||||
xSemaphoreGive(data->free_mutex);
|
||||
}
|
||||
|
||||
static int os_aes_write_aad(uint32_t aad_data, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
aes->aes_aad_data = aad_data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int os_aes_write_text(uint32_t text_data, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
aes->aes_text_data = text_data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int os_aes_write_tag(uint32_t* tag, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
aes->gcm_in_tag[0] = tag[3];
|
||||
aes->gcm_in_tag[1] = tag[2];
|
||||
aes->gcm_in_tag[2] = tag[1];
|
||||
aes->gcm_in_tag[3] = tag[0];
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int os_get_data_in_flag(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
/* data can in flag 1: data ready 0: data not ready */
|
||||
return aes->data_in_flag;
|
||||
}
|
||||
|
||||
static int os_get_data_out_flag(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
/* data can output flag 1: data ready 0: data not ready */
|
||||
return aes->data_out_flag;
|
||||
}
|
||||
|
||||
static int os_get_tag_in_flag(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
/* data can output flag 1: data ready 0: data not ready */
|
||||
return aes->tag_in_flag;
|
||||
}
|
||||
|
||||
static uint32_t os_read_out_data(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
return aes->aes_out_data;
|
||||
}
|
||||
|
||||
static int os_aes_check_tag(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
return aes->tag_chk;
|
||||
}
|
||||
|
||||
static int os_aes_get_tag(uint8_t* l_tag, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
uint32_t u32tag;
|
||||
uint8_t i = 0;
|
||||
|
||||
u32tag = aes->gcm_out_tag[3];
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag)&0xff);
|
||||
|
||||
u32tag = aes->gcm_out_tag[2];
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag)&0xff);
|
||||
|
||||
u32tag = aes->gcm_out_tag[1];
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag)&0xff);
|
||||
|
||||
u32tag = aes->gcm_out_tag[0];
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 24) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 16) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag >> 8) & 0xff);
|
||||
l_tag[i++] = (uint8_t)((u32tag)&0xff);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int os_aes_clear_chk_tag(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
aes->tag_clear = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int os_check_tag(uint32_t* aes_gcm_tag, void* userdata)
|
||||
{
|
||||
while (!os_get_tag_in_flag(userdata))
|
||||
;
|
||||
os_aes_write_tag(aes_gcm_tag, userdata);
|
||||
while (!os_aes_check_tag(userdata))
|
||||
;
|
||||
if (os_aes_check_tag(userdata) == 2)
|
||||
{
|
||||
os_aes_clear_chk_tag(userdata);
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
os_aes_clear_chk_tag(userdata);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static int os_aes_init(uint8_t* key_addr, uint8_t key_length, uint8_t* aes_iv,
|
||||
uint8_t iv_length, uint8_t* aes_aad, aes_cipher_mod cipher_mod, aes_encrypt_sel encrypt_sel,
|
||||
uint32_t add_size, uint32_t data_size, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
int i, remainder, num, cnt;
|
||||
uint32_t u32data;
|
||||
uint8_t u8data[4] = {0};
|
||||
|
||||
if ((cipher_mod == AES_CIPHER_ECB) || (cipher_mod == AES_CIPHER_CBC))
|
||||
data_size = ((data_size + 15) / 16) * 16;
|
||||
aes->aes_endian |= 1;
|
||||
|
||||
/* write key Low byte alignment */
|
||||
num = key_length / 4;
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
if (i < 4)
|
||||
aes->aes_key[i] = *((uint32_t*)(&key_addr[key_length - (4 * i) - 4]));
|
||||
else
|
||||
aes->aes_key_ext[i - 4] = *((uint32_t*)(&key_addr[key_length - (4 * i) - 4]));
|
||||
}
|
||||
remainder = key_length % 4;
|
||||
if (remainder)
|
||||
{
|
||||
switch (remainder)
|
||||
{
|
||||
case 1:
|
||||
u8data[0] = key_addr[0];
|
||||
break;
|
||||
case 2:
|
||||
u8data[0] = key_addr[0];
|
||||
u8data[1] = key_addr[1];
|
||||
break;
|
||||
case 3:
|
||||
u8data[0] = key_addr[0];
|
||||
u8data[1] = key_addr[1];
|
||||
u8data[2] = key_addr[2];
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
if (num < 4)
|
||||
aes->aes_key[num] = *((uint32_t*)(&u8data[0]));
|
||||
else
|
||||
aes->aes_key_ext[num - 4] = *((uint32_t*)(&u8data[0]));
|
||||
}
|
||||
|
||||
/* write iv Low byte alignment */
|
||||
num = iv_length / 4;
|
||||
for (i = 0; i < num; i++)
|
||||
aes->aes_iv[i] = *((uint32_t*)(&aes_iv[iv_length - (4 * i) - 4]));
|
||||
remainder = iv_length % 4;
|
||||
if (remainder)
|
||||
{
|
||||
switch (remainder)
|
||||
{
|
||||
case 1:
|
||||
u8data[0] = aes_iv[0];
|
||||
break;
|
||||
case 2:
|
||||
u8data[0] = aes_iv[0];
|
||||
u8data[1] = aes_iv[1];
|
||||
break;
|
||||
case 3:
|
||||
u8data[0] = aes_iv[0];
|
||||
u8data[1] = aes_iv[1];
|
||||
u8data[2] = aes_iv[2];
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
aes->aes_iv[num] = *((uint32_t*)(&u8data[0]));
|
||||
}
|
||||
aes->mode_ctl.kmode = key_length / 8 - 2; /* 00:AES_128 01:AES_192 10:AES_256 11:RESERVED */
|
||||
aes->mode_ctl.cipher_mode = cipher_mod;
|
||||
|
||||
/*
|
||||
* [1:0],set the first bit and second bit 00:ecb; 01:cbc;
|
||||
* 10,11:AES_CIPHER_GCM
|
||||
*/
|
||||
aes->encrypt_sel = encrypt_sel;
|
||||
aes->gb_aad_end_adr = add_size - 1;
|
||||
aes->gb_pc_end_adr = data_size - 1;
|
||||
aes->gb_aes_en |= 1;
|
||||
|
||||
/* write aad */
|
||||
if (cipher_mod == AES_CIPHER_GCM)
|
||||
{
|
||||
num = add_size / 4;
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
u32data = *((uint32_t*)(aes_aad + i * 4));
|
||||
while (!os_get_data_in_flag(userdata))
|
||||
;
|
||||
os_aes_write_aad(u32data, userdata);
|
||||
}
|
||||
cnt = 4 * num;
|
||||
remainder = add_size % 4;
|
||||
if (remainder)
|
||||
{
|
||||
switch (remainder)
|
||||
{
|
||||
case 1:
|
||||
u8data[0] = aes_aad[cnt];
|
||||
break;
|
||||
case 2:
|
||||
u8data[0] = aes_aad[cnt];
|
||||
u8data[1] = aes_aad[cnt + 1];
|
||||
break;
|
||||
case 3:
|
||||
u8data[0] = aes_aad[cnt];
|
||||
u8data[1] = aes_aad[cnt + 1];
|
||||
u8data[2] = aes_aad[cnt + 2];
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
u32data = *((uint32_t*)(&u8data[0]));
|
||||
while (!os_get_data_in_flag(userdata))
|
||||
;
|
||||
os_aes_write_aad(u32data, userdata);
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int aes_process_less_80_bytes(uint8_t* aes_in_data,
|
||||
uint8_t* aes_out_data,
|
||||
uint32_t data_size,
|
||||
aes_cipher_mod cipher_mod,
|
||||
void* userdata)
|
||||
{
|
||||
int padding_size;
|
||||
int num, i, remainder, cnt;
|
||||
uint32_t u32data;
|
||||
uint8_t u8data[4] = {0};
|
||||
|
||||
/* Fill 128 bits (16byte) */
|
||||
padding_size = ((data_size + 15) / 16) * 16;
|
||||
|
||||
/* write text */
|
||||
num = data_size / 4;
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
u32data = *((uint32_t*)(&aes_in_data[i * 4]));
|
||||
while (!os_get_data_in_flag(userdata))
|
||||
;
|
||||
os_aes_write_text(u32data, userdata);
|
||||
}
|
||||
cnt = 4 * num;
|
||||
remainder = data_size % 4;
|
||||
if (remainder)
|
||||
{
|
||||
switch (remainder)
|
||||
{
|
||||
case 1:
|
||||
u8data[0] = aes_in_data[cnt];
|
||||
break;
|
||||
case 2:
|
||||
u8data[0] = aes_in_data[cnt];
|
||||
u8data[1] = aes_in_data[cnt + 1];
|
||||
break;
|
||||
case 3:
|
||||
u8data[0] = aes_in_data[cnt];
|
||||
u8data[1] = aes_in_data[cnt + 1];
|
||||
u8data[2] = aes_in_data[cnt + 2];
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
u32data = *((uint32_t*)(&u8data[0]));
|
||||
while (!os_get_data_in_flag(userdata))
|
||||
;
|
||||
os_aes_write_text(u32data, userdata);
|
||||
}
|
||||
|
||||
if ((cipher_mod == AES_CIPHER_ECB) || (cipher_mod == AES_CIPHER_CBC))
|
||||
{
|
||||
/* use 0 to Fill 128 bits */
|
||||
num = (padding_size - data_size) / 4;
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
while (!os_get_data_in_flag(userdata))
|
||||
;
|
||||
os_aes_write_text(0, userdata);
|
||||
}
|
||||
|
||||
/* get data */
|
||||
num = padding_size / 4;
|
||||
}
|
||||
|
||||
/* get data */
|
||||
for (i = 0; i < num; i++)
|
||||
{
|
||||
while (!os_get_data_out_flag(userdata))
|
||||
;
|
||||
*((uint32_t*)(&aes_out_data[i * 4])) = os_read_out_data(userdata);
|
||||
}
|
||||
|
||||
if ((cipher_mod == AES_CIPHER_GCM) && (remainder))
|
||||
{
|
||||
while (!os_get_data_out_flag(userdata))
|
||||
;
|
||||
|
||||
*((uint32_t*)(&u8data[0])) = os_read_out_data(userdata);
|
||||
switch (remainder)
|
||||
{
|
||||
case 1:
|
||||
aes_out_data[num * 4] = u8data[0];
|
||||
break;
|
||||
case 2:
|
||||
aes_out_data[num * 4] = u8data[0];
|
||||
aes_out_data[(i * 4) + 1] = u8data[1];
|
||||
break;
|
||||
case 3:
|
||||
aes_out_data[num * 4] = u8data[0];
|
||||
aes_out_data[(i * 4) + 1] = u8data[1];
|
||||
aes_out_data[(i * 4) + 2] = u8data[2];
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int os_aes_process(uint8_t* aes_in_data,
|
||||
uint8_t* aes_out_data,
|
||||
uint32_t data_size,
|
||||
aes_cipher_mod cipher_mod,
|
||||
void* userdata)
|
||||
{
|
||||
|
||||
uint32_t i, temp_size;
|
||||
|
||||
i = 0;
|
||||
if (data_size >= 80)
|
||||
{
|
||||
for (i = 0; i < (data_size / 80); i++)
|
||||
aes_process_less_80_bytes(&aes_in_data[i * 80], &aes_out_data[i * 80], 80, cipher_mod, userdata);
|
||||
}
|
||||
temp_size = data_size % 80;
|
||||
if (temp_size)
|
||||
aes_process_less_80_bytes(&aes_in_data[i * 80], &aes_out_data[i * 80], temp_size, cipher_mod, userdata);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void aes_decrypt(aes_parameter* aes_param, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(aes_param->key_length == AES_128 || aes_param->key_length == AES_192 || aes_param->key_length == AES_256);
|
||||
|
||||
entry_exclusive(data);
|
||||
os_aes_init(aes_param->key_addr, aes_param->key_length, aes_param->gcm_iv, aes_param->iv_length, aes_param->aes_aad,
|
||||
aes_param->cipher_mod, AES_MODE_DECRYPTION, aes_param->add_size, aes_param->data_size, userdata);
|
||||
|
||||
int padding_size = aes_param->data_size;
|
||||
if (aes_param->cipher_mod == AES_CIPHER_CBC || aes_param->cipher_mod == AES_CIPHER_ECB)
|
||||
{
|
||||
padding_size = ((padding_size + 15) / 16) * 16;
|
||||
}
|
||||
|
||||
#if (AES_USE_DMA == 1)
|
||||
uint8_t* padding_buffer = NULL;
|
||||
padding_buffer = (uint8_t*)malloc(padding_size * sizeof(uint8_t));
|
||||
memset(padding_buffer, 0, padding_size);
|
||||
memcpy(padding_buffer, aes_param->aes_in_data, aes_param->data_size);
|
||||
|
||||
uintptr_t aes_write = dma_open_free();
|
||||
uintptr_t aes_read = dma_open_free();
|
||||
|
||||
dma_set_select_request(aes_read, SYSCTL_DMA_SELECT_AES_REQ);
|
||||
|
||||
SemaphoreHandle_t event_read = xSemaphoreCreateBinary(), event_write = xSemaphoreCreateBinary();
|
||||
|
||||
dma_transmit_async(aes_read, &aes->aes_out_data, aes_param->aes_out_data, 0, 1, sizeof(uint32_t), padding_size >> 2, 4, event_read);
|
||||
dma_transmit_async(aes_write, aes_param->aes_in_data, &aes->aes_text_data, 1, 0, sizeof(uint32_t), padding_size >> 2, 4, event_write);
|
||||
aes->dma_sel = 1;
|
||||
|
||||
configASSERT(xSemaphoreTake(event_read, portMAX_DELAY) == pdTRUE && xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
dma_close(aes_write);
|
||||
dma_close(aes_read);
|
||||
vSemaphoreDelete(event_read);
|
||||
vSemaphoreDelete(event_write);
|
||||
#else
|
||||
os_aes_process(aes_param->aes_in_data, aes_param->aes_out_data, padding_size, aes_param->cipher_mod, userdata);
|
||||
#endif
|
||||
if (aes_param->cipher_mod == AES_CIPHER_GCM)
|
||||
{
|
||||
os_aes_get_tag(aes_param->tag, userdata);
|
||||
os_check_tag(data->aes_hardware_tag, userdata); /* haredware need this */
|
||||
}
|
||||
#if (AES_USE_DMA == 1)
|
||||
free(padding_buffer);
|
||||
#endif
|
||||
exit_exclusive(data);
|
||||
}
|
||||
|
||||
static void aes_encrypt(aes_parameter* aes_param, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(aes_param->key_length == AES_128 || aes_param->key_length == AES_192 || aes_param->key_length == AES_256);
|
||||
|
||||
entry_exclusive(data);
|
||||
os_aes_init(aes_param->key_addr, aes_param->key_length, aes_param->gcm_iv, aes_param->iv_length, aes_param->aes_aad,
|
||||
aes_param->cipher_mod, AES_MODE_ENCRYPTION, aes_param->add_size, aes_param->data_size, userdata);
|
||||
|
||||
int padding_size = aes_param->data_size;
|
||||
#if (AES_USE_DMA == 1)
|
||||
uint8_t* padding_buffer = NULL;
|
||||
if (aes_param->cipher_mod == AES_CIPHER_CBC || aes_param->cipher_mod == AES_CIPHER_ECB)
|
||||
{
|
||||
padding_size = ((padding_size + 15) / 16) * 16;
|
||||
}
|
||||
padding_buffer = (uint8_t*)malloc(padding_size * sizeof(uint8_t));
|
||||
memset(padding_buffer, 0, padding_size);
|
||||
memcpy(padding_buffer, aes_param->aes_in_data, aes_param->data_size);
|
||||
|
||||
uintptr_t aes_read = dma_open_free();
|
||||
uintptr_t aes_write = dma_open_free();
|
||||
|
||||
dma_set_select_request(aes_read, SYSCTL_DMA_SELECT_AES_REQ);
|
||||
|
||||
SemaphoreHandle_t event_read = xSemaphoreCreateBinary(), event_write = xSemaphoreCreateBinary();
|
||||
aes->dma_sel = 1;
|
||||
dma_transmit_async(aes_read, &aes->aes_out_data, aes_param->aes_out_data, 0, 1, sizeof(uint32_t), padding_size >> 2, 4, event_read);
|
||||
dma_transmit_async(aes_write, padding_buffer, &aes->aes_text_data, 1, 0, sizeof(uint32_t), padding_size >> 2, 4, event_write);
|
||||
|
||||
configASSERT(xSemaphoreTake(event_read, portMAX_DELAY) == pdTRUE && xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
dma_close(aes_write);
|
||||
dma_close(aes_read);
|
||||
vSemaphoreDelete(event_read);
|
||||
vSemaphoreDelete(event_write);
|
||||
#else
|
||||
os_aes_process(aes_param->aes_in_data, aes_param->aes_out_data, aes_param->data_size, aes_param->cipher_mod, userdata);
|
||||
#endif
|
||||
if (aes_param->cipher_mod == AES_CIPHER_GCM)
|
||||
{
|
||||
os_aes_get_tag(aes_param->tag, userdata);
|
||||
os_check_tag(data->aes_hardware_tag, userdata); /* haredware need this */
|
||||
}
|
||||
#if (AES_USE_DMA == 1)
|
||||
free(padding_buffer);
|
||||
#endif
|
||||
exit_exclusive(data);
|
||||
}
|
||||
|
||||
static aes_dev_data dev0_data = {AES_BASE_ADDR, 0, {{0}}};
|
||||
|
||||
const aes_driver_t g_aes_driver_aes0 = {{&dev0_data, aes_install, aes_open, aes_close}, aes_decrypt, aes_encrypt};
|
|
@ -0,0 +1,666 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <atomic.h>
|
||||
#include <dmac.h>
|
||||
#include <driver.h>
|
||||
#include <hal.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
#include <task.h>
|
||||
|
||||
/* DMAC */
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
dmac_data* data = (dmac_data*)userdata; \
|
||||
volatile struct dmac_t* dmac = (volatile struct dmac_t*)data->base_addr;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uintptr_t base_addr;
|
||||
int32_t axi_master1_use;
|
||||
int32_t axi_master2_use;
|
||||
} dmac_data;
|
||||
|
||||
static void dmac_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint64_t tmp;
|
||||
union dmac_commonreg_intclear_u intclear;
|
||||
union dmac_cfg_u dmac_cfg;
|
||||
union dmac_reset_u dmac_reset;
|
||||
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_DMA);
|
||||
|
||||
dmac_reset.data = readq(&dmac->reset);
|
||||
dmac_reset.reset.rst = 1;
|
||||
writeq(dmac_reset.data, &dmac->reset);
|
||||
while (dmac_reset.reset.rst)
|
||||
dmac_reset.data = readq(&dmac->reset);
|
||||
|
||||
intclear.data = readq(&dmac->com_intclear);
|
||||
intclear.com_intclear.cear_slvif_dec_err_intstat = 1;
|
||||
intclear.com_intclear.clear_slvif_wr2ro_err_intstat = 1;
|
||||
intclear.com_intclear.clear_slvif_rd2wo_err_intstat = 1;
|
||||
intclear.com_intclear.clear_slvif_wronhold_err_intstat = 1;
|
||||
intclear.com_intclear.clear_slvif_undefinedreg_dec_err_intstat = 1;
|
||||
writeq(intclear.data, &dmac->com_intclear);
|
||||
|
||||
dmac_cfg.data = readq(&dmac->cfg);
|
||||
dmac_cfg.cfg.dmac_en = 0;
|
||||
dmac_cfg.cfg.int_en = 0;
|
||||
writeq(dmac_cfg.data, &dmac->cfg);
|
||||
|
||||
while (readq(&dmac->cfg))
|
||||
;
|
||||
|
||||
tmp = readq(&dmac->chen);
|
||||
tmp &= ~0xf;
|
||||
writeq(tmp, &dmac->chen);
|
||||
|
||||
dmac_cfg.data = readq(&dmac->cfg);
|
||||
dmac_cfg.cfg.dmac_en = 1;
|
||||
dmac_cfg.cfg.int_en = 1;
|
||||
writeq(dmac_cfg.data, &dmac->cfg);
|
||||
}
|
||||
|
||||
static int dmac_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void dmac_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static uint32_t add_lru_axi_master(dmac_data* data)
|
||||
{
|
||||
uint32_t axi1 = atomic_read(&data->axi_master1_use);
|
||||
uint32_t axi2 = atomic_read(&data->axi_master2_use);
|
||||
|
||||
if (axi1 < axi2)
|
||||
{
|
||||
atomic_add(&data->axi_master1_use, 1);
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
atomic_add(&data->axi_master2_use, 1);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
static void release_axi_master(dmac_data* data, uint32_t axi)
|
||||
{
|
||||
if (axi == 0)
|
||||
atomic_add(&data->axi_master1_use, -1);
|
||||
else
|
||||
atomic_add(&data->axi_master2_use, -1);
|
||||
}
|
||||
|
||||
static dmac_data dev0_data = {DMAC_BASE_ADDR, 0, 0};
|
||||
|
||||
const dmac_driver_t g_dmac_driver_dmac0 = {{&dev0_data, dmac_install, dmac_open, dmac_close}};
|
||||
|
||||
/* DMA Channel */
|
||||
|
||||
#define MAX_PING_PONG_SRCS 4
|
||||
#define C_COMMON_ENTRY \
|
||||
dma_data* data = (dma_data*)userdata; \
|
||||
dmac_data* dmacdata = data->dmac_data; \
|
||||
volatile struct dmac_t* dmac = (volatile struct dmac_t*)dmacdata->base_addr; \
|
||||
(void)dmac; \
|
||||
volatile struct dmac_channel_t* dma = (volatile struct dmac_channel_t*)dmac->channel + data->channel; \
|
||||
(void)dma;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
dmac_data* dmac_data;
|
||||
size_t channel;
|
||||
int used;
|
||||
|
||||
struct
|
||||
{
|
||||
SemaphoreHandle_t completion_event;
|
||||
uint32_t axi_master;
|
||||
int is_ping_pong;
|
||||
union
|
||||
{
|
||||
struct
|
||||
{
|
||||
enum dmac_transfer_flow flow_control;
|
||||
size_t element_size;
|
||||
size_t count;
|
||||
void* alloc_mem;
|
||||
volatile void* dest;
|
||||
};
|
||||
|
||||
struct
|
||||
{
|
||||
const volatile void* srcs[MAX_PING_PONG_SRCS];
|
||||
size_t src_num;
|
||||
volatile void* dests[MAX_PING_PONG_SRCS];
|
||||
size_t dest_num;
|
||||
size_t next_src_id;
|
||||
size_t next_dest_id;
|
||||
dma_stage_completion_handler stage_completion_handler;
|
||||
void* stage_completion_handler_data;
|
||||
int* stop_signal;
|
||||
};
|
||||
};
|
||||
} session;
|
||||
} dma_data;
|
||||
|
||||
static void dma_completion_isr(void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
|
||||
configASSERT(dma->intstatus & 0x2);
|
||||
dma->intclear = 0xFFFFFFFF;
|
||||
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
if (data->session.is_ping_pong)
|
||||
{
|
||||
if (atomic_read(data->session.stop_signal))
|
||||
{
|
||||
release_axi_master(dmacdata, data->session.axi_master);
|
||||
if (data->session.stage_completion_handler)
|
||||
data->session.stage_completion_handler(data->session.stage_completion_handler_data);
|
||||
xSemaphoreGiveFromISR(data->session.completion_event, &xHigherPriorityTaskWoken);
|
||||
}
|
||||
else
|
||||
{
|
||||
size_t cnt_src_id = data->session.next_src_id;
|
||||
dma->sar = (uint64_t)data->session.srcs[cnt_src_id++];
|
||||
if (cnt_src_id < data->session.src_num)
|
||||
data->session.next_src_id++;
|
||||
else
|
||||
data->session.next_src_id = 0;
|
||||
|
||||
size_t cnt_dest_id = data->session.next_dest_id;
|
||||
dma->dar = (uint64_t)data->session.dests[cnt_dest_id++];
|
||||
if (cnt_dest_id < data->session.dest_num)
|
||||
data->session.next_dest_id++;
|
||||
else
|
||||
data->session.next_dest_id = 0;
|
||||
|
||||
if (data->session.stage_completion_handler)
|
||||
data->session.stage_completion_handler(data->session.stage_completion_handler_data);
|
||||
dmac->chen |= 0x101 << data->channel;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
release_axi_master(dmacdata, data->session.axi_master);
|
||||
|
||||
if (data->session.flow_control != DMAC_MEM2MEM_DMA && data->session.element_size < 4)
|
||||
{
|
||||
if (data->session.flow_control == DMAC_PRF2MEM_DMA)
|
||||
{
|
||||
if (data->session.element_size == 1)
|
||||
{
|
||||
size_t i;
|
||||
uint32_t* p_src = data->session.alloc_mem;
|
||||
uint8_t* p_dst = (uint8_t*)data->session.dest;
|
||||
for (i = 0; i < data->session.count; i++)
|
||||
p_dst[i] = p_src[i];
|
||||
}
|
||||
else if (data->session.element_size == 2)
|
||||
{
|
||||
size_t i;
|
||||
uint32_t* p_src = data->session.alloc_mem;
|
||||
uint16_t* p_dst = (uint16_t*)data->session.dest;
|
||||
for (i = 0; i < data->session.count; i++)
|
||||
p_dst[i] = p_src[i];
|
||||
}
|
||||
else
|
||||
{
|
||||
configASSERT(!"invalid element size");
|
||||
}
|
||||
}
|
||||
else if (data->session.flow_control == DMAC_MEM2PRF_DMA)
|
||||
;
|
||||
else
|
||||
{
|
||||
configASSERT(!"Impossible");
|
||||
}
|
||||
|
||||
free(data->session.alloc_mem);
|
||||
}
|
||||
|
||||
xSemaphoreGiveFromISR(data->session.completion_event, &xHigherPriorityTaskWoken);
|
||||
}
|
||||
}
|
||||
|
||||
static void dma_install(void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
|
||||
pic_set_irq_handler(IRQN_DMA0_INTERRUPT + data->channel, dma_completion_isr, userdata);
|
||||
pic_set_irq_priority(IRQN_DMA0_INTERRUPT + data->channel, 1);
|
||||
pic_set_irq_enable(IRQN_DMA0_INTERRUPT + data->channel, 1);
|
||||
}
|
||||
|
||||
static int dma_open(void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
return atomic_cas(&data->used, 0, 1) == 0;
|
||||
}
|
||||
|
||||
static void dma_close_imp(void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
atomic_set(&data->used, 0);
|
||||
}
|
||||
|
||||
static void dma_set_select_request_imp(uint32_t request, void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
|
||||
if (data->channel == SYSCTL_DMA_CHANNEL_5)
|
||||
{
|
||||
sysctl->dma_sel1.dma_sel5 = request;
|
||||
}
|
||||
else
|
||||
{
|
||||
struct sysctl_dma_sel0_t dma_sel;
|
||||
dma_sel = sysctl->dma_sel0;
|
||||
|
||||
switch (data->channel)
|
||||
{
|
||||
case SYSCTL_DMA_CHANNEL_0:
|
||||
dma_sel.dma_sel0 = request;
|
||||
break;
|
||||
|
||||
case SYSCTL_DMA_CHANNEL_1:
|
||||
dma_sel.dma_sel1 = request;
|
||||
break;
|
||||
|
||||
case SYSCTL_DMA_CHANNEL_2:
|
||||
dma_sel.dma_sel2 = request;
|
||||
break;
|
||||
|
||||
case SYSCTL_DMA_CHANNEL_3:
|
||||
dma_sel.dma_sel3 = request;
|
||||
break;
|
||||
|
||||
case SYSCTL_DMA_CHANNEL_4:
|
||||
dma_sel.dma_sel4 = request;
|
||||
break;
|
||||
|
||||
default:
|
||||
configASSERT(!"Invalid dma channel");
|
||||
}
|
||||
|
||||
/* Write register back to bus */
|
||||
sysctl->dma_sel0 = dma_sel;
|
||||
}
|
||||
}
|
||||
|
||||
static void dma_config_imp(uint32_t priority, void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
configASSERT((dmac->chen & (1 << data->channel)) == 0);
|
||||
configASSERT(priority <= 7);
|
||||
|
||||
union dmac_ch_cfg_u cfg_u;
|
||||
|
||||
cfg_u.data = readq(&dma->cfg);
|
||||
cfg_u.ch_cfg.ch_prior = priority;
|
||||
writeq(cfg_u.data, &dma->cfg);
|
||||
}
|
||||
|
||||
static int is_memory(uintptr_t address)
|
||||
{
|
||||
enum
|
||||
{
|
||||
mem_len = 6 * 1024 * 1024
|
||||
};
|
||||
|
||||
return ((address >= 0x80000000) && (address < 0x80000000 + mem_len)) || ((address >= 0x40000000) && (address < 0x40000000 + mem_len)) || (address == 0x50450040);
|
||||
}
|
||||
|
||||
static void dma_loop_async_imp(const volatile void** srcs, size_t src_num, volatile void** dests, size_t dest_num, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, dma_stage_completion_handler stage_completion_handler, void* stage_completion_handler_data, SemaphoreHandle_t completion_event, int* stop_signal, void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
|
||||
if (count == 0)
|
||||
{
|
||||
xSemaphoreGive(completion_event);
|
||||
return;
|
||||
}
|
||||
|
||||
src_inc = !src_inc;
|
||||
dest_inc = !dest_inc;
|
||||
configASSERT(count > 0 && count <= 0x3fffff);
|
||||
configASSERT((dmac->chen & (1 << data->channel)) == 0);
|
||||
configASSERT(element_size >= 4);
|
||||
configASSERT(src_num > 0 && src_num <= MAX_PING_PONG_SRCS);
|
||||
configASSERT(dest_num > 0 && dest_num <= MAX_PING_PONG_SRCS);
|
||||
|
||||
int mem_type_src = is_memory((uintptr_t)srcs[0]), mem_type_dest = is_memory((uintptr_t)dests[0]);
|
||||
|
||||
union dmac_ch_cfg_u cfg_u;
|
||||
|
||||
enum dmac_transfer_flow flow_control = DMAC_MEM2MEM_DMA;
|
||||
if (mem_type_src == 0 && mem_type_dest == 0)
|
||||
{
|
||||
configASSERT(!"Periph to periph dma is not supported.");
|
||||
}
|
||||
else if (mem_type_src == 1 && mem_type_dest == 0)
|
||||
flow_control = DMAC_MEM2PRF_DMA;
|
||||
else if (mem_type_src == 0 && mem_type_dest == 1)
|
||||
flow_control = DMAC_PRF2MEM_DMA;
|
||||
else if (mem_type_src == 1 && mem_type_dest == 1)
|
||||
flow_control = DMAC_MEM2MEM_DMA;
|
||||
|
||||
configASSERT(flow_control == DMAC_MEM2MEM_DMA || element_size <= 8);
|
||||
|
||||
cfg_u.data = readq(&dma->cfg);
|
||||
cfg_u.ch_cfg.tt_fc = flow_control;
|
||||
cfg_u.ch_cfg.hs_sel_src = mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
|
||||
cfg_u.ch_cfg.hs_sel_dst = mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
|
||||
cfg_u.ch_cfg.src_per = data->channel;
|
||||
cfg_u.ch_cfg.dst_per = data->channel;
|
||||
cfg_u.ch_cfg.src_multblk_type = 0;
|
||||
cfg_u.ch_cfg.dst_multblk_type = 0;
|
||||
|
||||
writeq(cfg_u.data, &dma->cfg);
|
||||
|
||||
data->session.is_ping_pong = 1;
|
||||
data->session.flow_control = flow_control;
|
||||
|
||||
dma->sar = (uint64_t)srcs[0];
|
||||
dma->dar = (uint64_t)dests[0];
|
||||
|
||||
dma->block_ts = count - 1;
|
||||
|
||||
uint32_t tr_width = 0;
|
||||
switch (element_size)
|
||||
{
|
||||
case 1:
|
||||
tr_width = 0;
|
||||
break;
|
||||
case 2:
|
||||
tr_width = 1;
|
||||
break;
|
||||
case 4:
|
||||
tr_width = 2;
|
||||
break;
|
||||
case 8:
|
||||
tr_width = 3;
|
||||
break;
|
||||
case 16:
|
||||
tr_width = 4;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid element size.");
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t msize = 0;
|
||||
switch (burst_size)
|
||||
{
|
||||
case 1:
|
||||
msize = 0;
|
||||
break;
|
||||
case 4:
|
||||
msize = 1;
|
||||
break;
|
||||
case 8:
|
||||
msize = 2;
|
||||
break;
|
||||
case 16:
|
||||
msize = 3;
|
||||
break;
|
||||
case 32:
|
||||
msize = 4;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid busrt size.");
|
||||
break;
|
||||
}
|
||||
|
||||
dma->intstatus_en = 0xFFFFFFE2;
|
||||
dma->intclear = 0xFFFFFFFF;
|
||||
|
||||
union dmac_ch_ctl_u ctl_u;
|
||||
|
||||
ctl_u.data = readq(&dma->ctl);
|
||||
ctl_u.ch_ctl.sinc = src_inc;
|
||||
ctl_u.ch_ctl.src_tr_width = tr_width;
|
||||
ctl_u.ch_ctl.src_msize = msize;
|
||||
ctl_u.ch_ctl.dinc = dest_inc;
|
||||
ctl_u.ch_ctl.dst_tr_width = tr_width;
|
||||
ctl_u.ch_ctl.dst_msize = msize;
|
||||
|
||||
uint32_t axi_master = add_lru_axi_master(dmacdata);
|
||||
data->session.axi_master = axi_master;
|
||||
|
||||
ctl_u.ch_ctl.sms = axi_master;
|
||||
ctl_u.ch_ctl.dms = axi_master;
|
||||
|
||||
writeq(ctl_u.data, &dma->ctl);
|
||||
|
||||
data->session.completion_event = completion_event;
|
||||
data->session.stage_completion_handler_data = stage_completion_handler_data;
|
||||
data->session.stage_completion_handler = stage_completion_handler;
|
||||
data->session.stop_signal = stop_signal;
|
||||
data->session.src_num = src_num;
|
||||
data->session.dest_num = dest_num;
|
||||
data->session.next_src_id = 0;
|
||||
data->session.next_dest_id = 0;
|
||||
size_t i = 0;
|
||||
for (i = 0; i < src_num; i++)
|
||||
data->session.srcs[i] = srcs[i];
|
||||
for (i = 0; i < dest_num; i++)
|
||||
data->session.dests[i] = dests[i];
|
||||
|
||||
dmac->chen |= 0x101 << data->channel;
|
||||
}
|
||||
|
||||
static void dma_transmit_async_imp(const volatile void* src, volatile void* dest, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, SemaphoreHandle_t completion_event, void* userdata)
|
||||
{
|
||||
C_COMMON_ENTRY;
|
||||
|
||||
if (count == 0)
|
||||
{
|
||||
xSemaphoreGive(completion_event);
|
||||
return;
|
||||
}
|
||||
|
||||
src_inc = !src_inc;
|
||||
dest_inc = !dest_inc;
|
||||
configASSERT(count > 0 && count <= 0x3fffff);
|
||||
configASSERT((dmac->chen & (1 << data->channel)) == 0);
|
||||
|
||||
int mem_type_src = is_memory((uintptr_t)src), mem_type_dest = is_memory((uintptr_t)dest);
|
||||
|
||||
union dmac_ch_cfg_u cfg_u;
|
||||
|
||||
enum dmac_transfer_flow flow_control = DMAC_MEM2MEM_DMA;
|
||||
if (mem_type_src == 0 && mem_type_dest == 0)
|
||||
{
|
||||
configASSERT(!"Periph to periph dma is not supported.");
|
||||
}
|
||||
else if (mem_type_src == 1 && mem_type_dest == 0)
|
||||
flow_control = DMAC_MEM2PRF_DMA;
|
||||
else if (mem_type_src == 0 && mem_type_dest == 1)
|
||||
flow_control = DMAC_PRF2MEM_DMA;
|
||||
else if (mem_type_src == 1 && mem_type_dest == 1)
|
||||
flow_control = DMAC_MEM2MEM_DMA;
|
||||
|
||||
configASSERT(flow_control == DMAC_MEM2MEM_DMA || element_size <= 8);
|
||||
|
||||
cfg_u.data = readq(&dma->cfg);
|
||||
cfg_u.ch_cfg.tt_fc = flow_control;
|
||||
cfg_u.ch_cfg.hs_sel_src = mem_type_src ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
|
||||
cfg_u.ch_cfg.hs_sel_dst = mem_type_dest ? DMAC_HS_SOFTWARE : DMAC_HS_HARDWARE;
|
||||
cfg_u.ch_cfg.src_per = data->channel;
|
||||
cfg_u.ch_cfg.dst_per = data->channel;
|
||||
cfg_u.ch_cfg.src_multblk_type = 0;
|
||||
cfg_u.ch_cfg.dst_multblk_type = 0;
|
||||
|
||||
writeq(cfg_u.data, &dma->cfg);
|
||||
|
||||
data->session.is_ping_pong = 0;
|
||||
data->session.flow_control = flow_control;
|
||||
|
||||
size_t old_elm_size = element_size;
|
||||
data->session.element_size = old_elm_size;
|
||||
data->session.count = count;
|
||||
data->session.dest = dest;
|
||||
data->session.alloc_mem = NULL;
|
||||
|
||||
if (flow_control != DMAC_MEM2MEM_DMA && old_elm_size < 4)
|
||||
{
|
||||
void* alloc_mem = malloc(sizeof(uint32_t) * count);
|
||||
data->session.alloc_mem = alloc_mem;
|
||||
element_size = sizeof(uint32_t);
|
||||
|
||||
if (!mem_type_src)
|
||||
{
|
||||
dma->sar = (uint64_t)src;
|
||||
dma->dar = (uint64_t)alloc_mem;
|
||||
}
|
||||
else if (!mem_type_dest)
|
||||
{
|
||||
if (old_elm_size == 1)
|
||||
{
|
||||
size_t i;
|
||||
const uint8_t* p_src = (const uint8_t*)src;
|
||||
uint32_t* p_dst = alloc_mem;
|
||||
for (i = 0; i < count; i++)
|
||||
p_dst[i] = p_src[i];
|
||||
}
|
||||
else if (old_elm_size == 2)
|
||||
{
|
||||
size_t i;
|
||||
const uint16_t* p_src = (const uint16_t*)src;
|
||||
uint32_t* p_dst = alloc_mem;
|
||||
for (i = 0; i < count; i++)
|
||||
p_dst[i] = p_src[i];
|
||||
}
|
||||
else
|
||||
{
|
||||
configASSERT(!"invalid element size");
|
||||
}
|
||||
|
||||
dma->sar = (uint64_t)alloc_mem;
|
||||
dma->dar = (uint64_t)dest;
|
||||
}
|
||||
else
|
||||
{
|
||||
configASSERT(!"Impossible");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
dma->sar = (uint64_t)src;
|
||||
dma->dar = (uint64_t)dest;
|
||||
}
|
||||
|
||||
dma->block_ts = count - 1;
|
||||
|
||||
uint32_t tr_width = 0;
|
||||
switch (element_size)
|
||||
{
|
||||
case 1:
|
||||
tr_width = 0;
|
||||
break;
|
||||
case 2:
|
||||
tr_width = 1;
|
||||
break;
|
||||
case 4:
|
||||
tr_width = 2;
|
||||
break;
|
||||
case 8:
|
||||
tr_width = 3;
|
||||
break;
|
||||
case 16:
|
||||
tr_width = 4;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid element size.");
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t msize = 0;
|
||||
switch (burst_size)
|
||||
{
|
||||
case 1:
|
||||
msize = 0;
|
||||
break;
|
||||
case 4:
|
||||
msize = 1;
|
||||
break;
|
||||
case 8:
|
||||
msize = 2;
|
||||
break;
|
||||
case 16:
|
||||
msize = 3;
|
||||
break;
|
||||
case 32:
|
||||
msize = 4;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid busrt size.");
|
||||
break;
|
||||
}
|
||||
|
||||
dma->intstatus_en = 0xFFFFFFE2;
|
||||
dma->intclear = 0xFFFFFFFF;
|
||||
|
||||
union dmac_ch_ctl_u ctl_u;
|
||||
|
||||
ctl_u.data = readq(&dma->ctl);
|
||||
ctl_u.ch_ctl.sinc = src_inc;
|
||||
ctl_u.ch_ctl.src_tr_width = tr_width;
|
||||
ctl_u.ch_ctl.src_msize = msize;
|
||||
ctl_u.ch_ctl.dinc = dest_inc;
|
||||
ctl_u.ch_ctl.dst_tr_width = tr_width;
|
||||
ctl_u.ch_ctl.dst_msize = msize;
|
||||
|
||||
uint32_t axi_master = add_lru_axi_master(dmacdata);
|
||||
data->session.axi_master = axi_master;
|
||||
|
||||
ctl_u.ch_ctl.sms = axi_master;
|
||||
ctl_u.ch_ctl.dms = axi_master;
|
||||
|
||||
writeq(ctl_u.data, &dma->ctl);
|
||||
|
||||
data->session.completion_event = completion_event;
|
||||
dmac->chen |= 0x101 << data->channel;
|
||||
}
|
||||
|
||||
static dma_data dev0_c0_data = {&dev0_data, 0, 0, {0}};
|
||||
static dma_data dev0_c1_data = {&dev0_data, 1, 0, {0}};
|
||||
static dma_data dev0_c2_data = {&dev0_data, 2, 0, {0}};
|
||||
static dma_data dev0_c3_data = {&dev0_data, 3, 0, {0}};
|
||||
static dma_data dev0_c4_data = {&dev0_data, 4, 0, {0}};
|
||||
static dma_data dev0_c5_data = {&dev0_data, 5, 0, {0}};
|
||||
|
||||
const dma_driver_t g_dma_driver_dma0 = {{&dev0_c0_data, dma_install, dma_open, dma_close_imp}, dma_set_select_request_imp, dma_config_imp, dma_transmit_async_imp, dma_loop_async_imp};
|
||||
const dma_driver_t g_dma_driver_dma1 = {{&dev0_c1_data, dma_install, dma_open, dma_close_imp}, dma_set_select_request_imp, dma_config_imp, dma_transmit_async_imp, dma_loop_async_imp};
|
||||
const dma_driver_t g_dma_driver_dma2 = {{&dev0_c2_data, dma_install, dma_open, dma_close_imp}, dma_set_select_request_imp, dma_config_imp, dma_transmit_async_imp, dma_loop_async_imp};
|
||||
const dma_driver_t g_dma_driver_dma3 = {{&dev0_c3_data, dma_install, dma_open, dma_close_imp}, dma_set_select_request_imp, dma_config_imp, dma_transmit_async_imp, dma_loop_async_imp};
|
||||
const dma_driver_t g_dma_driver_dma4 = {{&dev0_c4_data, dma_install, dma_open, dma_close_imp}, dma_set_select_request_imp, dma_config_imp, dma_transmit_async_imp, dma_loop_async_imp};
|
||||
const dma_driver_t g_dma_driver_dma5 = {{&dev0_c5_data, dma_install, dma_open, dma_close_imp}, dma_set_select_request_imp, dma_config_imp, dma_transmit_async_imp, dma_loop_async_imp};
|
|
@ -0,0 +1,233 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <dvp.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <io.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
dvp_data* data = (dvp_data*)userdata; \
|
||||
volatile struct dvp_t* dvp = (volatile struct dvp_t*)data->base_addr; \
|
||||
(void)dvp;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
uintptr_t base_addr;
|
||||
|
||||
struct
|
||||
{
|
||||
dvp_on_frame_event frame_event_callback;
|
||||
void* frame_event_callback_data;
|
||||
size_t width;
|
||||
size_t height;
|
||||
};
|
||||
} dvp_data;
|
||||
|
||||
static void dvp_frame_event_isr(void* userdata);
|
||||
|
||||
static void dvp_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
sysctl_clock_enable(data->clock);
|
||||
pic_set_irq_handler(IRQN_DVP_INTERRUPT, dvp_frame_event_isr, userdata);
|
||||
pic_set_irq_priority(IRQN_DVP_INTERRUPT, 1);
|
||||
}
|
||||
|
||||
static int dvp_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void dvp_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void dvp_config(size_t width, size_t height, int auto_enable, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(width % 8 == 0 && width && height);
|
||||
|
||||
uint32_t dvp_cfg = dvp->dvp_cfg;
|
||||
|
||||
if (width / 8 % 4 == 0)
|
||||
{
|
||||
dvp_cfg |= DVP_CFG_BURST_SIZE_4BEATS;
|
||||
set_bit_mask(&dvp_cfg, DVP_AXI_GM_MLEN_MASK | DVP_CFG_HREF_BURST_NUM_MASK, DVP_AXI_GM_MLEN_4BYTE | DVP_CFG_HREF_BURST_NUM(width / 8 / 4));
|
||||
}
|
||||
else
|
||||
{
|
||||
dvp_cfg &= (~DVP_CFG_BURST_SIZE_4BEATS);
|
||||
set_bit_mask(&dvp_cfg, DVP_AXI_GM_MLEN_MASK, DVP_AXI_GM_MLEN_1BYTE | DVP_CFG_HREF_BURST_NUM(width / 8));
|
||||
}
|
||||
|
||||
set_bit_mask(&dvp_cfg, DVP_CFG_LINE_NUM_MASK, DVP_CFG_LINE_NUM(height));
|
||||
|
||||
if (auto_enable)
|
||||
dvp_cfg |= DVP_CFG_AUTO_ENABLE;
|
||||
else
|
||||
dvp_cfg &= ~DVP_CFG_AUTO_ENABLE;
|
||||
|
||||
dvp->dvp_cfg = dvp_cfg;
|
||||
dvp->cmos_cfg |= DVP_CMOS_CLK_DIV(0) | DVP_CMOS_CLK_ENABLE;
|
||||
data->width = width;
|
||||
data->height = height;
|
||||
}
|
||||
|
||||
static void dvp_enable_frame(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
dvp->sts = DVP_STS_DVP_EN | DVP_STS_DVP_EN_WE;
|
||||
}
|
||||
|
||||
static void dvp_set_signal(dvp_signal_type type, int value, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
switch (type)
|
||||
{
|
||||
case DVP_SIG_POWER_DOWN:
|
||||
if (value)
|
||||
dvp->cmos_cfg |= DVP_CMOS_POWER_DOWN;
|
||||
else
|
||||
dvp->cmos_cfg &= ~DVP_CMOS_POWER_DOWN;
|
||||
break;
|
||||
case DVP_SIG_RESET:
|
||||
if (value)
|
||||
dvp->cmos_cfg |= DVP_CMOS_RESET;
|
||||
else
|
||||
dvp->cmos_cfg &= ~DVP_CMOS_RESET;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid signal type.");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void dvp_set_output_enable(size_t index, int enable, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(index < 2);
|
||||
|
||||
if (index == 0)
|
||||
{
|
||||
if (enable)
|
||||
dvp->dvp_cfg |= DVP_CFG_AI_OUTPUT_ENABLE;
|
||||
else
|
||||
dvp->dvp_cfg &= ~DVP_CFG_AI_OUTPUT_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (enable)
|
||||
dvp->dvp_cfg |= DVP_CFG_DISPLAY_OUTPUT_ENABLE;
|
||||
else
|
||||
dvp->dvp_cfg &= ~DVP_CFG_DISPLAY_OUTPUT_ENABLE;
|
||||
}
|
||||
}
|
||||
|
||||
static void dvp_set_output_attributes(size_t index, video_format format, void* output_buffer, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(index < 2);
|
||||
|
||||
if (index == 0)
|
||||
{
|
||||
configASSERT(format == VIDEO_FMT_RGB24Planar);
|
||||
uintptr_t buffer_addr = (uintptr_t)output_buffer;
|
||||
size_t planar_size = data->width * data->height;
|
||||
dvp->r_addr = buffer_addr;
|
||||
dvp->g_addr = buffer_addr + planar_size;
|
||||
dvp->b_addr = buffer_addr + planar_size * 2;
|
||||
}
|
||||
else
|
||||
{
|
||||
configASSERT(format == VIDEO_FMT_RGB565);
|
||||
dvp->rgb_addr = (uintptr_t)output_buffer;
|
||||
}
|
||||
}
|
||||
|
||||
static void dvp_frame_event_isr(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
if (dvp->sts & DVP_STS_FRAME_START)
|
||||
{
|
||||
dvp_on_frame_event callback;
|
||||
if ((callback = data->frame_event_callback))
|
||||
callback(VIDEO_FE_BEGIN, data->frame_event_callback_data);
|
||||
dvp->sts |= DVP_STS_FRAME_START | DVP_STS_FRAME_START_WE;
|
||||
}
|
||||
if (dvp->sts & DVP_STS_FRAME_FINISH)
|
||||
{
|
||||
dvp_on_frame_event callback;
|
||||
if ((callback = data->frame_event_callback))
|
||||
callback(VIDEO_FE_END, data->frame_event_callback_data);
|
||||
dvp->sts |= DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE;
|
||||
}
|
||||
}
|
||||
|
||||
static void dvp_set_frame_event_enable(video_frame_event event, int enable, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
switch (event)
|
||||
{
|
||||
case VIDEO_FE_BEGIN:
|
||||
if (enable)
|
||||
{
|
||||
dvp->sts |= DVP_STS_FRAME_START | DVP_STS_FRAME_START_WE;
|
||||
dvp->dvp_cfg |= DVP_CFG_START_INT_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
dvp->dvp_cfg &= ~DVP_CFG_START_INT_ENABLE;
|
||||
}
|
||||
break;
|
||||
case VIDEO_FE_END:
|
||||
if (enable)
|
||||
{
|
||||
dvp->sts |= DVP_STS_FRAME_FINISH | DVP_STS_FRAME_FINISH_WE;
|
||||
dvp->dvp_cfg |= DVP_CFG_FINISH_INT_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
dvp->dvp_cfg &= ~DVP_CFG_FINISH_INT_ENABLE;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid event.");
|
||||
break;
|
||||
}
|
||||
|
||||
pic_set_irq_enable(IRQN_DVP_INTERRUPT, 1);
|
||||
}
|
||||
|
||||
static void dvp_set_on_frame_event(dvp_on_frame_event callback, void* callback_data, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
data->frame_event_callback_data = callback_data;
|
||||
data->frame_event_callback = callback;
|
||||
}
|
||||
|
||||
static dvp_data dev0_data = {SYSCTL_CLOCK_DVP, DVP_BASE_ADDR, {0}};
|
||||
|
||||
const dvp_driver_t g_dvp_driver_dvp0 = {{&dev0_data, dvp_install, dvp_open, dvp_close}, 2, dvp_config, dvp_enable_frame, dvp_set_signal, dvp_set_output_enable, dvp_set_output_attributes, dvp_set_frame_event_enable, dvp_set_on_frame_event};
|
|
@ -0,0 +1,129 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <hal.h>
|
||||
#include <hard_fft.h>
|
||||
#include <io.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
|
||||
#define FFT_BASE_ADDR (0x42000000)
|
||||
#define FFT_RESULT_ADDR (0x42100000 + 0x2000)
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
fft_dev_data* data = (fft_dev_data*)userdata; \
|
||||
volatile fft_t* fft = (volatile fft_t*)data->base_addr;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uintptr_t base_addr;
|
||||
SemaphoreHandle_t free_mutex;
|
||||
} fft_dev_data;
|
||||
|
||||
static void fft_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_FFT);
|
||||
sysctl_reset(SYSCTL_RESET_FFT);
|
||||
data->free_mutex = xSemaphoreCreateMutex();
|
||||
|
||||
fft->intr_clear.fft_done_clear = 1;
|
||||
fft->intr_mask.fft_done_mask = 0;
|
||||
}
|
||||
|
||||
static int fft_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void fft_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void entry_exclusive(fft_dev_data* data)
|
||||
{
|
||||
configASSERT(xSemaphoreTake(data->free_mutex, portMAX_DELAY) == pdTRUE);
|
||||
}
|
||||
|
||||
static void exit_exclusive(fft_dev_data* data)
|
||||
{
|
||||
xSemaphoreGive(data->free_mutex);
|
||||
}
|
||||
|
||||
static void fft_complex_uint16(fft_point point, fft_direction direction, uint32_t shifts_mask, const uint16_t* input, uint16_t* output, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(((uintptr_t)input) % 8 == 0 && ((uintptr_t)output) % 8 == 0);
|
||||
configASSERT(shifts_mask <= 0x1ff);
|
||||
|
||||
entry_exclusive(data);
|
||||
|
||||
fft_fft_ctrl_t ctl = fft->fft_ctrl;
|
||||
ctl.dma_send = 1;
|
||||
ctl.fft_input_mode = 0;
|
||||
ctl.fft_data_mode = 0;
|
||||
ctl.fft_point = point;
|
||||
ctl.fft_mode = direction;
|
||||
ctl.fft_shift = shifts_mask;
|
||||
ctl.fft_enable = 1;
|
||||
fft->fft_ctrl = ctl;
|
||||
|
||||
size_t blocks = 0;
|
||||
switch (point)
|
||||
{
|
||||
case FFT_512:
|
||||
blocks = 256;
|
||||
break;
|
||||
case FFT_256:
|
||||
blocks = 128;
|
||||
break;
|
||||
case FFT_128:
|
||||
blocks = 64;
|
||||
break;
|
||||
case FFT_64:
|
||||
blocks = 32;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid fft point");
|
||||
break;
|
||||
}
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
uintptr_t dma_read = dma_open_free();
|
||||
|
||||
dma_set_select_request(dma_write, SYSCTL_DMA_SELECT_FFT_TX_REQ);
|
||||
dma_set_select_request(dma_read, SYSCTL_DMA_SELECT_FFT_RX_REQ);
|
||||
|
||||
SemaphoreHandle_t event_read = xSemaphoreCreateBinary(), event_write = xSemaphoreCreateBinary();
|
||||
|
||||
dma_transmit_async(dma_read, &fft->fft_output_fifo, output, 0, 1, sizeof(uint64_t), blocks, 4, event_read);
|
||||
dma_transmit_async(dma_write, input, &fft->fft_input_fifo, 1, 0, sizeof(uint64_t), blocks, 4, event_write);
|
||||
|
||||
configASSERT(xSemaphoreTake(event_read, portMAX_DELAY) == pdTRUE && xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
dma_close(dma_write);
|
||||
dma_close(dma_read);
|
||||
vSemaphoreDelete(event_read);
|
||||
vSemaphoreDelete(event_write);
|
||||
|
||||
exit_exclusive(data);
|
||||
}
|
||||
|
||||
static fft_dev_data dev0_data = {FFT_BASE_ADDR, 0};
|
||||
|
||||
const fft_driver_t g_fft_driver_fft0 = {{&dev0_data, fft_install, fft_open, fft_close}, fft_complex_uint16};
|
|
@ -0,0 +1,27 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
int fpioa_get_io_by_func(enum fpioa_function_e function)
|
||||
{
|
||||
int index;
|
||||
for (index = 0; index < FPIOA_NUM_IO; index++)
|
||||
{
|
||||
if (fpioa->io[index].ch_sel == function)
|
||||
return index;
|
||||
}
|
||||
|
||||
return -1;
|
||||
}
|
|
@ -0,0 +1,31 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _FPIOA_CFG_H
|
||||
#define _FPIOA_CFG_H
|
||||
|
||||
#include <fpioa.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t version;
|
||||
uint32_t io_count;
|
||||
enum fpioa_function_e io_functions[FPIOA_NUM_IO];
|
||||
} fpioa_cfg_t;
|
||||
|
||||
extern const fpioa_cfg_t g_fpioa_cfg;
|
||||
|
||||
int fpioa_get_io_by_func(enum fpioa_function_e function);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,123 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <gpio.h>
|
||||
#include <io.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
gpio_data* data = (gpio_data*)userdata; \
|
||||
volatile gpio_t* gpio = (volatile gpio_t*)data->base_addr; \
|
||||
configASSERT(pin < data->pin_count); \
|
||||
(void)data; \
|
||||
(void)gpio;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
size_t pin_count;
|
||||
uintptr_t base_addr;
|
||||
} gpio_data;
|
||||
|
||||
static void gpio_install(void* userdata)
|
||||
{
|
||||
/* GPIO clock under APB0 clock, so enable APB0 clock firstly */
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_APB0);
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_APB1);
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_GPIO);
|
||||
}
|
||||
|
||||
static int gpio_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void gpio_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void gpio_set_drive_mode(void* userdata, size_t pin, gpio_drive_mode mode)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
int io_number = fpioa_get_io_by_func(FUNC_GPIO0 + pin);
|
||||
configASSERT(io_number > 0);
|
||||
|
||||
enum fpioa_pull_e pull = 0;
|
||||
uint32_t dir = 0;
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_DM_INPUT:
|
||||
pull = FPIOA_PULL_NONE;
|
||||
dir = 0;
|
||||
break;
|
||||
case GPIO_DM_INPUT_PULL_DOWN:
|
||||
pull = FPIOA_PULL_DOWN;
|
||||
dir = 0;
|
||||
break;
|
||||
case GPIO_DM_INPUT_PULL_UP:
|
||||
pull = FPIOA_PULL_UP;
|
||||
dir = 0;
|
||||
break;
|
||||
case GPIO_DM_OUTPUT:
|
||||
pull = FPIOA_PULL_DOWN;
|
||||
dir = 1;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"GPIO drive mode is not supported.") break;
|
||||
}
|
||||
|
||||
fpioa_set_io_pull(io_number, pull);
|
||||
set_bit_idx(gpio->direction.u32, pin, dir);
|
||||
}
|
||||
|
||||
static void gpio_set_pin_edge(void* userdata, size_t pin, gpio_pin_edge edge)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(!"Not supported.")
|
||||
}
|
||||
|
||||
static void gpio_set_onchanged(void* userdata, size_t pin, gpio_onchanged callback, void* callback_data)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(!"Not supported.")
|
||||
}
|
||||
|
||||
static gpio_pin_value gpio_get_pin_value(void* userdata, size_t pin)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint32_t dir = get_bit_idx(gpio->direction.u32, pin);
|
||||
volatile uint32_t* reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
|
||||
return get_bit_idx(reg, pin);
|
||||
}
|
||||
|
||||
static void gpio_set_pin_value(void* userdata, size_t pin, gpio_pin_value value)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint32_t dir = get_bit_idx(gpio->direction.u32, pin);
|
||||
volatile uint32_t* reg = dir ? gpio->data_output.u32 : gpio->data_input.u32;
|
||||
configASSERT(dir == 1);
|
||||
set_bit_idx(reg, pin, value);
|
||||
}
|
||||
|
||||
static gpio_data dev0_data = {8, GPIO_BASE_ADDR};
|
||||
|
||||
const gpio_driver_t g_gpio_driver_gpio0 = {{&dev0_data, gpio_install, gpio_open, gpio_close}, 8, gpio_set_drive_mode, gpio_set_pin_edge, gpio_set_onchanged, gpio_set_pin_value, gpio_get_pin_value};
|
|
@ -0,0 +1,232 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <gpiohs.h>
|
||||
#include <hal.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
#define COMMON_ENTRY_NO_PIN \
|
||||
gpiohs_data* data = (gpiohs_data*)userdata; \
|
||||
volatile gpiohs_t* gpiohs = (volatile gpiohs_t*)data->base_addr; \
|
||||
(void)gpiohs;
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
COMMON_ENTRY_NO_PIN; \
|
||||
configASSERT(pin < data->pin_count);
|
||||
|
||||
typedef struct
|
||||
{
|
||||
size_t pin_count;
|
||||
uintptr_t base_addr;
|
||||
|
||||
struct gpiohs_pin_context
|
||||
{
|
||||
void* gpio_userdata;
|
||||
size_t pin;
|
||||
gpio_pin_edge edge;
|
||||
gpio_onchanged callback;
|
||||
void* userdata;
|
||||
} pin_context[32];
|
||||
|
||||
} gpiohs_data;
|
||||
|
||||
static void gpiohs_pin_onchange_isr(void* userdata);
|
||||
|
||||
static void gpiohs_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY_NO_PIN;
|
||||
|
||||
gpiohs->rise_ie.u32[0] = 0;
|
||||
gpiohs->rise_ip.u32[0] = 0xFFFFFFFF;
|
||||
gpiohs->fall_ie.u32[0] = 0;
|
||||
gpiohs->fall_ip.u32[0] = 0xFFFFFFFF;
|
||||
|
||||
size_t i;
|
||||
for (i = 0; i < 32; i++)
|
||||
{
|
||||
data->pin_context[i].gpio_userdata = data;
|
||||
data->pin_context[i].pin = i;
|
||||
data->pin_context[i].callback = NULL;
|
||||
data->pin_context[i].userdata = NULL;
|
||||
pic_set_irq_handler(IRQN_GPIOHS0_INTERRUPT + i, gpiohs_pin_onchange_isr, data->pin_context + i);
|
||||
pic_set_irq_priority(IRQN_GPIOHS0_INTERRUPT + i, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static int gpiohs_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void gpiohs_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static uint32_t get_bit(volatile uint32_t* bits, size_t idx)
|
||||
{
|
||||
return ((*bits) & (1 << idx)) >> idx;
|
||||
}
|
||||
|
||||
static void set_bit(volatile uint32_t* bits, size_t idx, uint32_t value)
|
||||
{
|
||||
uint32_t org = (*bits) & ~(1 << idx);
|
||||
*bits = org | (value << idx);
|
||||
}
|
||||
|
||||
static void gpiohs_set_drive_mode(void* userdata, size_t pin, gpio_drive_mode mode)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
int io_number = fpioa_get_io_by_func(FUNC_GPIOHS0 + pin);
|
||||
configASSERT(io_number > 0);
|
||||
|
||||
enum fpioa_pull_e pull;
|
||||
uint32_t dir;
|
||||
|
||||
switch (mode)
|
||||
{
|
||||
case GPIO_DM_INPUT:
|
||||
pull = FPIOA_PULL_NONE;
|
||||
dir = 0;
|
||||
break;
|
||||
case GPIO_DM_INPUT_PULL_DOWN:
|
||||
pull = FPIOA_PULL_DOWN;
|
||||
dir = 0;
|
||||
break;
|
||||
case GPIO_DM_INPUT_PULL_UP:
|
||||
pull = FPIOA_PULL_UP;
|
||||
dir = 0;
|
||||
break;
|
||||
case GPIO_DM_OUTPUT:
|
||||
pull = FPIOA_PULL_DOWN;
|
||||
dir = 1;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"GPIO drive mode is not supported.") break;
|
||||
}
|
||||
|
||||
fpioa_set_io_pull(io_number, pull);
|
||||
volatile uint32_t* reg = dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
|
||||
volatile uint32_t* reg_d = !dir ? gpiohs->output_en.u32 : gpiohs->input_en.u32;
|
||||
set_bit(reg_d, pin, 0);
|
||||
set_bit(reg, pin, 1);
|
||||
}
|
||||
|
||||
void gpiohs_set_pin_edge(void* userdata, size_t pin, gpio_pin_edge edge)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint32_t rise = 0, fall = 0, irq = 0;
|
||||
switch (edge)
|
||||
{
|
||||
case GPIO_PE_NONE:
|
||||
rise = fall = irq = 0;
|
||||
break;
|
||||
case GPIO_PE_FALLING:
|
||||
rise = 0;
|
||||
fall = irq = 1;
|
||||
break;
|
||||
case GPIO_PE_RISING:
|
||||
fall = 0;
|
||||
rise = irq = 1;
|
||||
break;
|
||||
case GPIO_PE_BOTH:
|
||||
rise = fall = irq = 1;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid gpio edge");
|
||||
break;
|
||||
}
|
||||
|
||||
data->pin_context[pin].edge = edge;
|
||||
set_bit(gpiohs->rise_ie.u32, pin, rise);
|
||||
set_bit(gpiohs->fall_ie.u32, pin, fall);
|
||||
pic_set_irq_enable(IRQN_GPIOHS0_INTERRUPT + pin, irq);
|
||||
}
|
||||
|
||||
static void gpiohs_pin_onchange_isr(void* userdata)
|
||||
{
|
||||
struct gpiohs_pin_context* ctx = (struct gpiohs_pin_context*)userdata;
|
||||
gpiohs_data* data = (gpiohs_data*)ctx->gpio_userdata;
|
||||
volatile gpiohs_t* gpiohs = (volatile gpiohs_t*)data->base_addr;
|
||||
|
||||
size_t pin = ctx->pin;
|
||||
uint32_t rise = 0, fall = 0;
|
||||
switch (ctx->edge)
|
||||
{
|
||||
case GPIO_PE_NONE:
|
||||
rise = fall = 0;
|
||||
break;
|
||||
case GPIO_PE_FALLING:
|
||||
rise = 0;
|
||||
fall = 1;
|
||||
break;
|
||||
case GPIO_PE_RISING:
|
||||
fall = 0;
|
||||
rise = 1;
|
||||
break;
|
||||
case GPIO_PE_BOTH:
|
||||
rise = fall = 1;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid gpio edge");
|
||||
break;
|
||||
}
|
||||
|
||||
if (rise)
|
||||
{
|
||||
set_bit(gpiohs->rise_ie.u32, pin, 0);
|
||||
set_bit(gpiohs->rise_ip.u32, pin, 1);
|
||||
set_bit(gpiohs->rise_ie.u32, pin, 1);
|
||||
}
|
||||
|
||||
if (fall)
|
||||
{
|
||||
set_bit(gpiohs->fall_ie.u32, pin, 0);
|
||||
set_bit(gpiohs->fall_ip.u32, pin, 1);
|
||||
set_bit(gpiohs->fall_ie.u32, pin, 1);
|
||||
}
|
||||
|
||||
if (ctx->callback)
|
||||
ctx->callback(ctx->pin, ctx->userdata);
|
||||
}
|
||||
|
||||
void gpiohs_set_onchanged(void* userdata, size_t pin, gpio_onchanged callback, void* callback_data)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
data->pin_context[pin].userdata = callback_data;
|
||||
data->pin_context[pin].callback = callback;
|
||||
}
|
||||
|
||||
gpio_pin_value gpiohs_get_pin_value(void* userdata, size_t pin)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
return get_bit(gpiohs->input_val.u32, pin);
|
||||
}
|
||||
|
||||
void gpiohs_set_pin_value(void* userdata, size_t pin, gpio_pin_value value)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
set_bit(gpiohs->output_val.u32, pin, value);
|
||||
}
|
||||
|
||||
static gpiohs_data dev0_data = {32, GPIOHS_BASE_ADDR, {{0}}};
|
||||
|
||||
const gpio_driver_t g_gpiohs_driver_gpio0 = {{&dev0_data, gpiohs_install, gpiohs_open, gpiohs_close}, 32, gpiohs_set_drive_mode, gpiohs_set_pin_edge, gpiohs_set_onchanged, gpiohs_set_pin_value, gpiohs_get_pin_value};
|
|
@ -0,0 +1,345 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <i2c.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
/* I2C Controller */
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
i2c_data* data = (i2c_data*)userdata; \
|
||||
volatile struct i2c_t* i2c = (volatile struct i2c_t*)data->base_addr; \
|
||||
(void)i2c;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
enum sysctl_threshold_e threshold;
|
||||
enum sysctl_dma_select_e dma_req_base;
|
||||
uintptr_t base_addr;
|
||||
struct
|
||||
{
|
||||
SemaphoreHandle_t free_mutex;
|
||||
i2c_slave_handler slave_handler;
|
||||
};
|
||||
} i2c_data;
|
||||
|
||||
static void i2c_install(void* userdata)
|
||||
{
|
||||
i2c_data* data = (i2c_data*)userdata;
|
||||
|
||||
/* GPIO clock under APB0 clock, so enable APB0 clock firstly */
|
||||
sysctl_clock_enable(data->clock);
|
||||
sysctl_clock_set_threshold(data->threshold, 3);
|
||||
data->free_mutex = xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
static int i2c_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void i2c_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
/* I2C Device */
|
||||
|
||||
#define COMMON_DEV_ENTRY \
|
||||
i2c_dev_data* dev_data = (i2c_dev_data*)userdata; \
|
||||
i2c_data* data = (i2c_data*)dev_data->i2c_data;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
i2c_data* i2c_data;
|
||||
size_t slave_address;
|
||||
size_t address_width;
|
||||
i2c_bus_speed_mode bus_speed_mode;
|
||||
} i2c_dev_data;
|
||||
|
||||
static void i2c_dev_install(void* userdata);
|
||||
static int i2c_dev_open(void* userdata);
|
||||
static void i2c_dev_close(void* userdata);
|
||||
static int i2c_dev_read(char* buffer, size_t len, void* userdata);
|
||||
static int i2c_dev_write(const char* buffer, size_t len, void* userdata);
|
||||
static int i2c_dev_transfer_sequential(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
|
||||
static i2c_device_driver_t* i2c_get_device(size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, void* userdata)
|
||||
{
|
||||
i2c_device_driver_t* driver = (i2c_device_driver_t*)malloc(sizeof(i2c_device_driver_t));
|
||||
memset(driver, 0, sizeof(i2c_device_driver_t));
|
||||
|
||||
i2c_dev_data* dev_data = (i2c_dev_data*)malloc(sizeof(i2c_dev_data));
|
||||
dev_data->slave_address = slave_address;
|
||||
dev_data->address_width = address_width;
|
||||
dev_data->bus_speed_mode = bus_speed_mode;
|
||||
dev_data->i2c_data = userdata;
|
||||
|
||||
driver->base.userdata = dev_data;
|
||||
driver->base.install = i2c_dev_install;
|
||||
driver->base.open = i2c_dev_open;
|
||||
driver->base.close = i2c_dev_close;
|
||||
driver->read = i2c_dev_read;
|
||||
driver->write = i2c_dev_write;
|
||||
driver->transfer_sequential = i2c_dev_transfer_sequential;
|
||||
return driver;
|
||||
}
|
||||
|
||||
static void i2c_config_as_master(size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, void* userdata)
|
||||
{
|
||||
configASSERT(address_width == 7 || address_width == 10);
|
||||
COMMON_ENTRY;
|
||||
|
||||
int speed_mode;
|
||||
switch (bus_speed_mode)
|
||||
{
|
||||
case I2C_BS_STANDARD:
|
||||
speed_mode = 1;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"I2C bus speed is not supported.");
|
||||
break;
|
||||
}
|
||||
|
||||
i2c->enable = 0;
|
||||
i2c->con = I2C_CON_MASTER_MODE | I2C_CON_SLAVE_DISABLE | I2C_CON_RESTART_EN | (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode);
|
||||
i2c->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37);
|
||||
i2c->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40);
|
||||
i2c->tar = I2C_TAR_ADDRESS(slave_address);
|
||||
i2c->intr_mask = 0;
|
||||
|
||||
i2c->dma_cr = 0x3;
|
||||
i2c->dma_rdlr = 0;
|
||||
i2c->dma_tdlr = 4;
|
||||
|
||||
i2c->enable = I2C_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
static int i2c_read(char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint8_t fifo_len, index;
|
||||
uint8_t rx_len = len;
|
||||
size_t read = 0;
|
||||
|
||||
fifo_len = len < 7 ? len : 7;
|
||||
for (index = 0; index < fifo_len; index++)
|
||||
i2c->data_cmd = I2C_DATA_CMD_CMD;
|
||||
len -= fifo_len;
|
||||
while (len || rx_len)
|
||||
{
|
||||
fifo_len = i2c->rxflr;
|
||||
fifo_len = rx_len < fifo_len ? rx_len : fifo_len;
|
||||
for (index = 0; index < fifo_len; index++)
|
||||
*buffer++ = i2c->data_cmd;
|
||||
rx_len -= fifo_len;
|
||||
read += fifo_len;
|
||||
fifo_len = 8 - i2c->txflr;
|
||||
fifo_len = len < fifo_len ? len : fifo_len;
|
||||
for (index = 0; index < fifo_len; index++)
|
||||
i2c->data_cmd = I2C_DATA_CMD_CMD;
|
||||
if (i2c->tx_abrt_source != 0)
|
||||
return read;
|
||||
len -= fifo_len;
|
||||
}
|
||||
|
||||
return read;
|
||||
}
|
||||
|
||||
static int i2c_write(const char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
|
||||
dma_set_select_request(dma_write, data->dma_req_base + 1);
|
||||
dma_transmit(dma_write, buffer, &i2c->data_cmd, 1, 0, 1, len, 4);
|
||||
dma_close(dma_write);
|
||||
|
||||
while (i2c->status & I2C_STATUS_ACTIVITY)
|
||||
{
|
||||
if (i2c->tx_abrt_source != 0)
|
||||
configASSERT(!"source abort");
|
||||
}
|
||||
return len;
|
||||
}
|
||||
|
||||
static int i2c_transfer_sequential(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint32_t* write_cmd = malloc(sizeof(uint32_t) * (write_len + read_len));
|
||||
size_t i;
|
||||
for (i = 0; i < write_len; i++)
|
||||
write_cmd[i] = write_buffer[i];
|
||||
for (i = 0; i < read_len; i++)
|
||||
write_cmd[i + write_len] = I2C_DATA_CMD_CMD;
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
uintptr_t dma_read = dma_open_free();
|
||||
SemaphoreHandle_t event_read = xSemaphoreCreateBinary(), event_write = xSemaphoreCreateBinary();
|
||||
|
||||
dma_set_select_request(dma_write, data->dma_req_base + 1);
|
||||
dma_set_select_request(dma_read, data->dma_req_base);
|
||||
|
||||
dma_transmit_async(dma_read, &i2c->data_cmd, read_buffer, 0, 1, 1 /*sizeof(uint32_t)*/, read_len, 1 /*4*/, event_read);
|
||||
dma_transmit_async(dma_write, write_cmd, &i2c->data_cmd, 1, 0, sizeof(uint32_t), write_len + read_len, 4, event_write);
|
||||
|
||||
configASSERT(xSemaphoreTake(event_read, portMAX_DELAY) == pdTRUE && xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
dma_close(dma_write);
|
||||
dma_close(dma_read);
|
||||
vSemaphoreDelete(event_read);
|
||||
vSemaphoreDelete(event_write);
|
||||
free(write_cmd);
|
||||
return read_len;
|
||||
}
|
||||
|
||||
static void entry_exclusive(i2c_dev_data* dev_data)
|
||||
{
|
||||
i2c_data* data = (i2c_data*)dev_data->i2c_data;
|
||||
configASSERT(xSemaphoreTake(data->free_mutex, portMAX_DELAY) == pdTRUE);
|
||||
i2c_config_as_master(dev_data->slave_address, dev_data->address_width, dev_data->bus_speed_mode, data);
|
||||
}
|
||||
|
||||
static void exit_exclusive(i2c_dev_data* dev_data)
|
||||
{
|
||||
i2c_data* data = (i2c_data*)dev_data->i2c_data;
|
||||
xSemaphoreGive(data->free_mutex);
|
||||
}
|
||||
|
||||
static void i2c_dev_install(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static int i2c_dev_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void i2c_dev_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static int i2c_dev_read(char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = i2c_read(buffer, len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int i2c_dev_write(const char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = i2c_write(buffer, len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int i2c_dev_transfer_sequential(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = i2c_transfer_sequential(write_buffer, write_len, read_buffer, read_len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void on_i2c_irq(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uint32_t status = i2c->intr_stat;
|
||||
uint32_t dummy;
|
||||
|
||||
if (status & I2C_INTR_STAT_START_DET)
|
||||
{
|
||||
data->slave_handler.on_event(I2C_EV_START);
|
||||
dummy = i2c->clr_start_det;
|
||||
}
|
||||
if (status & I2C_INTR_STAT_STOP_DET)
|
||||
{
|
||||
data->slave_handler.on_event(I2C_EV_STOP);
|
||||
dummy = i2c->clr_stop_det;
|
||||
}
|
||||
if (status & I2C_INTR_STAT_RX_FULL)
|
||||
{
|
||||
data->slave_handler.on_receive(i2c->data_cmd);
|
||||
}
|
||||
if (status & I2C_INTR_STAT_RD_REQ)
|
||||
{
|
||||
i2c->data_cmd = data->slave_handler.on_transmit();
|
||||
}
|
||||
|
||||
(void)dummy;
|
||||
}
|
||||
|
||||
static void i2c_config_as_slave(size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, i2c_slave_handler* handler, void* userdata)
|
||||
{
|
||||
configASSERT(address_width == 7 || address_width == 10);
|
||||
COMMON_ENTRY;
|
||||
|
||||
int speed_mode;
|
||||
switch (bus_speed_mode)
|
||||
{
|
||||
case I2C_BS_STANDARD:
|
||||
speed_mode = 1;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"I2C bus speed is not supported.");
|
||||
break;
|
||||
}
|
||||
|
||||
data->slave_handler.on_event = handler->on_event;
|
||||
data->slave_handler.on_receive = handler->on_receive;
|
||||
data->slave_handler.on_transmit = handler->on_transmit;
|
||||
|
||||
i2c->enable = 0;
|
||||
i2c->con = (address_width == 10 ? I2C_CON_10BITADDR_SLAVE : 0) | I2C_CON_SPEED(speed_mode) | I2C_CON_STOP_DET_IFADDRESSED;
|
||||
i2c->ss_scl_hcnt = I2C_SS_SCL_HCNT_COUNT(37);
|
||||
i2c->ss_scl_lcnt = I2C_SS_SCL_LCNT_COUNT(40);
|
||||
i2c->sar = I2C_SAR_ADDRESS(slave_address);
|
||||
i2c->rx_tl = I2C_RX_TL_VALUE(0);
|
||||
i2c->tx_tl = I2C_TX_TL_VALUE(0);
|
||||
i2c->intr_mask = I2C_INTR_MASK_RX_FULL | I2C_INTR_MASK_START_DET | I2C_INTR_MASK_STOP_DET | I2C_INTR_MASK_RD_REQ;
|
||||
|
||||
int i2c_idx = data->clock - SYSCTL_CLOCK_I2C0;
|
||||
pic_set_irq_priority(IRQN_I2C0_INTERRUPT + i2c_idx, 1);
|
||||
pic_set_irq_handler(IRQN_I2C0_INTERRUPT + i2c_idx, on_i2c_irq, userdata);
|
||||
pic_set_irq_enable(IRQN_I2C0_INTERRUPT + i2c_idx, 1);
|
||||
|
||||
i2c->enable = I2C_ENABLE_ENABLE;
|
||||
}
|
||||
|
||||
static i2c_data dev0_data = {SYSCTL_CLOCK_I2C0, SYSCTL_THRESHOLD_I2C0, SYSCTL_DMA_SELECT_I2C0_RX_REQ, I2C0_BASE_ADDR, {0}};
|
||||
static i2c_data dev1_data = {SYSCTL_CLOCK_I2C1, SYSCTL_THRESHOLD_I2C1, SYSCTL_DMA_SELECT_I2C1_RX_REQ, I2C1_BASE_ADDR, {0}};
|
||||
static i2c_data dev2_data = {SYSCTL_CLOCK_I2C2, SYSCTL_THRESHOLD_I2C2, SYSCTL_DMA_SELECT_I2C2_RX_REQ, I2C2_BASE_ADDR, {0}};
|
||||
|
||||
const i2c_driver_t g_i2c_driver_i2c0 = {{&dev0_data, i2c_install, i2c_open, i2c_close}, i2c_get_device, i2c_config_as_slave};
|
||||
const i2c_driver_t g_i2c_driver_i2c1 = {{&dev1_data, i2c_install, i2c_open, i2c_close}, i2c_get_device, i2c_config_as_slave};
|
||||
const i2c_driver_t g_i2c_driver_i2c2 = {{&dev2_data, i2c_install, i2c_open, i2c_close}, i2c_get_device, i2c_config_as_slave};
|
|
@ -0,0 +1,512 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <i2s.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
#define BUFFER_COUNT 2
|
||||
#define COMMON_ENTRY \
|
||||
i2s_data* data = (i2s_data*)userdata; \
|
||||
volatile struct i2s_t* i2s = (volatile struct i2s_t*)data->base_addr; \
|
||||
(void)i2s;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2S_RECEIVE,
|
||||
I2S_SEND
|
||||
} i2s_transmit;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
uintptr_t base_addr;
|
||||
enum sysctl_dma_select_e dma_req_base;
|
||||
enum sysctl_threshold_e clock_threshold;
|
||||
struct
|
||||
{
|
||||
i2s_transmit transmit;
|
||||
char* buffer;
|
||||
size_t buffer_frames;
|
||||
size_t buffer_size;
|
||||
size_t block_align;
|
||||
size_t channels;
|
||||
size_t buffer_ptr;
|
||||
int next_free_buffer;
|
||||
int dma_in_use_buffer;
|
||||
int stop_signal;
|
||||
uintptr_t transmit_dma;
|
||||
SemaphoreHandle_t stage_completion_event;
|
||||
SemaphoreHandle_t completion_event;
|
||||
};
|
||||
} i2s_data;
|
||||
|
||||
static void i2s_transmit_set_enable(i2s_transmit transmit, int enable, volatile struct i2s_t* i2s);
|
||||
static void i2sc_transmit_set_enable(i2s_transmit transmit, int enable, volatile struct i2s_channel_t* i2sc);
|
||||
|
||||
static void i2s_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
/* GPIO clock under APB0 clock, so enable APB0 clock firstly */
|
||||
sysctl_clock_enable(data->clock);
|
||||
|
||||
union ier_u u_ier;
|
||||
|
||||
u_ier.reg_data = readl(&i2s->ier);
|
||||
u_ier.ier.ien = 1;
|
||||
writel(u_ier.reg_data, &i2s->ier);
|
||||
|
||||
data->buffer = NULL;
|
||||
}
|
||||
|
||||
static int i2s_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void i2s_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void i2s_set_threshold(volatile struct i2s_channel_t* i2sc, i2s_transmit transmit, enum fifo_threshold_t threshold)
|
||||
{
|
||||
if (transmit == I2S_RECEIVE)
|
||||
{
|
||||
union rfcr_u u_rfcr;
|
||||
|
||||
u_rfcr.reg_data = readl(&i2sc->rfcr);
|
||||
u_rfcr.rfcr.rxchdt = threshold;
|
||||
writel(u_rfcr.reg_data, &i2sc->rfcr);
|
||||
}
|
||||
else
|
||||
{
|
||||
union tfcr_u u_tfcr;
|
||||
|
||||
u_tfcr.reg_data = readl(&i2sc->tfcr);
|
||||
u_tfcr.tfcr.txchet = threshold;
|
||||
writel(u_tfcr.reg_data, &i2sc->tfcr);
|
||||
}
|
||||
}
|
||||
|
||||
static void i2sc_set_mask_interrupt(volatile struct i2s_channel_t* i2sc,
|
||||
uint32_t rx_available_int, uint32_t rx_overrun_int,
|
||||
uint32_t tx_empty_int, uint32_t tx_overrun_int)
|
||||
{
|
||||
union imr_u u_imr;
|
||||
|
||||
u_imr.reg_data = readl(&i2sc->imr);
|
||||
|
||||
if (rx_available_int == 1)
|
||||
u_imr.imr.rxdam = 1;
|
||||
else
|
||||
u_imr.imr.rxdam = 0;
|
||||
if (rx_overrun_int == 1)
|
||||
u_imr.imr.rxfom = 1;
|
||||
else
|
||||
u_imr.imr.rxfom = 0;
|
||||
|
||||
if (tx_empty_int == 1)
|
||||
u_imr.imr.txfem = 1;
|
||||
else
|
||||
u_imr.imr.txfem = 0;
|
||||
if (tx_overrun_int == 1)
|
||||
u_imr.imr.txfom = 1;
|
||||
else
|
||||
u_imr.imr.txfom = 0;
|
||||
writel(u_imr.reg_data, &i2sc->imr);
|
||||
}
|
||||
|
||||
static void extract_params(const audio_format_t* format, enum word_select_cycles_t* wsc, enum word_length_t* wlen, size_t* block_align, uint32_t* dma_divide16)
|
||||
{
|
||||
configASSERT(format->sample_rate == 44100);
|
||||
|
||||
switch (format->bits_per_sample)
|
||||
{
|
||||
case 16:
|
||||
*wsc = SCLK_CYCLES_32;
|
||||
*wlen = RESOLUTION_16_BIT;
|
||||
*block_align = format->channels * 2;
|
||||
*dma_divide16 = 1;
|
||||
break;
|
||||
case 24:
|
||||
*wsc = SCLK_CYCLES_32;
|
||||
*wlen = RESOLUTION_24_BIT;
|
||||
*block_align = format->channels * 4;
|
||||
*dma_divide16 = 0;
|
||||
break;
|
||||
case 32:
|
||||
*wsc = SCLK_CYCLES_32;
|
||||
*wlen = RESOLUTION_32_BIT;
|
||||
*block_align = format->channels * 4;
|
||||
*dma_divide16 = 0;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invlid bits per sample");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void i2s_config_as_render(const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
data->transmit = I2S_SEND;
|
||||
|
||||
uint32_t am = 0;
|
||||
|
||||
switch (align_mode)
|
||||
{
|
||||
case I2S_AM_STANDARD:
|
||||
am = 0x1;
|
||||
break;
|
||||
case I2S_AM_RIGHT:
|
||||
am = 0x2;
|
||||
break;
|
||||
case I2S_AM_LEFT:
|
||||
am = 0x4;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"I2S align mode not supported.");
|
||||
break;
|
||||
}
|
||||
|
||||
enum word_select_cycles_t wsc;
|
||||
enum word_length_t wlen;
|
||||
size_t block_align;
|
||||
uint32_t dma_divide16;
|
||||
|
||||
extract_params(format, &wsc, &wlen, &block_align, &dma_divide16);
|
||||
|
||||
sysctl_clock_set_threshold(data->clock_threshold, 7);
|
||||
|
||||
i2s_transmit_set_enable(I2S_RECEIVE, 0, userdata);
|
||||
i2s_transmit_set_enable(I2S_SEND, 0, userdata);
|
||||
|
||||
union ccr_u u_ccr;
|
||||
union cer_u u_cer;
|
||||
|
||||
u_cer.reg_data = readl(&i2s->cer);
|
||||
u_cer.cer.clken = 0;
|
||||
writel(u_cer.reg_data, &i2s->cer);
|
||||
|
||||
u_ccr.reg_data = readl(&i2s->ccr);
|
||||
u_ccr.ccr.clk_word_size = wsc;
|
||||
u_ccr.ccr.clk_gate = NO_CLOCK_GATING;
|
||||
u_ccr.ccr.align_mode = am;
|
||||
u_ccr.ccr.dma_tx_en = 1;
|
||||
u_ccr.ccr.sign_expand_en = 1;
|
||||
u_ccr.ccr.dma_divide_16 = dma_divide16;
|
||||
u_ccr.ccr.dma_rx_en = 0;
|
||||
writel(u_ccr.reg_data, &i2s->ccr);
|
||||
|
||||
u_cer.reg_data = readl(&i2s->cer);
|
||||
u_cer.cer.clken = 1;
|
||||
writel(u_cer.reg_data, &i2s->cer);
|
||||
|
||||
writel(1, &i2s->txffr);
|
||||
writel(1, &i2s->rxffr);
|
||||
|
||||
size_t channel = 0;
|
||||
size_t enabled_channel = 0;
|
||||
for (channel = 0; channel < 4; channel++)
|
||||
{
|
||||
volatile struct i2s_channel_t* i2sc = i2s->channel + channel;
|
||||
|
||||
if ((channels_mask & 3) == 3)
|
||||
{
|
||||
i2sc_transmit_set_enable(I2S_SEND, 1, i2sc);
|
||||
i2sc_transmit_set_enable(I2S_RECEIVE, 0, i2sc);
|
||||
i2sc_set_mask_interrupt(i2sc, 0, 0, 1, 1);
|
||||
|
||||
union rcr_tcr_u u_tcr;
|
||||
u_tcr.reg_data = readl(&i2sc->tcr);
|
||||
u_tcr.rcr_tcr.wlen = wlen;
|
||||
writel(u_tcr.reg_data, &i2sc->tcr);
|
||||
|
||||
i2s_set_threshold(i2sc, I2S_SEND, TRIGGER_LEVEL_4);
|
||||
enabled_channel++;
|
||||
}
|
||||
else
|
||||
{
|
||||
i2sc_transmit_set_enable(I2S_SEND, 0, i2sc);
|
||||
i2sc_transmit_set_enable(I2S_RECEIVE, 0, i2sc);
|
||||
}
|
||||
|
||||
channels_mask >>= 2;
|
||||
}
|
||||
|
||||
configASSERT(enabled_channel * 2 == format->channels);
|
||||
|
||||
data->channels = format->channels;
|
||||
data->block_align = block_align;
|
||||
data->buffer_frames = 44100 * delay_ms / 1000;
|
||||
configASSERT(data->buffer_frames >= 100);
|
||||
free(data->buffer);
|
||||
data->buffer_size = data->block_align * data->buffer_frames;
|
||||
data->buffer = (char*)malloc(data->buffer_size * BUFFER_COUNT);
|
||||
data->buffer_ptr = 0;
|
||||
data->next_free_buffer = 0;
|
||||
data->stop_signal = 0;
|
||||
data->transmit_dma = 0;
|
||||
data->dma_in_use_buffer = -1;
|
||||
}
|
||||
|
||||
static void i2s_config_as_capture(const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
data->transmit = I2S_RECEIVE;
|
||||
|
||||
uint32_t am = 0;
|
||||
|
||||
switch (align_mode)
|
||||
{
|
||||
case I2S_AM_STANDARD:
|
||||
am = 0x1;
|
||||
break;
|
||||
case I2S_AM_RIGHT:
|
||||
am = 0x2;
|
||||
break;
|
||||
case I2S_AM_LEFT:
|
||||
am = 0x4;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"I2S align mode not supported.");
|
||||
break;
|
||||
}
|
||||
|
||||
enum word_select_cycles_t wsc;
|
||||
enum word_length_t wlen;
|
||||
size_t block_align;
|
||||
uint32_t dma_divide16;
|
||||
|
||||
configASSERT(format->bits_per_sample != 16);
|
||||
extract_params(format, &wsc, &wlen, &block_align, &dma_divide16);
|
||||
|
||||
sysctl_clock_set_threshold(data->clock_threshold, 7);
|
||||
|
||||
i2s_transmit_set_enable(I2S_RECEIVE, 0, userdata);
|
||||
i2s_transmit_set_enable(I2S_SEND, 0, userdata);
|
||||
|
||||
union ccr_u u_ccr;
|
||||
union cer_u u_cer;
|
||||
|
||||
u_cer.reg_data = readl(&i2s->cer);
|
||||
u_cer.cer.clken = 0;
|
||||
writel(u_cer.reg_data, &i2s->cer);
|
||||
|
||||
u_ccr.reg_data = readl(&i2s->ccr);
|
||||
u_ccr.ccr.clk_word_size = wsc;
|
||||
u_ccr.ccr.clk_gate = NO_CLOCK_GATING;
|
||||
u_ccr.ccr.align_mode = am;
|
||||
u_ccr.ccr.dma_tx_en = 0;
|
||||
u_ccr.ccr.sign_expand_en = 1;
|
||||
u_ccr.ccr.dma_divide_16 = dma_divide16;
|
||||
u_ccr.ccr.dma_rx_en = 1;
|
||||
writel(u_ccr.reg_data, &i2s->ccr);
|
||||
|
||||
u_cer.reg_data = readl(&i2s->cer);
|
||||
u_cer.cer.clken = 1;
|
||||
writel(u_cer.reg_data, &i2s->cer);
|
||||
|
||||
writel(1, &i2s->txffr);
|
||||
writel(1, &i2s->rxffr);
|
||||
|
||||
size_t channel = 0;
|
||||
size_t enabled_channel = 0;
|
||||
for (channel = 0; channel < 4; channel++)
|
||||
{
|
||||
volatile struct i2s_channel_t* i2sc = i2s->channel + channel;
|
||||
|
||||
if ((channels_mask & 3) == 3)
|
||||
{
|
||||
i2sc_transmit_set_enable(I2S_SEND, 0, i2sc);
|
||||
i2sc_transmit_set_enable(I2S_RECEIVE, 1, i2sc);
|
||||
i2sc_set_mask_interrupt(i2sc, 1, 1, 0, 0);
|
||||
|
||||
/* set word length */
|
||||
union rcr_tcr_u u_tcr;
|
||||
u_tcr.reg_data = readl(&i2sc->rcr);
|
||||
u_tcr.rcr_tcr.wlen = wlen;
|
||||
writel(u_tcr.reg_data, &i2sc->rcr);
|
||||
|
||||
i2s_set_threshold(i2sc, I2S_RECEIVE, TRIGGER_LEVEL_4);
|
||||
enabled_channel++;
|
||||
}
|
||||
else
|
||||
{
|
||||
i2sc_transmit_set_enable(I2S_SEND, 0, i2sc);
|
||||
i2sc_transmit_set_enable(I2S_RECEIVE, 0, i2sc);
|
||||
}
|
||||
|
||||
channels_mask >>= 2;
|
||||
}
|
||||
|
||||
configASSERT(enabled_channel * 2 == format->channels);
|
||||
|
||||
data->channels = format->channels;
|
||||
data->block_align = block_align;
|
||||
data->buffer_frames = 44100 * delay_ms / 1000;
|
||||
configASSERT(data->buffer_frames >= 100);
|
||||
free(data->buffer);
|
||||
data->buffer_size = data->block_align * data->buffer_frames;
|
||||
data->buffer = (char*)malloc(data->buffer_size * BUFFER_COUNT);
|
||||
data->buffer_ptr = 0;
|
||||
data->next_free_buffer = 0;
|
||||
data->stop_signal = 0;
|
||||
data->transmit_dma = 0;
|
||||
data->dma_in_use_buffer = 0;
|
||||
}
|
||||
|
||||
static void i2s_get_buffer(char** buffer, size_t* frames, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
while (data->next_free_buffer == data->dma_in_use_buffer)
|
||||
{
|
||||
xSemaphoreTake(data->stage_completion_event, portMAX_DELAY);
|
||||
}
|
||||
|
||||
*buffer = data->buffer + data->buffer_size * data->next_free_buffer + data->buffer_ptr;
|
||||
*frames = (data->buffer_size - data->buffer_ptr) / data->block_align;
|
||||
}
|
||||
|
||||
static void i2s_release_buffer(size_t frames, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
data->buffer_ptr += frames * data->block_align;
|
||||
if (data->buffer_ptr >= data->buffer_size)
|
||||
{
|
||||
data->buffer_ptr = 0;
|
||||
if (++data->next_free_buffer >= BUFFER_COUNT)
|
||||
data->next_free_buffer = 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void i2s_transmit_set_enable(i2s_transmit transmit, int enable, volatile struct i2s_t* i2s)
|
||||
{
|
||||
union irer_u u_irer;
|
||||
union iter_u u_iter;
|
||||
|
||||
if (transmit == I2S_RECEIVE)
|
||||
{
|
||||
u_irer.reg_data = readl(&i2s->irer);
|
||||
u_irer.irer.rxen = enable;
|
||||
writel(u_irer.reg_data, &i2s->irer);
|
||||
}
|
||||
else
|
||||
{
|
||||
u_iter.reg_data = readl(&i2s->iter);
|
||||
u_iter.iter.txen = enable;
|
||||
writel(u_iter.reg_data, &i2s->iter);
|
||||
}
|
||||
}
|
||||
|
||||
static void i2sc_transmit_set_enable(i2s_transmit transmit, int enable, volatile struct i2s_channel_t* i2sc)
|
||||
{
|
||||
union rer_u u_rer;
|
||||
union ter_u u_ter;
|
||||
|
||||
if (transmit == I2S_SEND)
|
||||
{
|
||||
u_ter.reg_data = readl(&i2sc->ter);
|
||||
u_ter.ter.txchenx = enable;
|
||||
writel(u_ter.reg_data, &i2sc->ter);
|
||||
}
|
||||
else
|
||||
{
|
||||
u_rer.reg_data = readl(&i2sc->rer);
|
||||
u_rer.rer.rxchenx = enable;
|
||||
writel(u_rer.reg_data, &i2sc->rer);
|
||||
}
|
||||
}
|
||||
|
||||
static void i2s_stage_completion_isr(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
if (++data->dma_in_use_buffer >= BUFFER_COUNT)
|
||||
data->dma_in_use_buffer = 0;
|
||||
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE;
|
||||
xSemaphoreGiveFromISR(data->stage_completion_event, &xHigherPriorityTaskWoken);
|
||||
}
|
||||
|
||||
static void i2s_start(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
if (data->transmit == I2S_SEND)
|
||||
{
|
||||
configASSERT(!data->transmit_dma);
|
||||
|
||||
data->stop_signal = 0;
|
||||
data->transmit_dma = dma_open_free();
|
||||
dma_set_select_request(data->transmit_dma, data->dma_req_base - 1);
|
||||
data->dma_in_use_buffer = 0;
|
||||
data->stage_completion_event = xSemaphoreCreateCounting(100, 0);
|
||||
data->completion_event = xSemaphoreCreateBinary();
|
||||
|
||||
const volatile void* srcs[BUFFER_COUNT] = {
|
||||
data->buffer,
|
||||
data->buffer + data->buffer_size};
|
||||
volatile void* dests[1] = {
|
||||
&i2s->txdma};
|
||||
|
||||
dma_loop_async(data->transmit_dma, srcs, BUFFER_COUNT, dests, 1, 1, 0, sizeof(uint32_t), data->buffer_size >> 2, 4, i2s_stage_completion_isr, userdata, data->completion_event, &data->stop_signal);
|
||||
}
|
||||
else
|
||||
{
|
||||
configASSERT(!data->transmit_dma);
|
||||
|
||||
data->stop_signal = 0;
|
||||
data->transmit_dma = dma_open_free();
|
||||
dma_set_select_request(data->transmit_dma, data->dma_req_base);
|
||||
data->dma_in_use_buffer = 0;
|
||||
data->stage_completion_event = xSemaphoreCreateCounting(100, 0);
|
||||
data->completion_event = xSemaphoreCreateBinary();
|
||||
|
||||
const volatile void* srcs[1] = {
|
||||
&i2s->rxdma};
|
||||
volatile void* dests[BUFFER_COUNT] = {
|
||||
data->buffer,
|
||||
data->buffer + data->buffer_size};
|
||||
|
||||
dma_loop_async(data->transmit_dma, srcs, 1, dests, BUFFER_COUNT, 0, 1, sizeof(uint32_t), data->buffer_size >> 2, 4, i2s_stage_completion_isr, userdata, data->completion_event, &data->stop_signal);
|
||||
}
|
||||
i2s_transmit_set_enable(data->transmit, 1, i2s);
|
||||
}
|
||||
|
||||
static void i2s_stop(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
i2s_transmit_set_enable(data->transmit, 0, i2s);
|
||||
}
|
||||
|
||||
static i2s_data dev0_data = {SYSCTL_CLOCK_I2S0, I2S0_BASE_ADDR, SYSCTL_DMA_SELECT_I2S0_RX_REQ, SYSCTL_THRESHOLD_I2S0, {0}};
|
||||
static i2s_data dev1_data = {SYSCTL_CLOCK_I2S1, I2S1_BASE_ADDR, SYSCTL_DMA_SELECT_I2S1_RX_REQ, SYSCTL_THRESHOLD_I2S1, {0}};
|
||||
static i2s_data dev2_data = {SYSCTL_CLOCK_I2S2, I2S2_BASE_ADDR, SYSCTL_DMA_SELECT_I2S2_RX_REQ, SYSCTL_THRESHOLD_I2S2, {0}};
|
||||
|
||||
const i2s_driver_t g_i2s_driver_i2s0 = {{&dev0_data, i2s_install, i2s_open, i2s_close}, i2s_config_as_render, i2s_config_as_capture, i2s_get_buffer, i2s_release_buffer, i2s_start, i2s_stop};
|
||||
const i2s_driver_t g_i2s_driver_i2s1 = {{&dev1_data, i2s_install, i2s_open, i2s_close}, i2s_config_as_render, i2s_config_as_capture, i2s_get_buffer, i2s_release_buffer, i2s_start, i2s_stop};
|
||||
const i2s_driver_t g_i2s_driver_i2s2 = {{&dev2_data, i2s_install, i2s_open, i2s_close}, i2s_config_as_render, i2s_config_as_capture, i2s_get_buffer, i2s_release_buffer, i2s_start, i2s_stop};
|
|
@ -0,0 +1,123 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
|
||||
#define plic ((volatile struct plic_t*)PLIC_BASE_ADDR)
|
||||
|
||||
static void plic_install(void* userdata)
|
||||
{
|
||||
int i = 0;
|
||||
size_t hart_id;
|
||||
|
||||
for (hart_id = 0; hart_id < PLIC_NUM_HARTS; hart_id++)
|
||||
{
|
||||
/* Disable all interrupts for the current hart. */
|
||||
for (i = 0; i < ((PLIC_NUM_SOURCES + 32u) / 32u); i++)
|
||||
plic->target_enables.target[hart_id].enable[i] = 0;
|
||||
}
|
||||
|
||||
/* Set priorities to zero. */
|
||||
for (i = 0; i < PLIC_NUM_SOURCES; i++)
|
||||
plic->source_priorities.priority[i] = 0;
|
||||
|
||||
/* Set the threshold to zero. */
|
||||
for (hart_id = 0; hart_id < PLIC_NUM_HARTS; hart_id++)
|
||||
{
|
||||
plic->targets.target[hart_id].priority_threshold = 0;
|
||||
}
|
||||
|
||||
/* Enable machine external interrupts. */
|
||||
set_csr(mie, MIP_MEIP);
|
||||
}
|
||||
|
||||
static int plic_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void plic_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void plic_set_irq_enable(size_t irq, int enable, void* userdata)
|
||||
{
|
||||
configASSERT(irq <= PLIC_NUM_SOURCES);
|
||||
|
||||
/* Get current enable bit array by IRQ number */
|
||||
uint32_t current = plic->target_enables.target[0].enable[irq / 32];
|
||||
/* Set enable bit in enable bit array */
|
||||
if (enable)
|
||||
current |= (uint32_t)1 << (irq % 32);
|
||||
else
|
||||
current &= ~((uint32_t)1 << (irq % 32));
|
||||
/* Write back the enable bit array */
|
||||
plic->target_enables.target[0].enable[irq / 32] = current;
|
||||
}
|
||||
|
||||
static void plic_set_irq_priority(size_t irq, size_t priority, void* userdata)
|
||||
{
|
||||
configASSERT(irq <= PLIC_NUM_SOURCES);
|
||||
/* Set interrupt priority by IRQ number */
|
||||
plic->source_priorities.priority[irq] = priority;
|
||||
}
|
||||
|
||||
static void plic_complete_irq(uint32_t source)
|
||||
{
|
||||
unsigned long hart_id = xPortGetProcessorId();
|
||||
/* Perform IRQ complete */
|
||||
plic->targets.target[hart_id].claim_complete = source;
|
||||
}
|
||||
|
||||
/*Entry Point for PLIC Interrupt Handler*/
|
||||
uintptr_t handle_irq_m_ext(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
|
||||
{
|
||||
/**
|
||||
* After the highest-priority pending interrupt is claimed by a target
|
||||
* and the corresponding IP bit is cleared, other lower-priority
|
||||
* pending interrupts might then become visible to the target, and so
|
||||
* the PLIC EIP bit might not be cleared after a claim. The interrupt
|
||||
* handler can check the local meip/heip/seip/ueip bits before exiting
|
||||
* the handler, to allow more efficient service of other interrupts
|
||||
* without first restoring the interrupted context and taking another
|
||||
* interrupt trap.
|
||||
*/
|
||||
if (read_csr(mip) & MIP_MEIP)
|
||||
{
|
||||
/* Get current hart id */
|
||||
uint64_t hart_id = read_csr(mhartid);
|
||||
uint64_t ie_flag = read_csr(mie);
|
||||
uint32_t int_num = plic->targets.target[hart_id].claim_complete;
|
||||
uint32_t int_threshold = plic->targets.target[hart_id].priority_threshold;
|
||||
|
||||
plic->targets.target[hart_id].priority_threshold = plic->source_priorities.priority[int_num];
|
||||
clear_csr(mie, MIP_MTIP | MIP_MSIP);
|
||||
set_csr(mstatus, MSTATUS_MIE);
|
||||
kernel_iface_pic_on_irq(int_num);
|
||||
plic_complete_irq(int_num);
|
||||
clear_csr(mstatus, MSTATUS_MIE);
|
||||
set_csr(mstatus, MSTATUS_MPIE | MSTATUS_MPP);
|
||||
write_csr(mie, ie_flag);
|
||||
plic->targets.target[hart_id].priority_threshold = int_threshold;
|
||||
}
|
||||
|
||||
return epc;
|
||||
}
|
||||
|
||||
const pic_driver_t g_pic_driver_plic0 = {{NULL, plic_install, plic_open, plic_close}, plic_set_irq_enable, plic_set_irq_priority};
|
|
@ -0,0 +1,98 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
#include <timer.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
pwm_data* data = (pwm_data*)userdata; \
|
||||
volatile struct timer_t* pwm = (volatile struct timer_t*)data->base_addr; \
|
||||
(void)pwm; \
|
||||
(void)data;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
uintptr_t base_addr;
|
||||
size_t pin_count;
|
||||
struct
|
||||
{
|
||||
uint32_t periods;
|
||||
};
|
||||
} pwm_data;
|
||||
|
||||
static void pwm_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
}
|
||||
|
||||
static int pwm_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void pwm_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static double pwm_set_frequency(double frequency, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
uint32_t clk_freq = sysctl_clock_get_freq(data->clock);
|
||||
|
||||
/* frequency = clk_freq / periods */
|
||||
int32_t periods = (int32_t)(clk_freq / frequency);
|
||||
configASSERT(periods > 0 && periods <= INT32_MAX);
|
||||
frequency = clk_freq / (double)periods;
|
||||
data->periods = periods;
|
||||
return frequency;
|
||||
}
|
||||
|
||||
static double pwm_set_active_duty_cycle_percentage(size_t pin, double duty_cycle_percentage, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(pin < data->pin_count);
|
||||
configASSERT(duty_cycle_percentage >= 0 && duty_cycle_percentage <= 1);
|
||||
|
||||
uint32_t percent = (uint32_t)(duty_cycle_percentage * data->periods);
|
||||
pwm->channel[pin].load_count = data->periods - percent;
|
||||
pwm->load_count2[pin] = percent;
|
||||
return percent / 100.0;
|
||||
}
|
||||
|
||||
static void pwm_set_enable(size_t pin, int enable, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(pin < data->pin_count);
|
||||
if (enable)
|
||||
pwm->channel[pin].control = TIMER_CR_INTERRUPT_MASK | TIMER_CR_PWM_ENABLE | TIMER_CR_USER_MODE | TIMER_CR_ENABLE;
|
||||
else
|
||||
pwm->channel[pin].control = TIMER_CR_INTERRUPT_MASK;
|
||||
}
|
||||
|
||||
static pwm_data dev0_data = {SYSCTL_CLOCK_TIMER0, TIMER0_BASE_ADDR, 4, {0}};
|
||||
static pwm_data dev1_data = {SYSCTL_CLOCK_TIMER1, TIMER1_BASE_ADDR, 4, {0}};
|
||||
static pwm_data dev2_data = {SYSCTL_CLOCK_TIMER2, TIMER2_BASE_ADDR, 4, {0}};
|
||||
|
||||
const pwm_driver_t g_pwm_driver_pwm0 = {{&dev0_data, pwm_install, pwm_open, pwm_close}, 4, pwm_set_frequency, pwm_set_active_duty_cycle_percentage, pwm_set_enable};
|
||||
const pwm_driver_t g_pwm_driver_pwm1 = {{&dev1_data, pwm_install, pwm_open, pwm_close}, 4, pwm_set_frequency, pwm_set_active_duty_cycle_percentage, pwm_set_enable};
|
||||
const pwm_driver_t g_pwm_driver_pwm2 = {{&dev2_data, pwm_install, pwm_open, pwm_close}, 4, pwm_set_frequency, pwm_set_active_duty_cycle_percentage, pwm_set_enable};
|
|
@ -0,0 +1,144 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <driver.h>
|
||||
|
||||
/* System Drivers */
|
||||
|
||||
extern const uart_driver_t g_uart_driver_uart0;
|
||||
extern const uart_driver_t g_uart_driver_uart1;
|
||||
extern const uart_driver_t g_uart_driver_uart2;
|
||||
|
||||
extern const gpio_driver_t g_gpio_driver_gpio0;
|
||||
extern const gpio_driver_t g_gpiohs_driver_gpio0;
|
||||
|
||||
extern const i2c_driver_t g_i2c_driver_i2c0;
|
||||
extern const i2c_driver_t g_i2c_driver_i2c1;
|
||||
extern const i2c_driver_t g_i2c_driver_i2c2;
|
||||
|
||||
extern const i2s_driver_t g_i2s_driver_i2s0;
|
||||
extern const i2s_driver_t g_i2s_driver_i2s1;
|
||||
extern const i2s_driver_t g_i2s_driver_i2s2;
|
||||
|
||||
extern const spi_driver_t g_spi_driver_spi0;
|
||||
extern const spi_driver_t g_spi_driver_spi1;
|
||||
extern const spi_driver_t g_spi_driver_spi3;
|
||||
|
||||
extern const sccb_driver_t g_sccb_driver_sccb0;
|
||||
|
||||
extern const dvp_driver_t g_dvp_driver_dvp0;
|
||||
|
||||
extern const fft_driver_t g_fft_driver_fft0;
|
||||
|
||||
extern const aes_driver_t g_aes_driver_aes0;
|
||||
|
||||
extern const sha256_driver_t g_sha_driver_sha256;
|
||||
|
||||
extern const timer_driver_t g_timer_driver_timer0;
|
||||
extern const timer_driver_t g_timer_driver_timer1;
|
||||
extern const timer_driver_t g_timer_driver_timer2;
|
||||
extern const timer_driver_t g_timer_driver_timer3;
|
||||
extern const timer_driver_t g_timer_driver_timer4;
|
||||
extern const timer_driver_t g_timer_driver_timer5;
|
||||
extern const timer_driver_t g_timer_driver_timer6;
|
||||
extern const timer_driver_t g_timer_driver_timer7;
|
||||
extern const timer_driver_t g_timer_driver_timer8;
|
||||
extern const timer_driver_t g_timer_driver_timer9;
|
||||
extern const timer_driver_t g_timer_driver_timer10;
|
||||
extern const timer_driver_t g_timer_driver_timer11;
|
||||
|
||||
extern const pwm_driver_t g_pwm_driver_pwm0;
|
||||
extern const pwm_driver_t g_pwm_driver_pwm1;
|
||||
extern const pwm_driver_t g_pwm_driver_pwm2;
|
||||
|
||||
driver_registry_t g_system_drivers[] =
|
||||
{
|
||||
{"/dev/uart1", &g_uart_driver_uart0, DRIVER_UART},
|
||||
{"/dev/uart2", &g_uart_driver_uart1, DRIVER_UART},
|
||||
{"/dev/uart3", &g_uart_driver_uart2, DRIVER_UART},
|
||||
|
||||
{"/dev/gpio0", &g_gpiohs_driver_gpio0, DRIVER_GPIO},
|
||||
{"/dev/gpio1", &g_gpio_driver_gpio0, DRIVER_GPIO},
|
||||
|
||||
{"/dev/i2c0", &g_i2c_driver_i2c0, DRIVER_I2C},
|
||||
{"/dev/i2c1", &g_i2c_driver_i2c1, DRIVER_I2C},
|
||||
{"/dev/i2c2", &g_i2c_driver_i2c2, DRIVER_I2C},
|
||||
|
||||
{"/dev/i2s0", &g_i2s_driver_i2s0, DRIVER_I2S},
|
||||
{"/dev/i2s1", &g_i2s_driver_i2s1, DRIVER_I2S},
|
||||
{"/dev/i2s2", &g_i2s_driver_i2s2, DRIVER_I2S},
|
||||
|
||||
{"/dev/spi0", &g_spi_driver_spi0, DRIVER_SPI},
|
||||
{"/dev/spi1", &g_spi_driver_spi1, DRIVER_SPI},
|
||||
{"/dev/spi3", &g_spi_driver_spi3, DRIVER_SPI},
|
||||
|
||||
{"/dev/sccb0", &g_sccb_driver_sccb0, DRIVER_SCCB},
|
||||
|
||||
{"/dev/dvp0", &g_dvp_driver_dvp0, DRIVER_DVP},
|
||||
|
||||
{"/dev/fft0", &g_fft_driver_fft0, DRIVER_FFT},
|
||||
|
||||
{"/dev/aes0", &g_aes_driver_aes0, DRIVER_AES},
|
||||
|
||||
{"/dev/sha256", &g_sha_driver_sha256, DRIVER_SHA256},
|
||||
|
||||
{"/dev/timer0", &g_timer_driver_timer0, DRIVER_TIMER},
|
||||
{"/dev/timer1", &g_timer_driver_timer1, DRIVER_TIMER},
|
||||
{"/dev/timer2", &g_timer_driver_timer2, DRIVER_TIMER},
|
||||
{"/dev/timer3", &g_timer_driver_timer3, DRIVER_TIMER},
|
||||
{"/dev/timer4", &g_timer_driver_timer4, DRIVER_TIMER},
|
||||
{"/dev/timer5", &g_timer_driver_timer5, DRIVER_TIMER},
|
||||
{"/dev/timer6", &g_timer_driver_timer6, DRIVER_TIMER},
|
||||
{"/dev/timer7", &g_timer_driver_timer7, DRIVER_TIMER},
|
||||
{"/dev/timer8", &g_timer_driver_timer8, DRIVER_TIMER},
|
||||
{"/dev/timer9", &g_timer_driver_timer9, DRIVER_TIMER},
|
||||
{"/dev/timer10", &g_timer_driver_timer10, DRIVER_TIMER},
|
||||
{"/dev/timer11", &g_timer_driver_timer11, DRIVER_TIMER},
|
||||
|
||||
{"/dev/pwm0", &g_pwm_driver_pwm0, DRIVER_PWM},
|
||||
{"/dev/pwm1", &g_pwm_driver_pwm1, DRIVER_PWM},
|
||||
{"/dev/pwm2", &g_pwm_driver_pwm2, DRIVER_PWM},
|
||||
{0}
|
||||
};
|
||||
|
||||
/* HAL Drivers */
|
||||
|
||||
extern const pic_driver_t g_pic_driver_plic0;
|
||||
extern const dmac_driver_t g_dmac_driver_dmac0;
|
||||
|
||||
driver_registry_t g_hal_drivers[] =
|
||||
{
|
||||
{"/dev/pic0", &g_pic_driver_plic0, DRIVER_PIC},
|
||||
{"/dev/dmac0", &g_dmac_driver_dmac0, DRIVER_DMAC},
|
||||
{0}
|
||||
};
|
||||
|
||||
/* DMA Drivers */
|
||||
|
||||
extern const dma_driver_t g_dma_driver_dma0;
|
||||
extern const dma_driver_t g_dma_driver_dma1;
|
||||
extern const dma_driver_t g_dma_driver_dma2;
|
||||
extern const dma_driver_t g_dma_driver_dma3;
|
||||
extern const dma_driver_t g_dma_driver_dma4;
|
||||
extern const dma_driver_t g_dma_driver_dma5;
|
||||
driver_registry_t g_dma_drivers[] =
|
||||
{
|
||||
{"/dev/dmac0/0", &g_dma_driver_dma0, DRIVER_DMA},
|
||||
{"/dev/dmac0/1", &g_dma_driver_dma1, DRIVER_DMA},
|
||||
{"/dev/dmac0/2", &g_dma_driver_dma2, DRIVER_DMA},
|
||||
{"/dev/dmac0/3", &g_dma_driver_dma3, DRIVER_DMA},
|
||||
{"/dev/dmac0/4", &g_dma_driver_dma4, DRIVER_DMA},
|
||||
{"/dev/dmac0/5", &g_dma_driver_dma5, DRIVER_DMA},
|
||||
{0}
|
||||
};
|
|
@ -0,0 +1,185 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <dvp.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <io.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
/* SCCB Controller */
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
sccb_data* data = (sccb_data*)userdata; \
|
||||
volatile struct dvp_t* sccb = (volatile struct dvp_t*)data->base_addr; \
|
||||
(void)sccb;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
uintptr_t base_addr;
|
||||
SemaphoreHandle_t free_mutex;
|
||||
} sccb_data;
|
||||
|
||||
static void sccb_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
sysctl_clock_enable(data->clock);
|
||||
set_bit_mask(&sccb->sccb_cfg, DVP_SCCB_SCL_LCNT_MASK | DVP_SCCB_SCL_HCNT_MASK, DVP_SCCB_SCL_LCNT(500) | DVP_SCCB_SCL_HCNT(500));
|
||||
|
||||
data->free_mutex = xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
static int sccb_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void sccb_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
/* SCCB Device */
|
||||
|
||||
#define COMMON_DEV_ENTRY \
|
||||
sccb_dev_data* dev_data = (sccb_dev_data*)userdata; \
|
||||
sccb_data* data = (sccb_data*)dev_data->sccb_data; \
|
||||
volatile struct dvp_t* sccb = (volatile struct dvp_t*)data->base_addr;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
sccb_data* sccb_data;
|
||||
size_t slaveAddress;
|
||||
size_t address_width;
|
||||
} sccb_dev_data;
|
||||
|
||||
static void sccb_dev_install(void* userdata);
|
||||
static int sccb_dev_open(void* userdata);
|
||||
static void sccb_dev_close(void* userdata);
|
||||
static uint8_t sccb_dev_read_byte(uint16_t reg_address, void* userdata);
|
||||
static void sccb_dev_write_byte(uint16_t reg_address, uint8_t value, void* userdata);
|
||||
|
||||
static sccb_device_driver_t* sccb_get_device(size_t slaveAddress, size_t address_width, void* userdata)
|
||||
{
|
||||
configASSERT(address_width == 8 || address_width == 16);
|
||||
|
||||
sccb_device_driver_t* driver = (sccb_device_driver_t*)malloc(sizeof(sccb_device_driver_t));
|
||||
memset(driver, 0, sizeof(sccb_device_driver_t));
|
||||
|
||||
sccb_dev_data* dev_data = (sccb_dev_data*)malloc(sizeof(sccb_dev_data));
|
||||
dev_data->slaveAddress = slaveAddress;
|
||||
dev_data->address_width = address_width;
|
||||
dev_data->sccb_data = userdata;
|
||||
|
||||
driver->base.userdata = dev_data;
|
||||
driver->base.install = sccb_dev_install;
|
||||
driver->base.open = sccb_dev_open;
|
||||
driver->base.close = sccb_dev_close;
|
||||
driver->read_byte = sccb_dev_read_byte;
|
||||
driver->write_byte = sccb_dev_write_byte;
|
||||
return driver;
|
||||
}
|
||||
|
||||
static void entry_exclusive(sccb_dev_data* dev_data)
|
||||
{
|
||||
sccb_data* data = (sccb_data*)dev_data->sccb_data;
|
||||
configASSERT(xSemaphoreTake(data->free_mutex, portMAX_DELAY) == pdTRUE);
|
||||
}
|
||||
|
||||
static void exit_exclusive(sccb_dev_data* dev_data)
|
||||
{
|
||||
sccb_data* data = (sccb_data*)dev_data->sccb_data;
|
||||
xSemaphoreGive(data->free_mutex);
|
||||
}
|
||||
|
||||
static void sccb_dev_install(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static int sccb_dev_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void sccb_dev_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void dvp_sccb_start_transfer(volatile struct dvp_t* dvp)
|
||||
{
|
||||
while (dvp->sts & DVP_STS_SCCB_EN)
|
||||
;
|
||||
dvp->sts = DVP_STS_SCCB_EN | DVP_STS_SCCB_EN_WE;
|
||||
while (dvp->sts & DVP_STS_SCCB_EN)
|
||||
;
|
||||
}
|
||||
|
||||
static uint8_t sccb_dev_read_byte(uint16_t reg_address, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
|
||||
if (dev_data->address_width == 8)
|
||||
{
|
||||
set_bit_mask(&sccb->sccb_cfg, DVP_SCCB_BYTE_NUM_MASK, DVP_SCCB_BYTE_NUM_2);
|
||||
sccb->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_data->slaveAddress) | DVP_SCCB_REG_ADDRESS(reg_address);
|
||||
}
|
||||
else
|
||||
{
|
||||
set_bit_mask(&sccb->sccb_cfg, DVP_SCCB_BYTE_NUM_MASK, DVP_SCCB_BYTE_NUM_3);
|
||||
sccb->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_data->slaveAddress) | DVP_SCCB_REG_ADDRESS(reg_address >> 8) | DVP_SCCB_WDATA_BYTE0(reg_address & 0xFF);
|
||||
}
|
||||
|
||||
dvp_sccb_start_transfer(sccb);
|
||||
sccb->sccb_ctl = DVP_SCCB_DEVICE_ADDRESS(dev_data->slaveAddress);
|
||||
dvp_sccb_start_transfer(sccb);
|
||||
|
||||
uint8_t ret = DVP_SCCB_RDATA_BYTE(sccb->sccb_cfg);
|
||||
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void sccb_dev_write_byte(uint16_t reg_address, uint8_t value, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
|
||||
if (dev_data->address_width == 8)
|
||||
{
|
||||
set_bit_mask(&sccb->sccb_cfg, DVP_SCCB_BYTE_NUM_MASK, DVP_SCCB_BYTE_NUM_3);
|
||||
sccb->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_data->slaveAddress) | DVP_SCCB_REG_ADDRESS(reg_address) | DVP_SCCB_WDATA_BYTE0(value);
|
||||
}
|
||||
else
|
||||
{
|
||||
set_bit_mask(&sccb->sccb_cfg, DVP_SCCB_BYTE_NUM_MASK, DVP_SCCB_BYTE_NUM_4);
|
||||
sccb->sccb_ctl = DVP_SCCB_WRITE_ENABLE | DVP_SCCB_DEVICE_ADDRESS(dev_data->slaveAddress) | DVP_SCCB_REG_ADDRESS(reg_address >> 8) | DVP_SCCB_WDATA_BYTE0(reg_address & 0xFF) | DVP_SCCB_WDATA_BYTE1(value);
|
||||
}
|
||||
|
||||
dvp_sccb_start_transfer(sccb);
|
||||
|
||||
exit_exclusive(dev_data);
|
||||
}
|
||||
|
||||
static sccb_data dev0_data = {SYSCTL_CLOCK_DVP, DVP_BASE_ADDR, NULL};
|
||||
|
||||
const sccb_driver_t g_sccb_driver_sccb0 = {{&dev0_data, sccb_install, sccb_open, sccb_close}, sccb_get_device};
|
|
@ -0,0 +1,197 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <dmac.h>
|
||||
#include <driver.h>
|
||||
#include <hal.h>
|
||||
#include <io.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <sha256.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
|
||||
#define ROTL(x, n) (((x) << (n)) | ((x) >> (32 - (n))))
|
||||
#define ROTR(x, n) (((x) >> (n)) | ((x) << (32 - (n))))
|
||||
#define BYTESWAP(x) ((ROTR((x), 8) & 0xff00ff00L) | (ROTL((x), 8) & 0x00ff00ffL))
|
||||
#define BYTESWAP64(x) byteswap64(x)
|
||||
#define COMMON_ENTRY \
|
||||
sha256_dev_data* data = (sha256_dev_data*)userdata; \
|
||||
volatile struct sha256_t* sha256 = (volatile struct sha256_t*)data->base_addr; \
|
||||
(void)sha256;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uintptr_t base_addr;
|
||||
SemaphoreHandle_t free_mutex;
|
||||
} sha256_dev_data;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint64_t total_length;
|
||||
uint32_t hash[SHA256_HASH_WORDS];
|
||||
uint32_t dma_buf_length;
|
||||
uint32_t* dma_buf;
|
||||
uint32_t buffer_length;
|
||||
union
|
||||
{
|
||||
uint32_t words[16];
|
||||
uint8_t bytes[64];
|
||||
} buffer;
|
||||
} sha256_context;
|
||||
|
||||
static const uint8_t padding[64] =
|
||||
{
|
||||
0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00
|
||||
};
|
||||
|
||||
static inline uint64_t byteswap64(uint64_t x)
|
||||
{
|
||||
uint32_t a = x >> 32;
|
||||
uint32_t b = (uint32_t)x;
|
||||
|
||||
return ((uint64_t)BYTESWAP(b) << 32) | (uint64_t)BYTESWAP(a);
|
||||
}
|
||||
|
||||
static void sha256_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_SHA);
|
||||
sysctl_reset(SYSCTL_RESET_SHA);
|
||||
data->free_mutex = xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
static int sha256_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void sha256_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static void entry_exclusive(sha256_dev_data* data)
|
||||
{
|
||||
configASSERT(xSemaphoreTake(data->free_mutex, portMAX_DELAY) == pdTRUE);
|
||||
}
|
||||
|
||||
static void exit_exclusive(sha256_dev_data* data)
|
||||
{
|
||||
xSemaphoreGive(data->free_mutex);
|
||||
}
|
||||
|
||||
static void sha256_update_buf(sha256_context* sc, const void* vdata, uint32_t len)
|
||||
{
|
||||
const uint8_t* data = vdata;
|
||||
uint32_t buffer_bytes_left;
|
||||
uint32_t bytes_to_copy;
|
||||
uint32_t i;
|
||||
|
||||
while (len)
|
||||
{
|
||||
buffer_bytes_left = 64L - sc->buffer_length;
|
||||
|
||||
bytes_to_copy = buffer_bytes_left;
|
||||
if (bytes_to_copy > len)
|
||||
bytes_to_copy = len;
|
||||
|
||||
memcpy(&sc->buffer.bytes[sc->buffer_length], data, bytes_to_copy);
|
||||
|
||||
sc->total_length += bytes_to_copy * 8L;
|
||||
|
||||
sc->buffer_length += bytes_to_copy;
|
||||
data += bytes_to_copy;
|
||||
len -= bytes_to_copy;
|
||||
|
||||
if (sc->buffer_length == 64L)
|
||||
{
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
sc->dma_buf[sc->dma_buf_length++] = sc->buffer.words[i];
|
||||
}
|
||||
sc->buffer_length = 0L;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void sha256_final_buf(sha256_context* sc)
|
||||
{
|
||||
uint32_t bytes_to_pad;
|
||||
uint64_t length_pad;
|
||||
|
||||
bytes_to_pad = 120L - sc->buffer_length;
|
||||
|
||||
if (bytes_to_pad > 64L)
|
||||
bytes_to_pad -= 64L;
|
||||
length_pad = BYTESWAP64(sc->total_length);
|
||||
sha256_update_buf(sc, padding, bytes_to_pad);
|
||||
sha256_update_buf(sc, &length_pad, 8L);
|
||||
}
|
||||
|
||||
static void sha256_str(const char* str, size_t length, uint8_t* hash, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
entry_exclusive(data);
|
||||
int i = 0;
|
||||
sha256_context sha;
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_SHA);
|
||||
sysctl_reset(SYSCTL_RESET_SHA);
|
||||
|
||||
sha256->reserved0 = 0;
|
||||
sha256->sha_status |= 1 << 16; /*!< 0 for little endian, 1 for big endian */
|
||||
sha256->sha_status |= 1; /*!< enable sha256 */
|
||||
sha256->sha_data_num = (length + 64 + 8) / 64;
|
||||
sha.dma_buf = (uint32_t*)malloc((length + 64 + 8) / 64 * 16 * sizeof(uint32_t));
|
||||
sha.buffer_length = 0L;
|
||||
sha.dma_buf_length = 0L;
|
||||
sha.total_length = 0LL;
|
||||
for (i = 0; i < (sizeof(sha.dma_buf) / 4); i++)
|
||||
sha.dma_buf[i] = 0;
|
||||
sha256_update_buf(&sha, str, length);
|
||||
sha256_final_buf(&sha);
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
|
||||
dma_set_select_request(dma_write, SYSCTL_DMA_SELECT_SHA_RX_REQ);
|
||||
|
||||
SemaphoreHandle_t event_write = xSemaphoreCreateBinary();
|
||||
|
||||
dma_transmit_async(dma_write, sha.dma_buf, &sha256->sha_data_in1, 1, 0, sizeof(uint32_t), sha.dma_buf_length, 16, event_write);
|
||||
sha256->sha_input_ctrl |= 1; /*!< dma enable */
|
||||
configASSERT(xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
while (!(sha256->sha_status & 0x01))
|
||||
;
|
||||
for (i = 0; i < SHA256_HASH_WORDS; i++)
|
||||
*((uint32_t*)&hash[i * 4]) = sha256->sha_result[SHA256_HASH_WORDS - i - 1];
|
||||
free(sha.dma_buf);
|
||||
dma_close(dma_write);
|
||||
vSemaphoreDelete(event_write);
|
||||
|
||||
exit_exclusive(data);
|
||||
}
|
||||
|
||||
static sha256_dev_data dev0_data = {SHA256_BASE_ADDR, 0};
|
||||
|
||||
const sha256_driver_t g_sha_driver_sha256 = {{&dev0_data, sha256_install, sha256_open, sha256_close}, sha256_str};
|
|
@ -0,0 +1,512 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <io.h>
|
||||
#include <math.h>
|
||||
#include <semphr.h>
|
||||
#include <spi.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
/* SPI Controller */
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
spi_data* data = (spi_data*)userdata; \
|
||||
volatile struct spi_t* spi = (volatile struct spi_t*)data->base_addr; \
|
||||
(void)spi;
|
||||
|
||||
#define TMOD_MASK (3 << data->tmod_off)
|
||||
#define TMOD_VALUE(value) (value << data->tmod_off)
|
||||
#define min(a, b) ((a) < (b) ? (a) : (b))
|
||||
#define max(a, b) ((a) > (b) ? (a) : (b))
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
uintptr_t base_addr;
|
||||
uint8_t dfs_off;
|
||||
uint8_t tmod_off;
|
||||
uint8_t frf_off;
|
||||
enum sysctl_dma_select_e dma_req_base;
|
||||
|
||||
struct
|
||||
{
|
||||
spi_frame_format frame_format;
|
||||
size_t chip_select_line;
|
||||
size_t buffer_width;
|
||||
size_t inst_width;
|
||||
size_t addr_width;
|
||||
SemaphoreHandle_t free_mutex;
|
||||
};
|
||||
} spi_data;
|
||||
|
||||
static void spi_install(void* userdata)
|
||||
{
|
||||
spi_data* data = (spi_data*)userdata;
|
||||
|
||||
/* GPIO clock under APB0 clock, so enable APB0 clock firstly */
|
||||
sysctl_clock_enable(data->clock);
|
||||
data->free_mutex = xSemaphoreCreateMutex();
|
||||
}
|
||||
|
||||
static int spi_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void spi_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
/* SPI Device */
|
||||
|
||||
#define COMMON_DEV_ENTRY \
|
||||
spi_dev_data* dev_data = (spi_dev_data*)userdata; \
|
||||
spi_data* data = (spi_data*)dev_data->spi_data;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
spi_data* spi_data;
|
||||
spi_mode mode;
|
||||
spi_frame_format frame_format;
|
||||
size_t chip_select_line;
|
||||
size_t data_bit_length;
|
||||
size_t instruction_length;
|
||||
size_t address_length;
|
||||
size_t wait_cycles;
|
||||
spi_addr_inst_trans_mode trans_mode;
|
||||
uint32_t baud_rate;
|
||||
} spi_dev_data;
|
||||
|
||||
static void spi_dev_install(void* userdata);
|
||||
static int spi_dev_open(void* userdata);
|
||||
static void spi_dev_close(void* userdata);
|
||||
static int spi_dev_read(char* buffer, size_t len, void* userdata);
|
||||
static int spi_dev_write(const char* buffer, size_t len, void* userdata);
|
||||
static void spi_dev_config(size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode trans_mode, void* userdata);
|
||||
static double spi_dev_set_speed(double speed, void* userdata);
|
||||
static int spi_dev_transfer_sequential(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
static int spi_dev_transfer_full_duplex(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
static void spi_dev_fill(size_t instruction, size_t address, uint32_t value, size_t count, void* userdata);
|
||||
|
||||
static spi_device_driver_t* spi_get_device(spi_mode mode, spi_frame_format frame_format, size_t chip_select_line, size_t data_bit_length, void* userdata)
|
||||
{
|
||||
spi_device_driver_t* driver = (spi_device_driver_t*)malloc(sizeof(spi_device_driver_t));
|
||||
memset(driver, 0, sizeof(spi_device_driver_t));
|
||||
|
||||
spi_dev_data* dev_data = (spi_dev_data*)malloc(sizeof(spi_dev_data));
|
||||
dev_data->spi_data = userdata;
|
||||
dev_data->mode = mode;
|
||||
dev_data->frame_format = frame_format;
|
||||
dev_data->chip_select_line = chip_select_line;
|
||||
dev_data->data_bit_length = data_bit_length;
|
||||
dev_data->baud_rate = 0x2;
|
||||
|
||||
driver->base.userdata = dev_data;
|
||||
driver->base.install = spi_dev_install;
|
||||
driver->base.open = spi_dev_open;
|
||||
driver->base.close = spi_dev_close;
|
||||
driver->read = spi_dev_read;
|
||||
driver->write = spi_dev_write;
|
||||
driver->config = spi_dev_config;
|
||||
driver->set_speed = spi_dev_set_speed;
|
||||
driver->transfer_sequential = spi_dev_transfer_sequential;
|
||||
driver->transfer_full_duplex = spi_dev_transfer_full_duplex;
|
||||
driver->fill = spi_dev_fill;
|
||||
return driver;
|
||||
}
|
||||
|
||||
static int get_buffer_width(size_t data_bit_length)
|
||||
{
|
||||
if (data_bit_length <= 8)
|
||||
return 1;
|
||||
else if (data_bit_length <= 16)
|
||||
return 2;
|
||||
return 4;
|
||||
}
|
||||
|
||||
static int get_inst_addr_width(size_t length)
|
||||
{
|
||||
if (length == 0)
|
||||
return 0;
|
||||
else if (length <= 8)
|
||||
return 1;
|
||||
else if (length <= 16)
|
||||
return 2;
|
||||
else if (length <= 24)
|
||||
return 3;
|
||||
return 4;
|
||||
}
|
||||
|
||||
static void spi_config_as_master(spi_mode mode, spi_frame_format frame_format, size_t chip_select_line, size_t data_bit_length, uint32_t baud_rate, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(data_bit_length >= 4 && data_bit_length <= 32);
|
||||
configASSERT(chip_select_line);
|
||||
|
||||
switch (frame_format)
|
||||
{
|
||||
case SPI_FF_DUAL:
|
||||
configASSERT(data_bit_length % 2 == 0);
|
||||
break;
|
||||
case SPI_FF_QUAD:
|
||||
configASSERT(data_bit_length % 4 == 0);
|
||||
break;
|
||||
case SPI_FF_OCTAL:
|
||||
configASSERT(data_bit_length % 8 == 0);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
spi->baudr = baud_rate;
|
||||
spi->imr = 0x00;
|
||||
spi->dmacr = 0x00;
|
||||
spi->dmatdlr = 0x10;
|
||||
spi->dmardlr = 0x0;
|
||||
spi->ser = 0x00;
|
||||
spi->ssienr = 0x00;
|
||||
spi->ctrlr0 = (mode << 6) | (frame_format << data->frf_off) | ((data_bit_length - 1) << data->dfs_off);
|
||||
spi->spi_ctrlr0 = 0;
|
||||
|
||||
data->chip_select_line = chip_select_line;
|
||||
data->frame_format = frame_format;
|
||||
data->buffer_width = get_buffer_width(data_bit_length);
|
||||
data->inst_width = 0;
|
||||
data->addr_width = 0;
|
||||
}
|
||||
|
||||
static void spi_config(size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode trans_mode, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(data->frame_format != SPI_FF_STANDARD);
|
||||
configASSERT(wait_cycles < (1 << 5));
|
||||
|
||||
uint32_t inst_l = 0;
|
||||
switch (instruction_length)
|
||||
{
|
||||
case 0:
|
||||
inst_l = 0;
|
||||
break;
|
||||
case 4:
|
||||
inst_l = 1;
|
||||
break;
|
||||
case 8:
|
||||
inst_l = 2;
|
||||
break;
|
||||
case 16:
|
||||
inst_l = 3;
|
||||
break;
|
||||
default:
|
||||
configASSERT("Invalid instruction length");
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t trans = 0;
|
||||
switch (trans_mode)
|
||||
{
|
||||
case SPI_AITM_STANDARD:
|
||||
trans = 0;
|
||||
break;
|
||||
case SPI_AITM_ADDR_STANDARD:
|
||||
trans = 1;
|
||||
break;
|
||||
case SPI_AITM_AS_FRAME_FORMAT:
|
||||
trans = 2;
|
||||
break;
|
||||
default:
|
||||
configASSERT("Invalid trans mode");
|
||||
break;
|
||||
}
|
||||
|
||||
configASSERT(address_length % 4 == 0 && address_length <= 60);
|
||||
uint32_t addr_l = address_length / 4;
|
||||
|
||||
spi->spi_ctrlr0 = (wait_cycles << 11) | (inst_l << 8) | (addr_l << 2) | trans;
|
||||
data->inst_width = get_inst_addr_width(instruction_length);
|
||||
data->addr_width = get_inst_addr_width(address_length);
|
||||
}
|
||||
|
||||
static void write_inst_addr(volatile uint32_t* dr, const char** buffer, size_t width)
|
||||
{
|
||||
configASSERT(width <= 4);
|
||||
if (width)
|
||||
{
|
||||
uint32_t cmd = 0;
|
||||
char* pcmd = (char*)&cmd;
|
||||
size_t i;
|
||||
for (i = 0; i < width; i++)
|
||||
{
|
||||
pcmd[i] = **buffer;
|
||||
++(*buffer);
|
||||
}
|
||||
|
||||
*dr = cmd;
|
||||
}
|
||||
}
|
||||
|
||||
static int spi_read(char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
size_t frames = len / data->buffer_width;
|
||||
uintptr_t dma_read = dma_open_free();
|
||||
dma_set_select_request(dma_read, data->dma_req_base);
|
||||
|
||||
char* ori_buffer = buffer;
|
||||
|
||||
set_bit_mask(&spi->ctrlr0, TMOD_MASK, TMOD_VALUE(2));
|
||||
spi->ctrlr1 = frames - 1;
|
||||
spi->dmacr = 0x1;
|
||||
spi->ssienr = 0x01;
|
||||
|
||||
SemaphoreHandle_t event_read = xSemaphoreCreateBinary();
|
||||
|
||||
dma_transmit_async(dma_read, &spi->dr[0], ori_buffer, 0, 1, data->buffer_width, frames, 1, event_read);
|
||||
|
||||
write_inst_addr(spi->dr, (const char**)&buffer, data->inst_width);
|
||||
write_inst_addr(spi->dr, (const char**)&buffer, data->addr_width);
|
||||
spi->ser = data->chip_select_line;
|
||||
|
||||
configASSERT(xSemaphoreTake(event_read, portMAX_DELAY) == pdTRUE);
|
||||
dma_close(dma_read);
|
||||
vSemaphoreDelete(event_read);
|
||||
|
||||
spi->ser = 0x00;
|
||||
spi->ssienr = 0x00;
|
||||
spi->dmacr = 0x00;
|
||||
return len;
|
||||
}
|
||||
|
||||
static int spi_write(const char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
dma_set_select_request(dma_write, data->dma_req_base + 1);
|
||||
|
||||
set_bit_mask(&spi->ctrlr0, TMOD_MASK, TMOD_VALUE(1));
|
||||
spi->dmacr = 0x2;
|
||||
spi->ssienr = 0x01;
|
||||
|
||||
write_inst_addr(spi->dr, &buffer, data->inst_width);
|
||||
write_inst_addr(spi->dr, &buffer, data->addr_width);
|
||||
|
||||
size_t frames = (len - (data->inst_width + data->addr_width)) / data->buffer_width;
|
||||
SemaphoreHandle_t event_write = xSemaphoreCreateBinary();
|
||||
dma_transmit_async(dma_write, buffer, &spi->dr[0], 1, 0, data->buffer_width, frames, 4, event_write);
|
||||
|
||||
spi->ser = data->chip_select_line;
|
||||
configASSERT(xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
dma_close(dma_write);
|
||||
vSemaphoreDelete(event_write);
|
||||
|
||||
while ((spi->sr & 0x05) != 0x04)
|
||||
;
|
||||
spi->ser = 0x00;
|
||||
spi->ssienr = 0x00;
|
||||
spi->dmacr = 0x00;
|
||||
return len;
|
||||
}
|
||||
|
||||
void spi_fill(size_t instruction, size_t address, uint32_t value, size_t count, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
dma_set_select_request(dma_write, data->dma_req_base + 1);
|
||||
|
||||
set_bit_mask(&spi->ctrlr0, TMOD_MASK, TMOD_VALUE(1));
|
||||
spi->dmacr = 0x2;
|
||||
spi->ssienr = 0x01;
|
||||
|
||||
const char* buffer = (const char*)&instruction;
|
||||
write_inst_addr(spi->dr, &buffer, data->inst_width);
|
||||
buffer = (const char*)&address;
|
||||
write_inst_addr(spi->dr, &buffer, data->addr_width);
|
||||
|
||||
SemaphoreHandle_t event_write = xSemaphoreCreateBinary();
|
||||
dma_transmit_async(dma_write, &value, &spi->dr[0], 0, 0, sizeof(uint32_t), count, 4, event_write);
|
||||
|
||||
spi->ser = data->chip_select_line;
|
||||
configASSERT(xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
dma_close(dma_write);
|
||||
vSemaphoreDelete(event_write);
|
||||
|
||||
while ((spi->sr & 0x05) != 0x04)
|
||||
;
|
||||
spi->ser = 0x00;
|
||||
spi->ssienr = 0x00;
|
||||
spi->dmacr = 0x00;
|
||||
}
|
||||
|
||||
static int spi_read_write(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(data->frame_format == SPI_FF_STANDARD);
|
||||
|
||||
uintptr_t dma_write = dma_open_free();
|
||||
uintptr_t dma_read = dma_open_free();
|
||||
|
||||
dma_set_select_request(dma_write, data->dma_req_base + 1);
|
||||
dma_set_select_request(dma_read, data->dma_req_base);
|
||||
|
||||
size_t tx_frames = write_len / data->buffer_width;
|
||||
size_t rx_frames = read_len / data->buffer_width;
|
||||
|
||||
spi->ctrlr1 = rx_frames - 1;
|
||||
spi->dmacr = 0x3;
|
||||
spi->ssienr = 0x01;
|
||||
spi->ser = data->chip_select_line;
|
||||
SemaphoreHandle_t event_read = xSemaphoreCreateBinary(), event_write = xSemaphoreCreateBinary();
|
||||
|
||||
dma_transmit_async(dma_read, &spi->dr[0], read_buffer, 0, 1, data->buffer_width, rx_frames, 1, event_read);
|
||||
dma_transmit_async(dma_write, write_buffer, &spi->dr[0], 1, 0, data->buffer_width, tx_frames, 4, event_write);
|
||||
|
||||
configASSERT(xSemaphoreTake(event_read, portMAX_DELAY) == pdTRUE && xSemaphoreTake(event_write, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
dma_close(dma_write);
|
||||
dma_close(dma_read);
|
||||
vSemaphoreDelete(event_read);
|
||||
vSemaphoreDelete(event_write);
|
||||
|
||||
spi->ser = 0x00;
|
||||
spi->ssienr = 0x00;
|
||||
spi->dmacr = 0x00;
|
||||
|
||||
return read_len;
|
||||
}
|
||||
|
||||
static int spi_transfer_full_duplex(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(data->frame_format == SPI_FF_STANDARD);
|
||||
set_bit_mask(&spi->ctrlr0, TMOD_MASK, TMOD_VALUE(0));
|
||||
return spi_read_write(write_buffer, write_len, read_buffer, read_len, userdata);
|
||||
}
|
||||
|
||||
static int spi_transfer_sequential(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
configASSERT(data->frame_format == SPI_FF_STANDARD);
|
||||
set_bit_mask(&spi->ctrlr0, TMOD_MASK, TMOD_VALUE(3));
|
||||
return spi_read_write(write_buffer, write_len, read_buffer, read_len, userdata);
|
||||
}
|
||||
|
||||
static void entry_exclusive(spi_dev_data* dev_data)
|
||||
{
|
||||
spi_data* data = (spi_data*)dev_data->spi_data;
|
||||
configASSERT(xSemaphoreTake(data->free_mutex, portMAX_DELAY) == pdTRUE);
|
||||
spi_config_as_master(dev_data->mode, dev_data->frame_format, dev_data->chip_select_line, dev_data->data_bit_length, dev_data->baud_rate, data);
|
||||
if (dev_data->frame_format != SPI_FF_STANDARD)
|
||||
spi_config(dev_data->instruction_length, dev_data->address_length, dev_data->wait_cycles, dev_data->trans_mode, data);
|
||||
}
|
||||
|
||||
static void exit_exclusive(spi_dev_data* dev_data)
|
||||
{
|
||||
spi_data* data = (spi_data*)dev_data->spi_data;
|
||||
xSemaphoreGive(data->free_mutex);
|
||||
}
|
||||
|
||||
static void spi_dev_install(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static int spi_dev_open(void* userdata)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void spi_dev_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static int spi_dev_read(char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = spi_read(buffer, len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_dev_write(const char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = spi_write(buffer, len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void spi_dev_config(size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode trans_mode, void* userdata)
|
||||
{
|
||||
spi_dev_data* dev_data = (spi_dev_data*)userdata;
|
||||
dev_data->instruction_length = instruction_length;
|
||||
dev_data->address_length = address_length;
|
||||
dev_data->wait_cycles = wait_cycles;
|
||||
dev_data->trans_mode = trans_mode;
|
||||
}
|
||||
|
||||
static double spi_dev_set_speed(double speed, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
double clk = (double)sysctl_clock_get_freq(data->clock);
|
||||
uint32_t div = min(65534, max((uint32_t)ceil(clk / speed), 2));
|
||||
if (div & 1)
|
||||
div++;
|
||||
dev_data->baud_rate = div;
|
||||
return clk / div;
|
||||
}
|
||||
|
||||
static int spi_dev_transfer_sequential(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = spi_transfer_sequential(write_buffer, write_len, read_buffer, read_len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int spi_dev_transfer_full_duplex(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
int ret = spi_transfer_full_duplex(write_buffer, write_len, read_buffer, read_len, data);
|
||||
exit_exclusive(dev_data);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void spi_dev_fill(size_t instruction, size_t address, uint32_t value, size_t count, void* userdata)
|
||||
{
|
||||
COMMON_DEV_ENTRY;
|
||||
entry_exclusive(dev_data);
|
||||
spi_fill(instruction, address, value, count, data);
|
||||
exit_exclusive(dev_data);
|
||||
}
|
||||
|
||||
static spi_data dev0_data = {SYSCTL_CLOCK_SPI0, SPI0_BASE_ADDR, 16, 8, 21, SYSCTL_DMA_SELECT_SSI0_RX_REQ, {0}};
|
||||
static spi_data dev1_data = {SYSCTL_CLOCK_SPI1, SPI1_BASE_ADDR, 16, 8, 21, SYSCTL_DMA_SELECT_SSI1_RX_REQ, {0}};
|
||||
static spi_data dev3_data = {SYSCTL_CLOCK_SPI3, SPI3_BASE_ADDR, 0, 10, 22, SYSCTL_DMA_SELECT_SSI3_RX_REQ, {0}};
|
||||
|
||||
const spi_driver_t g_spi_driver_spi0 = {{&dev0_data, spi_install, spi_open, spi_close}, spi_get_device};
|
||||
const spi_driver_t g_spi_driver_spi1 = {{&dev1_data, spi_install, spi_open, spi_close}, spi_get_device};
|
||||
const spi_driver_t g_spi_driver_spi3 = {{&dev3_data, spi_install, spi_open, spi_close}, spi_get_device};
|
|
@ -0,0 +1,166 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <fpioa.h>
|
||||
#include <hal.h>
|
||||
#include <io.h>
|
||||
#include <limits.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <sysctl.h>
|
||||
#include <timer.h>
|
||||
#include "fpioa_cfg.h"
|
||||
|
||||
#define COMMON_ENTRY \
|
||||
timer_data* data = (timer_data*)userdata; \
|
||||
volatile struct timer_t* timer = (volatile struct timer_t*)data->base_addr; \
|
||||
(void)timer;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uintptr_t base_addr;
|
||||
enum sysctl_clock_e clock;
|
||||
enum plic_irq_t irq;
|
||||
size_t channel;
|
||||
timer_ontick ontick;
|
||||
void* ontick_data;
|
||||
} timer_data;
|
||||
|
||||
static void timer_isr(void* userdata);
|
||||
|
||||
static void timer_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
if (data->channel == 0)
|
||||
{
|
||||
sysctl_clock_enable(data->clock);
|
||||
|
||||
readl(&timer->eoi);
|
||||
size_t i;
|
||||
for (i = 0; i < 4; i++)
|
||||
timer->channel[i].control = TIMER_CR_INTERRUPT_MASK;
|
||||
|
||||
pic_set_irq_handler(data->irq, timer_isr, userdata);
|
||||
pic_set_irq_handler(data->irq + 1, timer_isr, userdata);
|
||||
pic_set_irq_priority(data->irq, 1);
|
||||
pic_set_irq_priority(data->irq + 1, 1);
|
||||
pic_set_irq_enable(data->irq, 1);
|
||||
pic_set_irq_enable(data->irq + 1, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static int timer_open(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void timer_close(void* userdata)
|
||||
{
|
||||
}
|
||||
|
||||
static size_t timer_set_interval(size_t nanoseconds, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
uint32_t clk_freq = sysctl_clock_get_freq(data->clock);
|
||||
double min_step = 1e9 / clk_freq;
|
||||
size_t value = (size_t)(nanoseconds / min_step);
|
||||
configASSERT(value > 0 && value < UINT32_MAX);
|
||||
timer->channel[data->channel].load_count = (uint32_t)value;
|
||||
return (size_t)(min_step * value);
|
||||
}
|
||||
|
||||
static void timer_set_ontick(timer_ontick ontick, void* ontick_data, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
data->ontick_data = ontick_data;
|
||||
data->ontick = ontick;
|
||||
}
|
||||
|
||||
static void timer_set_enable(int enable, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
if (enable)
|
||||
timer->channel[data->channel].control = TIMER_CR_USER_MODE | TIMER_CR_ENABLE;
|
||||
else
|
||||
timer->channel[data->channel].control = TIMER_CR_INTERRUPT_MASK;
|
||||
}
|
||||
|
||||
static void timer_isr(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
uint32_t channel = timer->intr_stat;
|
||||
size_t i = 0;
|
||||
for (i = 0; i < 4; i++)
|
||||
{
|
||||
if (channel & 1)
|
||||
{
|
||||
timer_data* td = data + i;
|
||||
if (td->ontick)
|
||||
td->ontick(td->ontick_data);
|
||||
}
|
||||
|
||||
channel >>= 1;
|
||||
}
|
||||
|
||||
readl(&timer->eoi);
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
#define DEFINE_TIMER_DATA(i) \
|
||||
{ TIMER##i##_BASE_ADDR, SYSCTL_CLOCK_TIMER##i, IRQN_TIMER##i##A_INTERRUPT, 0, NULL, NULL }, \
|
||||
{ TIMER##i##_BASE_ADDR, SYSCTL_CLOCK_TIMER##i, IRQN_TIMER##i##A_INTERRUPT, 1, NULL, NULL }, \
|
||||
{ TIMER##i##_BASE_ADDR, SYSCTL_CLOCK_TIMER##i, IRQN_TIMER##i##A_INTERRUPT, 2, NULL, NULL }, \
|
||||
{ TIMER##i##_BASE_ADDR, SYSCTL_CLOCK_TIMER##i, IRQN_TIMER##i##A_INTERRUPT, 3, NULL, NULL }
|
||||
/* clang format on */
|
||||
|
||||
#define INIT_TIMER_DRIVER(i) { { &dev_data[i], timer_install, timer_open, timer_close }, timer_set_interval, timer_set_ontick, timer_set_enable }
|
||||
|
||||
static timer_data dev_data[12] =
|
||||
{
|
||||
DEFINE_TIMER_DATA(0),
|
||||
DEFINE_TIMER_DATA(1),
|
||||
DEFINE_TIMER_DATA(2)
|
||||
};
|
||||
|
||||
const timer_driver_t g_timer_driver_timer0 = INIT_TIMER_DRIVER(0);
|
||||
const timer_driver_t g_timer_driver_timer1 = INIT_TIMER_DRIVER(1);
|
||||
const timer_driver_t g_timer_driver_timer2 = INIT_TIMER_DRIVER(2);
|
||||
const timer_driver_t g_timer_driver_timer3 = INIT_TIMER_DRIVER(3);
|
||||
const timer_driver_t g_timer_driver_timer4 = INIT_TIMER_DRIVER(4);
|
||||
const timer_driver_t g_timer_driver_timer5 = INIT_TIMER_DRIVER(5);
|
||||
const timer_driver_t g_timer_driver_timer6 = INIT_TIMER_DRIVER(6);
|
||||
const timer_driver_t g_timer_driver_timer7 = INIT_TIMER_DRIVER(7);
|
||||
const timer_driver_t g_timer_driver_timer8 = INIT_TIMER_DRIVER(8);
|
||||
const timer_driver_t g_timer_driver_timer9 = INIT_TIMER_DRIVER(9);
|
||||
const timer_driver_t g_timer_driver_timer10 = INIT_TIMER_DRIVER(10);
|
||||
const timer_driver_t g_timer_driver_timer11 = INIT_TIMER_DRIVER(11);
|
|
@ -0,0 +1,200 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <driver.h>
|
||||
#include <hal.h>
|
||||
#include <plic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <sysctl.h>
|
||||
#include <uart.h>
|
||||
|
||||
#define UART_BRATE_CONST 16
|
||||
#define RINGBUFF_LEN 64
|
||||
#define COMMON_ENTRY \
|
||||
uart_data* data = (uart_data*)userdata; \
|
||||
volatile uart_t* uart = (volatile uart_t*)data->base_addr; \
|
||||
(void)uart;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
size_t head;
|
||||
size_t tail;
|
||||
size_t length;
|
||||
char ring_buffer[RINGBUFF_LEN];
|
||||
} ringbuffer_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
enum sysctl_clock_e clock;
|
||||
uintptr_t base_addr;
|
||||
size_t channel;
|
||||
ringbuffer_t* recBuf;
|
||||
} uart_data;
|
||||
|
||||
static int write_ringbuff(uint8_t rdata, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
ringbuffer_t* ring_buff = data->recBuf;
|
||||
|
||||
if (ring_buff->length >= RINGBUFF_LEN)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
ring_buff->ring_buffer[ring_buff->tail] = rdata;
|
||||
ring_buff->tail = (ring_buff->tail + 1) % RINGBUFF_LEN;
|
||||
ring_buff->length++;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int read_ringbuff(char* rData, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
ringbuffer_t* ring_buff = data->recBuf;
|
||||
size_t cnt = 0;
|
||||
while ((len--) && ring_buff->length)
|
||||
{
|
||||
*(rData++) = ring_buff->ring_buffer[ring_buff->head];
|
||||
ring_buff->head = (ring_buff->head + 1) % RINGBUFF_LEN;
|
||||
ring_buff->length--;
|
||||
cnt++;
|
||||
}
|
||||
return cnt;
|
||||
}
|
||||
|
||||
static void on_irq_apbuart_recv(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
while (uart->LSR & 1)
|
||||
{
|
||||
write_ringbuff(((uint8_t)(uart->RBR & 0xff)), userdata);
|
||||
}
|
||||
}
|
||||
|
||||
static void uart_install(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
sysctl_clock_enable(data->clock);
|
||||
}
|
||||
|
||||
static int uart_open(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
ringbuffer_t* ring_buff = malloc(sizeof(ringbuffer_t));
|
||||
ring_buff->head = 0;
|
||||
ring_buff->tail = 0;
|
||||
ring_buff->length = 0;
|
||||
data->recBuf = ring_buff;
|
||||
pic_set_irq_handler(IRQN_UART1_INTERRUPT + data->channel, on_irq_apbuart_recv, userdata);
|
||||
pic_set_irq_priority(IRQN_UART1_INTERRUPT + data->channel, 1);
|
||||
pic_set_irq_enable(IRQN_UART1_INTERRUPT + data->channel, 1);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void uart_close(void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
free(data->recBuf);
|
||||
}
|
||||
|
||||
static void uart_config(size_t baud_rate, size_t data_width, uart_stopbit stopbit, uart_parity parity, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
configASSERT(data_width >= 5 && data_width <= 8);
|
||||
if (data_width == 5)
|
||||
{
|
||||
configASSERT(stopbit != UART_STOP_2);
|
||||
}
|
||||
else
|
||||
{
|
||||
configASSERT(stopbit != UART_STOP_1_5);
|
||||
}
|
||||
|
||||
uint32_t stopbit_val = stopbit == UART_STOP_1 ? 0 : 1;
|
||||
uint32_t parity_val = 0;
|
||||
switch (parity)
|
||||
{
|
||||
case UART_PARITY_NONE:
|
||||
parity_val = 0;
|
||||
break;
|
||||
case UART_PARITY_ODD:
|
||||
parity_val = 1;
|
||||
break;
|
||||
case UART_PARITY_EVEN:
|
||||
parity_val = 3;
|
||||
break;
|
||||
default:
|
||||
configASSERT(!"Invalid parity");
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t freq = sysctl_clock_get_freq(data->clock);
|
||||
uint32_t u16Divider = (freq + UART_BRATE_CONST * baud_rate / 2) / (UART_BRATE_CONST * baud_rate);
|
||||
|
||||
/* Set UART registers */
|
||||
uart->TCR &= ~(1u);
|
||||
uart->TCR &= ~(1u << 3);
|
||||
uart->TCR &= ~(1u << 4);
|
||||
uart->TCR |= (1u << 2);
|
||||
uart->TCR &= ~(1u << 1);
|
||||
uart->DE_EN &= ~(1u);
|
||||
|
||||
uart->LCR |= 1u << 7;
|
||||
uart->DLL = u16Divider & 0xFF;
|
||||
uart->DLH = u16Divider >> 8;
|
||||
uart->LCR = 0;
|
||||
uart->LCR = (data_width - 5) | (stopbit_val << 2) | (parity_val << 3);
|
||||
uart->LCR &= ~(1u << 7);
|
||||
uart->MCR &= ~3;
|
||||
uart->IER = 1;
|
||||
}
|
||||
|
||||
static int uart_putc(volatile uart_t* uart, char c)
|
||||
{
|
||||
while (!(uart->LSR & (1u << 6)))
|
||||
continue;
|
||||
uart->THR = c;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int uart_read(char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
return read_ringbuff(buffer, len, userdata);
|
||||
}
|
||||
|
||||
static int uart_write(const char* buffer, size_t len, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY;
|
||||
|
||||
int write = 0;
|
||||
while (write < len)
|
||||
{
|
||||
uart_putc(uart, *buffer++);
|
||||
write++;
|
||||
}
|
||||
|
||||
return write;
|
||||
}
|
||||
|
||||
static uart_data dev0_data = {SYSCTL_CLOCK_UART1, UART1_BASE_ADDR, 0, NULL};
|
||||
static uart_data dev1_data = {SYSCTL_CLOCK_UART2, UART2_BASE_ADDR, 1, NULL};
|
||||
static uart_data dev2_data = {SYSCTL_CLOCK_UART3, UART3_BASE_ADDR, 2, NULL};
|
||||
|
||||
const uart_driver_t g_uart_driver_uart0 = {{&dev0_data, uart_install, uart_open, uart_close}, uart_config, uart_read, uart_write};
|
||||
const uart_driver_t g_uart_driver_uart1 = {{&dev1_data, uart_install, uart_open, uart_close}, uart_config, uart_read, uart_write};
|
||||
const uart_driver_t g_uart_driver_uart2 = {{&dev2_data, uart_install, uart_open, uart_close}, uart_config, uart_read, uart_write};
|
|
@ -0,0 +1,85 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* Enable kernel-mode log API */
|
||||
#include <stdlib.h>
|
||||
|
||||
#include <FreeRTOSConfig.h>
|
||||
#include <sysctl.h>
|
||||
#include "clint.h"
|
||||
#include "entry.h"
|
||||
#include "fpioa.h"
|
||||
#include "uarths.h"
|
||||
|
||||
#define PLL0_OUTPUT_FREQ configCPU_CLOCK_HZ * 2
|
||||
#define PLL1_OUTPUT_FREQ 160000000UL
|
||||
#define PLL2_OUTPUT_FREQ 45158400UL
|
||||
|
||||
extern int main(int argc, char* argv[]);
|
||||
extern void __libc_init_array(void);
|
||||
extern void __libc_fini_array(void);
|
||||
extern int os_entry(int core_id, int number_of_cores, int (*user_main)(int, char**));
|
||||
|
||||
void setup_clocks()
|
||||
{
|
||||
/* Only set once */
|
||||
if (!sysctl->pll0.pll_out_en0)
|
||||
{
|
||||
sysctl_pll_enable(SYSCTL_PLL0);
|
||||
sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, PLL0_OUTPUT_FREQ);
|
||||
while (sysctl_pll_is_lock(SYSCTL_PLL0) == 0)
|
||||
sysctl_pll_clear_slip(SYSCTL_PLL0);
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_PLL0);
|
||||
sysctl->clk_sel0.aclk_divider_sel = 0;
|
||||
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0);
|
||||
|
||||
sysctl_pll_enable(SYSCTL_PLL1);
|
||||
sysctl_pll_set_freq(SYSCTL_PLL1, SYSCTL_SOURCE_IN0, PLL1_OUTPUT_FREQ);
|
||||
while (sysctl_pll_is_lock(SYSCTL_PLL1) == 0)
|
||||
sysctl_pll_clear_slip(SYSCTL_PLL1);
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_PLL1);
|
||||
|
||||
sysctl_pll_enable(SYSCTL_PLL2);
|
||||
sysctl_pll_set_freq(SYSCTL_PLL2, SYSCTL_SOURCE_IN0, PLL2_OUTPUT_FREQ);
|
||||
while (sysctl_pll_is_lock(SYSCTL_PLL2) == 0)
|
||||
sysctl_pll_clear_slip(SYSCTL_PLL2);
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_PLL2);
|
||||
}
|
||||
}
|
||||
|
||||
void _init_bsp(int core_id, int number_of_cores)
|
||||
{
|
||||
/* Initialize thread local data */
|
||||
init_tls();
|
||||
|
||||
if (core_id == 0)
|
||||
{
|
||||
/* Copy lma data to memory */
|
||||
init_lma();
|
||||
/* Initialize bss data to 0 */
|
||||
init_bss();
|
||||
/* Register finalization function */
|
||||
atexit(__libc_fini_array);
|
||||
/* Init libc array for C++ */
|
||||
__libc_init_array();
|
||||
/* Init FPIOA */
|
||||
fpioa_init();
|
||||
/* Setup clocks */
|
||||
setup_clocks();
|
||||
/* Init UART */
|
||||
uart_init();
|
||||
}
|
||||
|
||||
exit(os_entry(core_id, number_of_cores, main));
|
||||
}
|
|
@ -0,0 +1,236 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _BSP_ATOMIC_H
|
||||
#define _BSP_ATOMIC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int lock;
|
||||
} spinlock_t;
|
||||
|
||||
#define SPINLOCK_INIT \
|
||||
{ \
|
||||
0 \
|
||||
}
|
||||
|
||||
/* Defination of memory barrier macro */
|
||||
#define mb() \
|
||||
{ \
|
||||
asm volatile("fence" :: \
|
||||
: "memory"); \
|
||||
}
|
||||
|
||||
#define atomic_set(ptr, val) (*(volatile typeof(*(ptr))*)(ptr) = val)
|
||||
#define atomic_read(ptr) (*(volatile typeof(*(ptr))*)(ptr))
|
||||
|
||||
#define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
|
||||
#define atomic_or(ptr, inc) __sync_fetch_and_or(ptr, inc)
|
||||
#define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
|
||||
#define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
|
||||
|
||||
static inline int spinlock_trylock(spinlock_t* lock)
|
||||
{
|
||||
int res = atomic_swap(&lock->lock, -1);
|
||||
/*Use memory barrier to keep coherency */
|
||||
mb();
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline void spinlock_lock(spinlock_t* lock)
|
||||
{
|
||||
do
|
||||
{
|
||||
while (atomic_read(&lock->lock))
|
||||
;
|
||||
} while (spinlock_trylock(lock));
|
||||
}
|
||||
|
||||
static inline void spinlock_unlock(spinlock_t* lock)
|
||||
{
|
||||
/*Use memory barrier to keep coherency */
|
||||
mb();
|
||||
atomic_set(&lock->lock, 0);
|
||||
}
|
||||
|
||||
typedef struct
|
||||
{
|
||||
spinlock_t lock;
|
||||
int count;
|
||||
int waiting;
|
||||
} semaphore_t;
|
||||
|
||||
static inline void semaphore_signal(semaphore_t* semaphore, int i)
|
||||
{
|
||||
spinlock_lock(&(semaphore->lock));
|
||||
semaphore->count += i;
|
||||
spinlock_unlock(&(semaphore->lock));
|
||||
}
|
||||
|
||||
static inline void semaphore_wait(semaphore_t* semaphore, int i)
|
||||
{
|
||||
atomic_add(&(semaphore->waiting), 1);
|
||||
while (1)
|
||||
{
|
||||
spinlock_lock(&(semaphore->lock));
|
||||
if (semaphore->count >= i)
|
||||
{
|
||||
semaphore->count -= i;
|
||||
atomic_add(&(semaphore->waiting), -1);
|
||||
spinlock_unlock(&(semaphore->lock));
|
||||
break;
|
||||
}
|
||||
spinlock_unlock(&(semaphore->lock));
|
||||
}
|
||||
}
|
||||
|
||||
static inline int semaphore_count(semaphore_t* semaphore)
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
spinlock_lock(&(semaphore->lock));
|
||||
res = semaphore->count;
|
||||
spinlock_unlock(&(semaphore->lock));
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline int semaphore_waiting(semaphore_t* semaphore)
|
||||
{
|
||||
return atomic_read(&(semaphore->waiting));
|
||||
}
|
||||
|
||||
typedef struct
|
||||
{
|
||||
spinlock_t lock;
|
||||
int count;
|
||||
int hart;
|
||||
} hartlock_t;
|
||||
|
||||
#define HARTLOCK_INIT \
|
||||
{ \
|
||||
.lock = SPINLOCK_INIT, \
|
||||
.count = 0, \
|
||||
.hart = -1 \
|
||||
}
|
||||
|
||||
static inline int hartlock_trylock(hartlock_t* lock)
|
||||
{
|
||||
int res = 0;
|
||||
unsigned long hart;
|
||||
|
||||
asm volatile("csrr %0, mhartid;"
|
||||
: "=r"(hart));
|
||||
spinlock_lock(&lock->lock);
|
||||
|
||||
if (lock->count == 0)
|
||||
{
|
||||
/* First time get lock */
|
||||
lock->count++;
|
||||
lock->hart = hart;
|
||||
res = 0;
|
||||
}
|
||||
else if (lock->hart == hart)
|
||||
{
|
||||
/* Same core get lock */
|
||||
lock->count++;
|
||||
res = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Different core get lock */
|
||||
res = -1;
|
||||
}
|
||||
spinlock_unlock(&lock->lock);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static inline void hartlock_lock(hartlock_t* lock)
|
||||
{
|
||||
unsigned long hart;
|
||||
|
||||
asm volatile("csrr %0, mhartid;"
|
||||
: "=r"(hart));
|
||||
spinlock_lock(&lock->lock);
|
||||
|
||||
if (lock->count == 0)
|
||||
{
|
||||
/* First time get lock */
|
||||
lock->count++;
|
||||
lock->hart = hart;
|
||||
}
|
||||
else if (lock->hart == hart)
|
||||
{
|
||||
/* Same core get lock */
|
||||
lock->count++;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Different core get lock */
|
||||
spinlock_unlock(&lock->lock);
|
||||
|
||||
do
|
||||
{
|
||||
while (atomic_read(&lock->count))
|
||||
;
|
||||
} while (hartlock_trylock(lock));
|
||||
}
|
||||
spinlock_unlock(&lock->lock);
|
||||
}
|
||||
|
||||
static inline void hartlock_unlock(hartlock_t* lock)
|
||||
{
|
||||
unsigned long hart;
|
||||
|
||||
asm volatile("csrr %0, mhartid;"
|
||||
: "=r"(hart));
|
||||
spinlock_lock(&lock->lock);
|
||||
|
||||
if (lock->hart == hart)
|
||||
{
|
||||
/* Same core release lock */
|
||||
lock->count--;
|
||||
if (lock->count <= 0)
|
||||
{
|
||||
lock->hart = -1;
|
||||
lock->count = 0;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Different core release lock */
|
||||
spinlock_unlock(&lock->lock);
|
||||
|
||||
register unsigned long a7 asm("a7") = 93;
|
||||
register unsigned long a0 asm("a0") = 0;
|
||||
register unsigned long a1 asm("a1") = 0;
|
||||
register unsigned long a2 asm("a2") = 0;
|
||||
|
||||
asm volatile("scall"
|
||||
: "+r"(a0)
|
||||
: "r"(a1), "r"(a2), "r"(a7));
|
||||
}
|
||||
spinlock_unlock(&lock->lock);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BSP_ATOMIC_H */
|
|
@ -0,0 +1,139 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _BSP_DUMP_H
|
||||
#define _BSP_DUMP_H
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "syslog.h"
|
||||
#include "uarths.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define DUMP_PRINTF printk
|
||||
|
||||
static inline void
|
||||
dump_core(const char* reason, uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
static const char* const reg_usage[][2] = {
|
||||
{"zero ", "Hard-wired zero"},
|
||||
{"ra ", "Return address"},
|
||||
{"sp ", "Stack pointer"},
|
||||
{"gp ", "Global pointer"},
|
||||
{"tp ", "Thread pointer"},
|
||||
{"t0 ", "Temporaries Caller"},
|
||||
{"t1 ", "Temporaries Caller"},
|
||||
{"t2 ", "Temporaries Caller"},
|
||||
{"s0/fp", "Saved register/frame pointer"},
|
||||
{"s1 ", "Saved register"},
|
||||
{"a0 ", "Function arguments/return values"},
|
||||
{"a1 ", "Function arguments/return values"},
|
||||
{"a2 ", "Function arguments values"},
|
||||
{"a3 ", "Function arguments values"},
|
||||
{"a4 ", "Function arguments values"},
|
||||
{"a5 ", "Function arguments values"},
|
||||
{"a6 ", "Function arguments values"},
|
||||
{"a7 ", "Function arguments values"},
|
||||
{"s2 ", "Saved registers"},
|
||||
{"s3 ", "Saved registers"},
|
||||
{"s4 ", "Saved registers"},
|
||||
{"s5 ", "Saved registers"},
|
||||
{"s6 ", "Saved registers"},
|
||||
{"s7 ", "Saved registers"},
|
||||
{"s8 ", "Saved registers"},
|
||||
{"s9 ", "Saved registers"},
|
||||
{"s10 ", "Saved registers"},
|
||||
{"s11 ", "Saved registers"},
|
||||
{"t3 ", "Temporaries Caller"},
|
||||
{"t4 ", "Temporaries Caller"},
|
||||
{"t5 ", "Temporaries Caller"},
|
||||
{"t6 ", "Temporaries Caller"},
|
||||
};
|
||||
|
||||
static const char* const regf_usage[][2] = {
|
||||
{"ft0 ", "FP temporaries"},
|
||||
{"ft1 ", "FP temporaries"},
|
||||
{"ft2 ", "FP temporaries"},
|
||||
{"ft3 ", "FP temporaries"},
|
||||
{"ft4 ", "FP temporaries"},
|
||||
{"ft5 ", "FP temporaries"},
|
||||
{"ft6 ", "FP temporaries"},
|
||||
{"ft7 ", "FP temporaries"},
|
||||
{"fs0 ", "FP saved registers"},
|
||||
{"fs1 ", "FP saved registers"},
|
||||
{"fa0 ", "FP arguments/return values"},
|
||||
{"fa1 ", "FP arguments/return values"},
|
||||
{"fa2 ", "FP arguments values"},
|
||||
{"fa3 ", "FP arguments values"},
|
||||
{"fa4 ", "FP arguments values"},
|
||||
{"fa5 ", "FP arguments values"},
|
||||
{"fa6 ", "FP arguments values"},
|
||||
{"fa7 ", "FP arguments values"},
|
||||
{"fs2 ", "FP Saved registers"},
|
||||
{"fs3 ", "FP Saved registers"},
|
||||
{"fs4 ", "FP Saved registers"},
|
||||
{"fs5 ", "FP Saved registers"},
|
||||
{"fs6 ", "FP Saved registers"},
|
||||
{"fs7 ", "FP Saved registers"},
|
||||
{"fs8 ", "FP Saved registers"},
|
||||
{"fs9 ", "FP Saved registers"},
|
||||
{"fs10", "FP Saved registers"},
|
||||
{"fs11", "FP Saved registers"},
|
||||
{"ft8 ", "FP Temporaries Caller"},
|
||||
{"ft9 ", "FP Temporaries Caller"},
|
||||
{"ft10", "FP Temporaries Caller"},
|
||||
{"ft11", "FP Temporaries Caller"},
|
||||
};
|
||||
|
||||
if (CONFIG_LOG_LEVEL >= LOG_ERROR)
|
||||
{
|
||||
const char unknown_reason[] = "unknown";
|
||||
|
||||
if (!reason)
|
||||
reason = unknown_reason;
|
||||
|
||||
DUMP_PRINTF("core %d, core dump: %s\n", (int)read_csr(mhartid), reason);
|
||||
DUMP_PRINTF("Cause 0x%016lx, EPC 0x%016lx\n", cause, epc);
|
||||
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < 32 / 2; i++)
|
||||
{
|
||||
DUMP_PRINTF(
|
||||
"reg[%02d](%s) = 0x%016lx, reg[%02d](%s) = 0x%016lx\n",
|
||||
i * 2, reg_usage[i * 2][0], regs[i * 2],
|
||||
i * 2 + 1, reg_usage[i * 2 + 1][0], regs[i * 2 + 1]);
|
||||
}
|
||||
|
||||
for (i = 0; i < 32 / 2; i++)
|
||||
{
|
||||
DUMP_PRINTF(
|
||||
"freg[%02d](%s) = 0x%016lx(%f), freg[%02d](%s) = 0x%016lx(%f)\n",
|
||||
i * 2, regf_usage[i * 2][0], fregs[i * 2], (float)fregs[i * 2],
|
||||
i * 2 + 1, regf_usage[i * 2 + 1][0], fregs[i * 2 + 1], (float)fregs[i * 2 + 1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#undef DUMP_PRINTF
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BSP_DUMP_H */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,70 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _BSP_ENTRY_H
|
||||
#define _BSP_ENTRY_H
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
static inline void init_lma(void)
|
||||
{
|
||||
extern unsigned int _data_lma;
|
||||
extern unsigned int _data;
|
||||
extern unsigned int _edata;
|
||||
unsigned int *src, *dst;
|
||||
|
||||
src = &_data_lma;
|
||||
dst = &_data;
|
||||
while (dst < &_edata)
|
||||
*dst++ = *src++;
|
||||
}
|
||||
|
||||
static inline void init_bss(void)
|
||||
{
|
||||
extern unsigned int _bss;
|
||||
extern unsigned int _ebss;
|
||||
unsigned int* dst;
|
||||
|
||||
dst = &_bss;
|
||||
while (dst < &_ebss)
|
||||
*dst++ = 0;
|
||||
}
|
||||
|
||||
static inline void init_tls(void)
|
||||
{
|
||||
register void* thread_pointer asm("tp");
|
||||
extern char _tls_data;
|
||||
|
||||
extern __thread char _tdata_begin, _tdata_end, _tbss_end;
|
||||
|
||||
size_t tdata_size = &_tdata_end - &_tdata_begin;
|
||||
|
||||
memcpy(thread_pointer, &_tls_data, tdata_size);
|
||||
|
||||
size_t tbss_size = &_tbss_end - &_tdata_end;
|
||||
|
||||
memset(thread_pointer + tdata_size, 0, tbss_size);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BSP_ENTRY_H */
|
|
@ -0,0 +1,44 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _BSP_INTERRUPT_H
|
||||
#define _BSP_INTERRUPT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
/* clang-format off */
|
||||
/* Machine interrupt mask for 64 bit system, 0x8000 0000 0000 0000 */
|
||||
#define CAUSE_MACHINE_IRQ_MASK (0x1ULL << 63)
|
||||
|
||||
/* Machine interrupt reason mask for 64 bit system, 0x7FFF FFFF FFFF FFFF */
|
||||
#define CAUSE_MACHINE_IRQ_REASON_MASK (CAUSE_MACHINE_IRQ_MASK - 1)
|
||||
|
||||
/* Hypervisor interrupt mask for 64 bit system, 0x8000 0000 0000 0000 */
|
||||
#define CAUSE_HYPERVISOR_IRQ_MASK (0x1ULL << 63)
|
||||
|
||||
/* Hypervisor interrupt reason mask for 64 bit system, 0x7FFF FFFF FFFF FFFF */
|
||||
#define CAUSE_HYPERVISOR_IRQ_REASON_MASK (CAUSE_HYPERVISOR_IRQ_MASK - 1)
|
||||
|
||||
/* Supervisor interrupt mask for 64 bit system, 0x8000 0000 0000 0000 */
|
||||
#define CAUSE_SUPERVISOR_IRQ_MASK (0x1ULL << 63)
|
||||
|
||||
/* Supervisor interrupt reason mask for 64 bit system, 0x7FFF FFFF FFFF FFFF */
|
||||
#define CAUSE_SUPERVISOR_IRQ_REASON_MASK (CAUSE_SUPERVISOR_IRQ_MASK - 1)
|
||||
/* clang-format on */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BSP_INTERRUPT_H */
|
|
@ -0,0 +1,89 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _BSP_PLATFORM_H
|
||||
#define _BSP_PLATFORM_H
|
||||
|
||||
/* clang-format off */
|
||||
/* Register base address */
|
||||
|
||||
/* Under Coreplex */
|
||||
#define CLINT_BASE_ADDR (0x02000000)
|
||||
#define PLIC_BASE_ADDR (0x0C000000)
|
||||
|
||||
/* Under TileLink */
|
||||
#define UARTHS_BASE_ADDR (0x38000000)
|
||||
#define GPIOHS_BASE_ADDR (0x38001000)
|
||||
|
||||
/* Under AXI 64 bit */
|
||||
#define RAM_BASE_ADDR (0x80000000)
|
||||
#define RAM_SIZE (6 * 1024 * 1024)
|
||||
|
||||
#define IO_BASE_ADDR (0x40000000)
|
||||
#define IO_SIZE (6 * 1024 * 1024)
|
||||
|
||||
#define AI_RAM_BASE_ADDR (0x80600000)
|
||||
#define AI_RAM_SIZE (2 * 1024 * 1024)
|
||||
|
||||
#define AI_IO_BASE_ADDR (0x40600000)
|
||||
#define AI_IO_SIZE (2 * 1024 * 1024)
|
||||
|
||||
#define AI_BASE_ADDR (0x40800000)
|
||||
#define AI_SIZE (12 * 1024 * 1024)
|
||||
|
||||
#define FFT_BASE_ADDR (0x42000000)
|
||||
#define FFT_SIZE (4 * 1024 * 1024)
|
||||
|
||||
#define ROM_BASE_ADDR (0x88000000)
|
||||
#define ROM_SIZE (128 * 1024)
|
||||
|
||||
/* Under AHB 32 bit */
|
||||
#define DMAC_BASE_ADDR (0x50000000)
|
||||
|
||||
/* Under APB1 32 bit */
|
||||
#define GPIO_BASE_ADDR (0x50200000)
|
||||
#define UART1_BASE_ADDR (0x50210000)
|
||||
#define UART2_BASE_ADDR (0x50220000)
|
||||
#define UART3_BASE_ADDR (0x50230000)
|
||||
#define SPI_SLAVE_BASE_ADDR (0x50240000)
|
||||
#define I2S0_BASE_ADDR (0x50250000)
|
||||
#define I2S1_BASE_ADDR (0x50260000)
|
||||
#define I2S2_BASE_ADDR (0x50270000)
|
||||
#define I2C0_BASE_ADDR (0x50280000)
|
||||
#define I2C1_BASE_ADDR (0x50290000)
|
||||
#define I2C2_BASE_ADDR (0x502A0000)
|
||||
#define FPIOA_BASE_ADDR (0x502B0000)
|
||||
#define SHA256_BASE_ADDR (0x502C0000)
|
||||
#define TIMER0_BASE_ADDR (0x502D0000)
|
||||
#define TIMER1_BASE_ADDR (0x502E0000)
|
||||
#define TIMER2_BASE_ADDR (0x502F0000)
|
||||
|
||||
/* Under APB2 32 bit */
|
||||
#define WDT0_BASE_ADDR (0x50400000)
|
||||
#define WDT1_BASE_ADDR (0x50410000)
|
||||
#define OTP_BASE_ADDR (0x50420000)
|
||||
#define DVP_BASE_ADDR (0x50430000)
|
||||
#define SYSCTL_BASE_ADDR (0x50440000)
|
||||
#define AES_BASE_ADDR (0x50450000)
|
||||
#define RTC_BASE_ADDR (0x50460000)
|
||||
|
||||
|
||||
/* Under APB3 32 bit */
|
||||
#define SPI0_BASE_ADDR (0x52000000)
|
||||
#define SPI1_BASE_ADDR (0x53000000)
|
||||
#define SPI3_BASE_ADDR (0x54000000)
|
||||
|
||||
/* clang-format on */
|
||||
|
||||
#endif /* _BSP_PLATFORM_H */
|
|
@ -0,0 +1,222 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* File: printf.h
|
||||
*
|
||||
* Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Kustaa Nyholm or SpareTimeLabs nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library; if not, write to the Free Software Foundation,
|
||||
* Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* This library is really just two files: 'tinyprintf.h' and 'tinyprintf.c'.
|
||||
*
|
||||
* They provide a simple and small (+400 loc) printf functionality to be used
|
||||
* in embedded systems.
|
||||
*
|
||||
* I've found them so useful in debugging that I do not bother with a debugger
|
||||
* at all.
|
||||
*
|
||||
* They are distributed in source form, so to use them, just compile them into
|
||||
* your project.
|
||||
*
|
||||
* Two printf variants are provided: printf and the 'sprintf' family of
|
||||
* functions ('snprintf', 'sprintf', 'vsnprintf', 'vsprintf').
|
||||
*
|
||||
* The formats supported by this implementation are: 'c' 'd' 'i' 'o' 'p' 'u'
|
||||
* 's' 'x' 'X'.
|
||||
*
|
||||
* Zero padding, field width, and precision are also supported.
|
||||
*
|
||||
* If the library is compiled with 'PRINTF_SUPPORT_LONG' defined, then the
|
||||
* long specifier is also supported. Note that this will pull in some long
|
||||
* math routines (pun intended!) and thus make your executable noticeably
|
||||
* longer. Likewise with 'PRINTF_LONG_LONG_SUPPORT' for the long long
|
||||
* specifier, and with 'PRINTF_SIZE_T_SUPPORT' for the size_t specifier.
|
||||
*
|
||||
* The memory footprint of course depends on the target CPU, compiler and
|
||||
* compiler options, but a rough guesstimate (based on a H8S target) is about
|
||||
* 1.4 kB for code and some twenty 'int's and 'char's, say 60 bytes of stack
|
||||
* space. Not too bad. Your mileage may vary. By hacking the source code you
|
||||
* can get rid of some hundred bytes, I'm sure, but personally I feel the
|
||||
* balance of functionality and flexibility versus code size is close to
|
||||
* optimal for many embedded systems.
|
||||
*
|
||||
* To use the printf, you need to supply your own character output function,
|
||||
* something like :
|
||||
*
|
||||
* void putc ( void* p, char c) { while (!SERIAL_PORT_EMPTY) ;
|
||||
* SERIAL_PORT_TX_REGISTER = c; }
|
||||
*
|
||||
* Before you can call printf, you need to initialize it to use your character
|
||||
* output function with something like:
|
||||
*
|
||||
* init_printf(NULL,putc);
|
||||
*
|
||||
* Notice the 'NULL' in 'init_printf' and the parameter 'void* p' in 'putc',
|
||||
* the NULL (or any pointer) you pass into the 'init_printf' will eventually
|
||||
* be passed to your 'putc' routine. This allows you to pass some storage
|
||||
* space (or anything really) to the character output function, if necessary.
|
||||
* This is not often needed but it was implemented like that because it made
|
||||
* implementing the sprintf function so neat (look at the source code).
|
||||
*
|
||||
* The code is re-entrant, except for the 'init_printf' function, so it is
|
||||
* safe to call it from interrupts too, although this may result in mixed
|
||||
* output. If you rely on re-entrancy, take care that your 'putc' function is
|
||||
* re-entrant!
|
||||
*
|
||||
* The printf and sprintf functions are actually macros that translate to
|
||||
* 'tfp_printf' and 'tfp_sprintf' when 'TINYPRINTF_OVERRIDE_LIBC' is set
|
||||
* (default). Setting it to 0 makes it possible to use them along with
|
||||
* 'stdio.h' printf's in a single source file. When 'TINYPRINTF_OVERRIDE_LIBC'
|
||||
* is set, please note that printf/sprintf are not function-like macros, so if
|
||||
* you have variables or struct members with these names, things will explode
|
||||
* in your face. Without variadic macros this is the best we can do to wrap
|
||||
* these function. If it is a problem, just give up the macros and use the
|
||||
* functions directly, or rename them.
|
||||
*
|
||||
* It is also possible to avoid defining tfp_printf and/or tfp_sprintf by
|
||||
* clearing 'TINYPRINTF_DEFINE_TFP_PRINTF' and/or
|
||||
* 'TINYPRINTF_DEFINE_TFP_SPRINTF' to 0. This allows for example to export
|
||||
* only tfp_format, which is at the core of all the other functions.
|
||||
*
|
||||
* For further details see source code.
|
||||
*
|
||||
* regs Kusti, 23.10.2004
|
||||
*/
|
||||
|
||||
#ifndef _BSP_PRINTF_H
|
||||
#define _BSP_PRINTF_H
|
||||
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
|
||||
/* Global configuration */
|
||||
|
||||
/* Set this to 0 if you do not want to provide tfp_printf */
|
||||
#ifndef TINYPRINTF_DEFINE_TFP_PRINTF
|
||||
#define TINYPRINTF_DEFINE_TFP_PRINTF 1
|
||||
#endif
|
||||
|
||||
/* Set this to 0 if you do not want to provide
|
||||
* tfp_sprintf/snprintf/vsprintf/vsnprintf
|
||||
*/
|
||||
#ifndef TINYPRINTF_DEFINE_TFP_SPRINTF
|
||||
#define TINYPRINTF_DEFINE_TFP_SPRINTF 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Set this to 0 if you do not want tfp_printf and
|
||||
* tfp_{vsn,sn,vs,s}printf to be also available as
|
||||
* printf/{vsn,sn,vs,s}printf
|
||||
*/
|
||||
#ifndef TINYPRINTF_OVERRIDE_LIBC
|
||||
#define TINYPRINTF_OVERRIDE_LIBC 0
|
||||
#endif
|
||||
|
||||
/* Optional external types dependencies */
|
||||
|
||||
/* Declarations */
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define _TFP_SPECIFY_PRINTF_FMT(fmt_idx, arg1_idx) \
|
||||
__attribute__((format(printf, fmt_idx, arg1_idx)))
|
||||
#else
|
||||
#define _TFP_SPECIFY_PRINTF_FMT(fmt_idx, arg1_idx)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
typedef void (*putcf)(void*, char);
|
||||
|
||||
/*
|
||||
* 'tfp_format' really is the central function for all tinyprintf. For
|
||||
* each output character after formatting, the 'putf' callback is
|
||||
* called with 2 args:
|
||||
* - an arbitrary void* 'putp' param defined by the user and
|
||||
* passed unmodified from 'tfp_format',
|
||||
* - the character.
|
||||
* The 'tfp_printf' and 'tfp_sprintf' functions simply define their own
|
||||
* callback and pass to it the right 'putp' it is expecting.
|
||||
*/
|
||||
void tfp_format(void* putp, putcf putf, const char* fmt, va_list va);
|
||||
|
||||
#if TINYPRINTF_DEFINE_TFP_SPRINTF
|
||||
int tfp_vsnprintf(char* str, size_t size, const char* fmt, va_list ap);
|
||||
int tfp_snprintf(char* str, size_t size, const char* fmt, ...)
|
||||
_TFP_SPECIFY_PRINTF_FMT(3, 4);
|
||||
int tfp_vsprintf(char* str, const char* fmt, va_list ap);
|
||||
int tfp_sprintf(char* str, const char* fmt, ...) _TFP_SPECIFY_PRINTF_FMT(2, 3);
|
||||
#if TINYPRINTF_OVERRIDE_LIBC
|
||||
#define vsnprintf tfp_vsnprintf
|
||||
#define snprintf tfp_snprintf
|
||||
#define vsprintf tfp_vsprintf
|
||||
#define sprintf tfp_sprintf
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if TINYPRINTF_DEFINE_TFP_PRINTF
|
||||
void init_printf(void* putp, putcf putf);
|
||||
void tfp_printf(char* fmt, ...) _TFP_SPECIFY_PRINTF_FMT(1, 2);
|
||||
#if TINYPRINTF_OVERRIDE_LIBC
|
||||
#define printf tfp_printf
|
||||
|
||||
#ifdef __cplusplus
|
||||
#include <forward_list>
|
||||
namespace std
|
||||
{
|
||||
template <typename... Args>
|
||||
auto tfp_printf(Args&&... args) -> decltype(::tfp_printf(std::forward<Args>(args)...))
|
||||
{
|
||||
return ::tfp_printf(std::forward<Args>(args)...);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
int printk(const char* format, ...) _TFP_SPECIFY_PRINTF_FMT(1, 2);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _BSP_PRINTF_H */
|
|
@ -0,0 +1,26 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _BSP_SLEEP_H
|
||||
#define _BSP_SLEEP_H
|
||||
|
||||
#include "clint.h"
|
||||
#include "encoding.h"
|
||||
#include <sys/time.h>
|
||||
|
||||
extern int nanosleep(const struct timespec* req, struct timespec* rem);
|
||||
extern int usleep(useconds_t usec);
|
||||
extern unsigned int sleep(unsigned int seconds);
|
||||
|
||||
#endif /* _BSP_SLEEP_H */
|
|
@ -0,0 +1,64 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* Enable kernel-mode log API */
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include "interrupt.h"
|
||||
#include "dump.h"
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_irq_dummy(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("unhandled interrupt", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_irq_dummy")))
|
||||
handle_irq_m_soft(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_irq_dummy")))
|
||||
handle_irq_m_timer(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_irq_dummy")))
|
||||
handle_irq_m_ext(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_irq(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#pragma GCC diagnostic ignored "-Woverride-init"
|
||||
#endif
|
||||
/* clang-format off */
|
||||
static uintptr_t (* const irq_table[])(
|
||||
uintptr_t cause,
|
||||
uintptr_t epc,
|
||||
uintptr_t regs[32],
|
||||
uintptr_t fregs[32]) = {
|
||||
[0 ... 14] = handle_irq_dummy,
|
||||
[IRQ_M_SOFT] = handle_irq_m_soft,
|
||||
[IRQ_M_TIMER] = handle_irq_m_timer,
|
||||
[IRQ_M_EXT] = handle_irq_m_ext,
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#pragma GCC diagnostic warning "-Woverride-init"
|
||||
#endif
|
||||
|
||||
epc = irq_table[cause & CAUSE_MACHINE_IRQ_REASON_MASK](cause, epc, regs, fregs);
|
||||
return epc;
|
||||
}
|
|
@ -0,0 +1,660 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* File: printf.c
|
||||
*
|
||||
* Copyright (c) 2004,2012 Kustaa Nyholm / SpareTimeLabs
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Kustaa Nyholm or SpareTimeLabs nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
#include "printf.h"
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
|
||||
/* Enable long int support */
|
||||
#define PRINTF_LONG_SUPPORT
|
||||
|
||||
/* Enable long long int support (implies long int support) */
|
||||
#define PRINTF_LONG_LONG_SUPPORT
|
||||
|
||||
/* Enable %z (size_t) support */
|
||||
#define PRINTF_SIZE_T_SUPPORT
|
||||
|
||||
/*
|
||||
* Configuration adjustments
|
||||
*/
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
#define PRINTF_LONG_SUPPORT
|
||||
#endif
|
||||
|
||||
/* __SIZEOF_<type>__ defined at least by gcc */
|
||||
#ifdef __SIZEOF_POINTER__
|
||||
#define SIZEOF_POINTER __SIZEOF_POINTER__
|
||||
#endif
|
||||
#ifdef __SIZEOF_LONG_LONG__
|
||||
#define SIZEOF_LONG_LONG __SIZEOF_LONG_LONG__
|
||||
#endif
|
||||
#ifdef __SIZEOF_LONG__
|
||||
#define SIZEOF_LONG __SIZEOF_LONG__
|
||||
#endif
|
||||
#ifdef __SIZEOF_INT__
|
||||
#define SIZEOF_INT __SIZEOF_INT__
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
#define _TFP_GCC_NO_INLINE_ __attribute__((noinline))
|
||||
#else
|
||||
#define _TFP_GCC_NO_INLINE_
|
||||
#endif
|
||||
|
||||
#define IS_DIGIT(x) ((x) >= '0' && (x) <= '9')
|
||||
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
#define BF_MAX 20 /* long = 64b on some architectures */
|
||||
#else
|
||||
#define BF_MAX 10 /* int = 32b on some architectures */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Implementation
|
||||
*/
|
||||
struct param
|
||||
{
|
||||
char lz : 1; /**< Leading zeros */
|
||||
char alt : 1; /**< alternate form */
|
||||
char uc : 1; /**< Upper case (for base16 only) */
|
||||
char align_left : 1; /**< 0 == align right (default), 1 == align left
|
||||
*/
|
||||
int width; /**< field width */
|
||||
int prec; /**< precision */
|
||||
char sign; /**< The sign to display (if any) */
|
||||
unsigned int base; /**< number base (e.g.: 8, 10, 16) */
|
||||
char* bf; /**< Buffer to output */
|
||||
size_t bf_len; /**< Buffer length */
|
||||
};
|
||||
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
static void _TFP_GCC_NO_INLINE_ ulli2a(unsigned long long int num, struct param* p)
|
||||
{
|
||||
unsigned long long int d = 1;
|
||||
char* bf = p->bf;
|
||||
if ((p->prec == 0) && (num == 0))
|
||||
return;
|
||||
while (num / d >= p->base)
|
||||
{
|
||||
d *= p->base;
|
||||
}
|
||||
while (d != 0)
|
||||
{
|
||||
int dgt = num / d;
|
||||
num %= d;
|
||||
d /= p->base;
|
||||
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
||||
}
|
||||
p->bf_len = bf - p->bf;
|
||||
}
|
||||
|
||||
static void lli2a(long long int num, struct param* p)
|
||||
{
|
||||
if (num < 0)
|
||||
{
|
||||
num = -num;
|
||||
p->sign = '-';
|
||||
}
|
||||
ulli2a(num, p);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
static void uli2a(unsigned long int num, struct param* p)
|
||||
{
|
||||
unsigned long int d = 1;
|
||||
char* bf = p->bf;
|
||||
if ((p->prec == 0) && (num == 0))
|
||||
return;
|
||||
while (num / d >= p->base)
|
||||
{
|
||||
d *= p->base;
|
||||
}
|
||||
while (d != 0)
|
||||
{
|
||||
int dgt = num / d;
|
||||
num %= d;
|
||||
d /= p->base;
|
||||
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
||||
}
|
||||
p->bf_len = bf - p->bf;
|
||||
}
|
||||
|
||||
static void li2a(long num, struct param* p)
|
||||
{
|
||||
if (num < 0)
|
||||
{
|
||||
num = -num;
|
||||
p->sign = '-';
|
||||
}
|
||||
uli2a(num, p);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void ui2a(unsigned int num, struct param* p)
|
||||
{
|
||||
unsigned int d = 1;
|
||||
char* bf = p->bf;
|
||||
if ((p->prec == 0) && (num == 0))
|
||||
return;
|
||||
while (num / d >= p->base)
|
||||
{
|
||||
d *= p->base;
|
||||
}
|
||||
while (d != 0)
|
||||
{
|
||||
int dgt = num / d;
|
||||
num %= d;
|
||||
d /= p->base;
|
||||
*bf++ = dgt + (dgt < 10 ? '0' : (p->uc ? 'A' : 'a') - 10);
|
||||
}
|
||||
p->bf_len = bf - p->bf;
|
||||
}
|
||||
|
||||
static void i2a(int num, struct param* p)
|
||||
{
|
||||
if (num < 0)
|
||||
{
|
||||
num = -num;
|
||||
p->sign = '-';
|
||||
}
|
||||
ui2a(num, p);
|
||||
}
|
||||
|
||||
static int a2d(char ch)
|
||||
{
|
||||
if (IS_DIGIT(ch))
|
||||
return ch - '0';
|
||||
else if (ch >= 'a' && ch <= 'f')
|
||||
return ch - 'a' + 10;
|
||||
else if (ch >= 'A' && ch <= 'F')
|
||||
return ch - 'A' + 10;
|
||||
else
|
||||
return -1;
|
||||
}
|
||||
|
||||
static char a2u(char ch, const char** src, int base, unsigned int* nump)
|
||||
{
|
||||
const char* p = *src;
|
||||
unsigned int num = 0;
|
||||
int digit;
|
||||
while ((digit = a2d(ch)) >= 0)
|
||||
{
|
||||
if (digit > base)
|
||||
break;
|
||||
num = num * base + digit;
|
||||
ch = *p++;
|
||||
}
|
||||
*src = p;
|
||||
*nump = num;
|
||||
return ch;
|
||||
}
|
||||
|
||||
static void putchw(void* putp, putcf putf, struct param* p)
|
||||
{
|
||||
char ch;
|
||||
int width = p->width;
|
||||
int prec = p->prec;
|
||||
char* bf = p->bf;
|
||||
size_t bf_len = p->bf_len;
|
||||
|
||||
/* Number of filling characters */
|
||||
width -= bf_len;
|
||||
prec -= bf_len;
|
||||
if (p->sign)
|
||||
width--;
|
||||
if (p->alt && p->base == 16)
|
||||
width -= 2;
|
||||
else if (p->alt && p->base == 8)
|
||||
width--;
|
||||
if (prec > 0)
|
||||
width -= prec;
|
||||
|
||||
/* Fill with space to align to the right, before alternate or sign */
|
||||
if (!p->lz && !p->align_left)
|
||||
{
|
||||
while (width-- > 0)
|
||||
putf(putp, ' ');
|
||||
}
|
||||
|
||||
/* print sign */
|
||||
if (p->sign)
|
||||
putf(putp, p->sign);
|
||||
|
||||
/* Alternate */
|
||||
if (p->alt && p->base == 16)
|
||||
{
|
||||
putf(putp, '0');
|
||||
putf(putp, (p->uc ? 'X' : 'x'));
|
||||
}
|
||||
else if (p->alt && p->base == 8)
|
||||
{
|
||||
putf(putp, '0');
|
||||
}
|
||||
|
||||
/* Fill with zeros, after alternate or sign */
|
||||
while (prec-- > 0)
|
||||
putf(putp, '0');
|
||||
if (p->lz)
|
||||
{
|
||||
while (width-- > 0)
|
||||
putf(putp, '0');
|
||||
}
|
||||
|
||||
/* Put actual buffer */
|
||||
while ((bf_len-- > 0) && (ch = *bf++))
|
||||
putf(putp, ch);
|
||||
|
||||
/* Fill with space to align to the left, after string */
|
||||
if (!p->lz && p->align_left)
|
||||
{
|
||||
while (width-- > 0)
|
||||
putf(putp, ' ');
|
||||
}
|
||||
}
|
||||
|
||||
void tfp_format(void* putp, putcf putf, const char* fmt, va_list va)
|
||||
{
|
||||
struct param p;
|
||||
char bf[BF_MAX];
|
||||
char ch;
|
||||
|
||||
while ((ch = *(fmt++)))
|
||||
{
|
||||
if (ch != '%')
|
||||
{
|
||||
putf(putp, ch);
|
||||
}
|
||||
else
|
||||
{
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
char lng = 0; /* 1 for long, 2 for long long */
|
||||
#endif
|
||||
/* Init parameter struct */
|
||||
p.lz = 0;
|
||||
p.alt = 0;
|
||||
p.uc = 0;
|
||||
p.align_left = 0;
|
||||
p.width = 0;
|
||||
p.prec = -1;
|
||||
p.sign = 0;
|
||||
p.bf = bf;
|
||||
p.bf_len = 0;
|
||||
|
||||
/* Flags */
|
||||
while ((ch = *(fmt++)))
|
||||
{
|
||||
switch (ch)
|
||||
{
|
||||
case '-':
|
||||
p.align_left = 1;
|
||||
continue;
|
||||
case '0':
|
||||
p.lz = 1;
|
||||
continue;
|
||||
case '#':
|
||||
p.alt = 1;
|
||||
continue;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (p.align_left)
|
||||
p.lz = 0;
|
||||
|
||||
/* Width */
|
||||
if (ch == '*')
|
||||
{
|
||||
ch = *(fmt++);
|
||||
p.width = va_arg(va, int);
|
||||
if (p.width < 0)
|
||||
{
|
||||
p.align_left = 1;
|
||||
p.width = -p.width;
|
||||
}
|
||||
}
|
||||
else if (IS_DIGIT(ch))
|
||||
{
|
||||
unsigned int width;
|
||||
ch = a2u(ch, &fmt, 10, &(width));
|
||||
p.width = width;
|
||||
}
|
||||
|
||||
/* Precision */
|
||||
if (ch == '.')
|
||||
{
|
||||
ch = *(fmt++);
|
||||
if (ch == '*')
|
||||
{
|
||||
int prec;
|
||||
ch = *(fmt++);
|
||||
prec = va_arg(va, int);
|
||||
if (prec < 0)
|
||||
/* act as if precision was
|
||||
* omitted */
|
||||
p.prec = -1;
|
||||
else
|
||||
p.prec = prec;
|
||||
}
|
||||
else if (IS_DIGIT(ch))
|
||||
{
|
||||
unsigned int prec;
|
||||
ch = a2u(ch, &fmt, 10, &(prec));
|
||||
p.prec = prec;
|
||||
}
|
||||
else
|
||||
{
|
||||
p.prec = 0;
|
||||
}
|
||||
}
|
||||
if (p.prec >= 0)
|
||||
/* precision causes zero pad to be ignored */
|
||||
p.lz = 0;
|
||||
|
||||
#ifdef PRINTF_SIZE_T_SUPPORT
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
if (ch == 'z')
|
||||
{
|
||||
ch = *(fmt++);
|
||||
if (sizeof(size_t) == sizeof(unsigned long int))
|
||||
lng = 1;
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
else if (sizeof(size_t) == sizeof(unsigned long long int))
|
||||
lng = 2;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
if (ch == 'l')
|
||||
{
|
||||
ch = *(fmt++);
|
||||
lng = 1;
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
if (ch == 'l')
|
||||
{
|
||||
ch = *(fmt++);
|
||||
lng = 2;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
switch (ch)
|
||||
{
|
||||
case 0:
|
||||
goto abort;
|
||||
case 'u':
|
||||
p.base = 10;
|
||||
if (p.prec < 0)
|
||||
p.prec = 1;
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
if (2 == lng)
|
||||
ulli2a(va_arg(va, unsigned long long int), &p);
|
||||
else
|
||||
#endif
|
||||
if (1 == lng)
|
||||
uli2a(va_arg(va, unsigned long int), &p);
|
||||
else
|
||||
#endif
|
||||
ui2a(va_arg(va, unsigned int), &p);
|
||||
putchw(putp, putf, &p);
|
||||
break;
|
||||
case 'd':
|
||||
case 'i':
|
||||
p.base = 10;
|
||||
if (p.prec < 0)
|
||||
p.prec = 1;
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
if (2 == lng)
|
||||
lli2a(va_arg(va, long long int), &p);
|
||||
else
|
||||
#endif
|
||||
if (1 == lng)
|
||||
li2a(va_arg(va, long int), &p);
|
||||
else
|
||||
#endif
|
||||
i2a(va_arg(va, int), &p);
|
||||
putchw(putp, putf, &p);
|
||||
break;
|
||||
#ifdef SIZEOF_POINTER
|
||||
case 'p':
|
||||
p.alt = 1;
|
||||
#if defined(SIZEOF_INT) && SIZEOF_POINTER <= SIZEOF_INT
|
||||
lng = 0;
|
||||
#elif defined(SIZEOF_LONG) && SIZEOF_POINTER <= SIZEOF_LONG
|
||||
lng = 1;
|
||||
#elif defined(SIZEOF_LONG_LONG) && SIZEOF_POINTER <= SIZEOF_LONG_LONG
|
||||
lng = 2;
|
||||
#endif
|
||||
#endif
|
||||
case 'x':
|
||||
case 'X':
|
||||
p.base = 16;
|
||||
p.uc = (ch == 'X') ? 1 : 0;
|
||||
if (p.prec < 0)
|
||||
p.prec = 1;
|
||||
#ifdef PRINTF_LONG_SUPPORT
|
||||
#ifdef PRINTF_LONG_LONG_SUPPORT
|
||||
if (2 == lng)
|
||||
ulli2a(va_arg(va, unsigned long long int), &p);
|
||||
else
|
||||
#endif
|
||||
if (1 == lng)
|
||||
uli2a(va_arg(va, unsigned long int), &p);
|
||||
else
|
||||
#endif
|
||||
ui2a(va_arg(va, unsigned int), &p);
|
||||
putchw(putp, putf, &p);
|
||||
break;
|
||||
case 'o':
|
||||
p.base = 8;
|
||||
if (p.prec < 0)
|
||||
p.prec = 1;
|
||||
ui2a(va_arg(va, unsigned int), &p);
|
||||
putchw(putp, putf, &p);
|
||||
break;
|
||||
case 'c':
|
||||
putf(putp, (char)(va_arg(va, int)));
|
||||
break;
|
||||
case 's':
|
||||
{
|
||||
unsigned int prec = p.prec;
|
||||
char* b;
|
||||
p.bf = va_arg(va, char*);
|
||||
b = p.bf;
|
||||
while ((prec-- != 0) && *b++)
|
||||
{
|
||||
p.bf_len++;
|
||||
}
|
||||
p.prec = -1;
|
||||
putchw(putp, putf, &p);
|
||||
}
|
||||
break;
|
||||
case '%':
|
||||
putf(putp, ch);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
abort:;
|
||||
}
|
||||
|
||||
#if TINYPRINTF_DEFINE_TFP_PRINTF
|
||||
static putcf stdout_putf;
|
||||
static void* stdout_putp;
|
||||
|
||||
void init_printf(void* putp, putcf putf)
|
||||
{
|
||||
stdout_putf = putf;
|
||||
stdout_putp = putp;
|
||||
}
|
||||
|
||||
void tfp_printf(char* fmt, ...)
|
||||
{
|
||||
va_list va;
|
||||
va_start(va, fmt);
|
||||
tfp_format(stdout_putp, stdout_putf, fmt, va);
|
||||
va_end(va);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if TINYPRINTF_DEFINE_TFP_SPRINTF
|
||||
struct _vsnprintf_putcf_data
|
||||
{
|
||||
size_t dest_capacity;
|
||||
char* dest;
|
||||
size_t num_chars;
|
||||
};
|
||||
|
||||
static void _vsnprintf_putcf(void* p, char c)
|
||||
{
|
||||
struct _vsnprintf_putcf_data* data = (struct _vsnprintf_putcf_data*)p;
|
||||
if (data->num_chars < data->dest_capacity)
|
||||
data->dest[data->num_chars] = c;
|
||||
data->num_chars++;
|
||||
}
|
||||
|
||||
int tfp_vsnprintf(char* str, size_t size, const char* format, va_list ap)
|
||||
{
|
||||
struct _vsnprintf_putcf_data data;
|
||||
|
||||
if (size < 1)
|
||||
return 0;
|
||||
|
||||
data.dest = str;
|
||||
data.dest_capacity = size - 1;
|
||||
data.num_chars = 0;
|
||||
tfp_format(&data, _vsnprintf_putcf, format, ap);
|
||||
|
||||
if (data.num_chars < data.dest_capacity)
|
||||
data.dest[data.num_chars] = '\0';
|
||||
else
|
||||
data.dest[data.dest_capacity] = '\0';
|
||||
|
||||
return data.num_chars;
|
||||
}
|
||||
|
||||
int tfp_snprintf(char* str, size_t size, const char* format, ...)
|
||||
{
|
||||
va_list ap;
|
||||
int retval;
|
||||
|
||||
va_start(ap, format);
|
||||
retval = tfp_vsnprintf(str, size, format, ap);
|
||||
va_end(ap);
|
||||
return retval;
|
||||
}
|
||||
|
||||
struct _vsprintf_putcf_data
|
||||
{
|
||||
char* dest;
|
||||
size_t num_chars;
|
||||
};
|
||||
|
||||
static void _vsprintf_putcf(void* p, char c)
|
||||
{
|
||||
struct _vsprintf_putcf_data* data = (struct _vsprintf_putcf_data*)p;
|
||||
data->dest[data->num_chars++] = c;
|
||||
}
|
||||
|
||||
int tfp_vsprintf(char* str, const char* format, va_list ap)
|
||||
{
|
||||
struct _vsprintf_putcf_data data;
|
||||
data.dest = str;
|
||||
data.num_chars = 0;
|
||||
tfp_format(&data, _vsprintf_putcf, format, ap);
|
||||
data.dest[data.num_chars] = '\0';
|
||||
return data.num_chars;
|
||||
}
|
||||
|
||||
int tfp_sprintf(char* str, const char* format, ...)
|
||||
{
|
||||
va_list ap;
|
||||
int retval;
|
||||
|
||||
va_start(ap, format);
|
||||
retval = tfp_vsprintf(str, format, ap);
|
||||
va_end(ap);
|
||||
return retval;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Clear unused warnings for actually unused variables */
|
||||
#define UNUSED(x) (void)(x)
|
||||
|
||||
#include "atomic.h"
|
||||
#include "uarths.h"
|
||||
|
||||
static hartlock_t lock = HARTLOCK_INIT;
|
||||
|
||||
static void uart_putf(void* unused, char c)
|
||||
{
|
||||
UNUSED(unused);
|
||||
uart_putchar(c);
|
||||
}
|
||||
|
||||
int printk(const char* format, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, format);
|
||||
/* Begin protected code */
|
||||
hartlock_lock(&lock);
|
||||
tfp_format(stdout_putp, uart_putf, format, ap);
|
||||
/* End protected code */
|
||||
hartlock_unlock(&lock);
|
||||
va_end(ap);
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,71 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <common.h>
|
||||
#include <task.h>
|
||||
#include <sysctl.h>
|
||||
#include "sleep.h"
|
||||
|
||||
int nanosleep(const struct timespec* req, struct timespec* rem)
|
||||
{
|
||||
uint64_t clock_sleep_ms = (uint64_t)req->tv_sec * 1000;
|
||||
uint64_t nsec_ms = req->tv_nsec / 1000000;
|
||||
uint64_t nsec_trailing = req->tv_nsec % 1000000;
|
||||
|
||||
clock_sleep_ms += nsec_ms;
|
||||
|
||||
if (clock_sleep_ms)
|
||||
vTaskDelay(pdMS_TO_TICKS(clock_sleep_ms));
|
||||
|
||||
uint64_t microsecs = nsec_trailing / 1000;
|
||||
if (microsecs)
|
||||
{
|
||||
uint32_t cycles_per_microsec = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 3000000;
|
||||
while (microsecs--)
|
||||
{
|
||||
int i = cycles_per_microsec;
|
||||
while (i--)
|
||||
asm volatile("nop");
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int usleep(useconds_t usec)
|
||||
{
|
||||
/* clang-format off */
|
||||
struct timespec req =
|
||||
{
|
||||
.tv_sec = 0,
|
||||
.tv_nsec = usec * 1000
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
return nanosleep(&req, (struct timespec*)0x0);
|
||||
}
|
||||
|
||||
unsigned int sleep(unsigned int seconds)
|
||||
{
|
||||
/* clang-format off */
|
||||
struct timespec req =
|
||||
{
|
||||
.tv_sec = seconds,
|
||||
.tv_nsec = 0
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
return (unsigned int)nanosleep(&req, (struct timespec*)0x0);
|
||||
}
|
|
@ -0,0 +1,627 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/* Enable kernel-mode log API */
|
||||
#include <machine/syscall.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/unistd.h>
|
||||
#include <errno.h>
|
||||
#include <limits.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include "../freertos/device/devices.h"
|
||||
#include "atomic.h"
|
||||
#include "clint.h"
|
||||
#include "dump.h"
|
||||
#include "fpioa.h"
|
||||
#include "interrupt.h"
|
||||
#include "sysctl.h"
|
||||
#include "syslog.h"
|
||||
#include "uarths.h"
|
||||
|
||||
/*
|
||||
* @note System call list
|
||||
*
|
||||
* See also riscv-newlib/libgloss/riscv/syscalls.c
|
||||
*
|
||||
* | System call | Number |
|
||||
* |------------------|--------|
|
||||
* | SYS_exit | 93 |
|
||||
* | SYS_exit_group | 94 |
|
||||
* | SYS_getpid | 172 |
|
||||
* | SYS_kill | 129 |
|
||||
* | SYS_read | 63 |
|
||||
* | SYS_write | 64 |
|
||||
* | SYS_open | 1024 |
|
||||
* | SYS_openat | 56 |
|
||||
* | SYS_close | 57 |
|
||||
* | SYS_lseek | 62 |
|
||||
* | SYS_brk | 214 |
|
||||
* | SYS_link | 1025 |
|
||||
* | SYS_unlink | 1026 |
|
||||
* | SYS_mkdir | 1030 |
|
||||
* | SYS_chdir | 49 |
|
||||
* | SYS_getcwd | 17 |
|
||||
* | SYS_stat | 1038 |
|
||||
* | SYS_fstat | 80 |
|
||||
* | SYS_lstat | 1039 |
|
||||
* | SYS_fstatat | 79 |
|
||||
* | SYS_access | 1033 |
|
||||
* | SYS_faccessat | 48 |
|
||||
* | SYS_pread | 67 |
|
||||
* | SYS_pwrite | 68 |
|
||||
* | SYS_uname | 160 |
|
||||
* | SYS_getuid | 174 |
|
||||
* | SYS_geteuid | 175 |
|
||||
* | SYS_getgid | 176 |
|
||||
* | SYS_getegid | 177 |
|
||||
* | SYS_mmap | 222 |
|
||||
* | SYS_munmap | 215 |
|
||||
* | SYS_mremap | 216 |
|
||||
* | SYS_time | 1062 |
|
||||
* | SYS_getmainvars | 2011 |
|
||||
* | SYS_rt_sigaction | 134 |
|
||||
* | SYS_writev | 66 |
|
||||
* | SYS_gettimeofday | 169 |
|
||||
* | SYS_times | 153 |
|
||||
* | SYS_fcntl | 25 |
|
||||
* | SYS_getdents | 61 |
|
||||
* | SYS_dup | 23 |
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef UNUSED
|
||||
#define UNUSED(x) (void)(x)
|
||||
#endif
|
||||
|
||||
static const char* TAG = "SYSCALL";
|
||||
|
||||
extern char _heap_start[];
|
||||
extern char _heap_end[];
|
||||
char* _heap_cur = &_heap_start[0];
|
||||
|
||||
static void __attribute__((noreturn)) sys_exit(int code)
|
||||
{
|
||||
/* First print some diagnostic information. */
|
||||
LOGW(TAG, "sys_exit called with 0x%lx\n", (uint64_t)code);
|
||||
/* Write exit register to pause netlist simulation */
|
||||
volatile uint32_t* reg = (uint32_t*)&sysctl->peri;
|
||||
/* Write stop bit and write back */
|
||||
*reg = (*reg) | 0x80000000UL;
|
||||
/* Send 0 to uart */
|
||||
uart_putchar(0);
|
||||
while (1)
|
||||
continue;
|
||||
}
|
||||
|
||||
static int sys_nosys(long a0, long a1, long a2, long a3, long a4, long a5, unsigned long n)
|
||||
{
|
||||
UNUSED(a3);
|
||||
UNUSED(a4);
|
||||
UNUSED(a5);
|
||||
|
||||
LOGE(TAG, "Unsupported syscall %ld: a0=%lx, a1=%lx, a2=%lx!\n", n, a0, a1, a2);
|
||||
/* Send 0 to uart */
|
||||
uart_putchar(0);
|
||||
while (1)
|
||||
continue;
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
static int sys_success(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static size_t sys_brk(size_t pos)
|
||||
{
|
||||
uintptr_t res = 0;
|
||||
/*
|
||||
* brk() sets the end of the data segment to the value
|
||||
* specified by addr, when that value is reasonable, the system
|
||||
* has enough memory, and the process does not exceed its
|
||||
* maximum data size.
|
||||
*
|
||||
* sbrk() increments the program's data space by increment
|
||||
* bytes. Calling sbrk() with an increment of 0 can be used to
|
||||
* find the current location of the program break.
|
||||
*
|
||||
* uintptr_t brk(uintptr_t ptr);
|
||||
*
|
||||
* IN : regs[10] = ptr
|
||||
* OUT: regs[10] = ptr
|
||||
*/
|
||||
|
||||
/*
|
||||
* - First call: Initialization brk pointer. newlib will pass
|
||||
* ptr = 0 when it is first called. In this case the address
|
||||
* _heap_start will be return.
|
||||
*
|
||||
* - Call again: Adjust brk pointer. The ptr never equal with
|
||||
* 0. If ptr is below _heap_end, then allocate memory.
|
||||
* Otherwise throw out of memory error, return -1.
|
||||
*/
|
||||
|
||||
if (pos)
|
||||
{
|
||||
/* Call again */
|
||||
if ((uintptr_t)pos > (uintptr_t)&_heap_end[0])
|
||||
{
|
||||
/* Memory out, return -ENOMEM */
|
||||
LOGE(TAG, "Out of memory\n");
|
||||
res = -ENOMEM;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Adjust brk pointer. */
|
||||
_heap_cur = (char*)(uintptr_t)pos;
|
||||
/* Return current address. */
|
||||
res = (uintptr_t)_heap_cur;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* First call, return initial address */
|
||||
res = (uintptr_t)&_heap_start[0];
|
||||
}
|
||||
return (size_t)res;
|
||||
}
|
||||
|
||||
static ssize_t sys_write(int file, const void* ptr, size_t len)
|
||||
{
|
||||
/*
|
||||
* Write to a file.
|
||||
*
|
||||
* ssize_t write(int file, const void* ptr, size_t len)
|
||||
*
|
||||
* IN : regs[10] = file, regs[11] = ptr, regs[12] = len
|
||||
* OUT: regs[10] = len
|
||||
*/
|
||||
|
||||
ssize_t res = -EBADF;
|
||||
/* Get size to write */
|
||||
register size_t length = len;
|
||||
/* Get data pointer */
|
||||
register char* data = (char*)ptr;
|
||||
|
||||
if (STDOUT_FILENO == file || STDERR_FILENO == file)
|
||||
{
|
||||
/* Write data */
|
||||
while (length-- > 0 && *data != 0)
|
||||
uart_putchar(*(data++));
|
||||
|
||||
/* Return the actual size written */
|
||||
res = len;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Not support yet */
|
||||
res = io_write(file, data, length);
|
||||
;
|
||||
}
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int sys_open(const char* name, int flags, int mode)
|
||||
{
|
||||
UNUSED(flags);
|
||||
UNUSED(mode);
|
||||
|
||||
uintptr_t ptr = io_open(name);
|
||||
LOGD("SYSCALL", "%s: %lu\n", name, ptr);
|
||||
return ptr;
|
||||
}
|
||||
|
||||
static int sys_fstat(int file, struct stat* st)
|
||||
{
|
||||
int res = -EBADF;
|
||||
|
||||
/*
|
||||
* Status of an open file. The sys/stat.h header file required
|
||||
* is
|
||||
* distributed in the include subdirectory for this C library.
|
||||
*
|
||||
* int fstat(int file, struct stat* st)
|
||||
*
|
||||
* IN : regs[10] = file, regs[11] = st
|
||||
* OUT: regs[10] = Upon successful completion, 0 shall be
|
||||
* returned.
|
||||
* Otherwise, -1 shall be returned and errno set to indicate
|
||||
* the error.
|
||||
*/
|
||||
|
||||
UNUSED(file);
|
||||
|
||||
if (st != NULL)
|
||||
memset(st, 0, sizeof(struct stat));
|
||||
/* Return the result */
|
||||
res = -ENOSYS;
|
||||
/*
|
||||
* Note: This value will return to syscall wrapper, syscall
|
||||
* wrapper will set errno to ENOSYS and return -1
|
||||
*/
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
static int sys_close(int file)
|
||||
{
|
||||
/*
|
||||
* Close a file.
|
||||
*
|
||||
* int close(int file)
|
||||
*
|
||||
* IN : regs[10] = file
|
||||
* OUT: regs[10] = Upon successful completion, 0 shall be
|
||||
* returned.
|
||||
* Otherwise, -1 shall be returned and errno set to indicate
|
||||
* the error.
|
||||
*/
|
||||
return io_close(file);
|
||||
}
|
||||
|
||||
static int sys_gettimeofday(struct timeval* tp, void* tzp)
|
||||
{
|
||||
/*
|
||||
* Get the current time. Only relatively correct.
|
||||
*
|
||||
* int gettimeofday(struct timeval* tp, void* tzp)
|
||||
*
|
||||
* IN : regs[10] = tp
|
||||
* OUT: regs[10] = Upon successful completion, 0 shall be
|
||||
* returned.
|
||||
* Otherwise, -1 shall be returned and errno set to indicate
|
||||
* the error.
|
||||
*/
|
||||
UNUSED(tzp);
|
||||
|
||||
if (tp != NULL)
|
||||
{
|
||||
uint64_t clint_usec = clint->mtime * CLINT_CLOCK_DIV / (sysctl_clock_get_freq(SYSCTL_CLOCK_CPU) / 1000000UL);
|
||||
|
||||
tp->tv_sec = clint_usec / 1000000UL;
|
||||
tp->tv_usec = clint_usec % 1000000UL;
|
||||
}
|
||||
/* Return the result */
|
||||
return 0;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_ecall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
UNUSED(cause);
|
||||
UNUSED(fregs);
|
||||
enum syscall_id_e
|
||||
{
|
||||
SYS_ID_NOSYS,
|
||||
SYS_ID_SUCCESS,
|
||||
SYS_ID_EXIT,
|
||||
SYS_ID_BRK,
|
||||
SYS_ID_WRITE,
|
||||
SYS_ID_OPEN,
|
||||
SYS_ID_FSTAT,
|
||||
SYS_ID_CLOSE,
|
||||
SYS_ID_GETTIMEOFDAY,
|
||||
SYS_ID_MAX
|
||||
};
|
||||
|
||||
static uintptr_t (*const syscall_table[])(long a0, long a1, long a2, long a3, long a4, long a5, unsigned long n) = {
|
||||
[SYS_ID_NOSYS] = (void*)sys_nosys,
|
||||
[SYS_ID_SUCCESS] = (void*)sys_success,
|
||||
[SYS_ID_EXIT] = (void*)sys_exit,
|
||||
[SYS_ID_BRK] = (void*)sys_brk,
|
||||
[SYS_ID_WRITE] = (void*)sys_write,
|
||||
[SYS_ID_OPEN] = (void*)sys_open,
|
||||
[SYS_ID_FSTAT] = (void*)sys_fstat,
|
||||
[SYS_ID_CLOSE] = (void*)sys_close,
|
||||
[SYS_ID_GETTIMEOFDAY] = (void*)sys_gettimeofday,
|
||||
};
|
||||
|
||||
#if defined(__GNUC__)
|
||||
#pragma GCC diagnostic ignored "-Woverride-init"
|
||||
#endif
|
||||
static const uint8_t syscall_id_table[0x100] = {
|
||||
[0x00 ... 0xFF] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_exit] = SYS_ID_EXIT,
|
||||
[0xFF & SYS_exit_group] = SYS_ID_EXIT,
|
||||
[0xFF & SYS_getpid] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_kill] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_read] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_write] = SYS_ID_WRITE,
|
||||
[0xFF & SYS_open] = SYS_ID_OPEN,
|
||||
[0xFF & SYS_openat] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_close] = SYS_ID_CLOSE,
|
||||
[0xFF & SYS_lseek] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_brk] = SYS_ID_BRK,
|
||||
[0xFF & SYS_link] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_unlink] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_mkdir] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_chdir] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_getcwd] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_stat] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_fstat] = SYS_ID_FSTAT,
|
||||
[0xFF & SYS_lstat] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_fstatat] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_access] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_faccessat] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_pread] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_pwrite] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_uname] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_getuid] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_geteuid] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_getgid] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_getegid] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_mmap] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_munmap] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_mremap] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_time] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_getmainvars] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_rt_sigaction] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_writev] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_gettimeofday] = SYS_ID_GETTIMEOFDAY,
|
||||
[0xFF & SYS_times] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_fcntl] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_getdents] = SYS_ID_NOSYS,
|
||||
[0xFF & SYS_dup] = SYS_ID_NOSYS,
|
||||
};
|
||||
#if defined(__GNUC__)
|
||||
#pragma GCC diagnostic warning "-Woverride-init"
|
||||
#endif
|
||||
|
||||
regs[10] = syscall_table[syscall_id_table[0xFF & regs[17]]](
|
||||
regs[10], /* a0 */
|
||||
regs[11], /* a1 */
|
||||
regs[12], /* a2 */
|
||||
regs[13], /* a3 */
|
||||
regs[14], /* a4 */
|
||||
regs[15], /* a5 */
|
||||
regs[17] /* n */
|
||||
);
|
||||
|
||||
return epc + ((*(unsigned short*)epc & 3) == 3 ? 4 : 2);
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_ecall")))
|
||||
handle_ecall_u(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_ecall")))
|
||||
handle_ecall_h(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_ecall")))
|
||||
handle_ecall_s(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak, alias("handle_ecall")))
|
||||
handle_ecall_m(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]);
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_misaligned_fetch(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("misaligned fetch", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_fault_fetch(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("fault fetch", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_illegal_instruction(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("illegal instruction", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_breakpoint(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("breakpoint", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_misaligned_load(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
/* notice this function only support 16bit or 32bit instruction */
|
||||
|
||||
bool compressed = (*(unsigned short*)epc & 3) != 3;
|
||||
bool fpu = 0; /*!< load to fpu ? */
|
||||
uintptr_t addr = 0; /*!< src addr */
|
||||
uint8_t src = 0; /*!< src register */
|
||||
uint8_t dst = 0; /*!< dst register */
|
||||
uint8_t len = 0; /*!< data length */
|
||||
int offset = 0; /*!< addr offset to addr in reg */
|
||||
bool unsigned_ = 0; /*!< unsigned */
|
||||
uint64_t data_load = 0; /*!< real data load */
|
||||
int i;
|
||||
|
||||
if (compressed)
|
||||
{
|
||||
/* compressed instruction should not get this fault. */
|
||||
goto on_error;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t instruct = *(uint32_t*)epc;
|
||||
uint8_t opcode = instruct & 0x7F;
|
||||
|
||||
dst = (instruct >> 7) & 0x1F;
|
||||
len = (instruct >> 12) & 3;
|
||||
unsigned_ = (instruct >> 14) & 1;
|
||||
src = (instruct >> 15) & 0x1F;
|
||||
offset = (instruct >> 20);
|
||||
len = 1 << len;
|
||||
switch (opcode)
|
||||
{
|
||||
case 3: /*!< load */
|
||||
break;
|
||||
case 7: /*!< fpu load */
|
||||
fpu = 1;
|
||||
break;
|
||||
default:
|
||||
goto on_error;
|
||||
}
|
||||
}
|
||||
|
||||
if (offset >> 11)
|
||||
offset = -((offset & 0x3FF) + 1);
|
||||
|
||||
addr = (uint64_t)((uint64_t)regs[src] + offset);
|
||||
|
||||
for (i = 0; i < len; ++i)
|
||||
data_load |= ((uint64_t) * ((uint8_t*)addr + i)) << (8 * i);
|
||||
|
||||
if (!unsigned_ & !fpu)
|
||||
{
|
||||
/* adjust sign */
|
||||
switch (len)
|
||||
{
|
||||
case 1:
|
||||
data_load = (uint64_t)(int64_t)((int8_t)data_load);
|
||||
break;
|
||||
case 2:
|
||||
data_load = (uint64_t)(int64_t)((int16_t)data_load);
|
||||
break;
|
||||
case 4:
|
||||
data_load = (uint64_t)(int64_t)((int32_t)data_load);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (fpu)
|
||||
fregs[dst] = data_load;
|
||||
else
|
||||
regs[dst] = data_load;
|
||||
|
||||
LOGV(TAG, "misaligned load recovered at %08lx. len:%02d,addr:%08lx,reg:%02d,data:%016lx,signed:%1d,float:%1d", (uint64_t)epc, len, (uint64_t)addr, dst, data_load, !unsigned_, fpu);
|
||||
|
||||
return epc + (compressed ? 2 : 4);
|
||||
on_error:
|
||||
dump_core("misaligned load", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_fault_load(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("fault load", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_misaligned_store(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
/* notice this function only support 16bit or 32bit instruction */
|
||||
|
||||
bool compressed = (*(unsigned short*)epc & 3) != 3;
|
||||
bool fpu = 0; /*!< load to fpu ? */
|
||||
uintptr_t addr = 0; /*!< src addr */
|
||||
uint8_t src = 0; /*!< src register */
|
||||
uint8_t dst = 0; /*!< dst register */
|
||||
uint8_t len = 0; /*!< data length */
|
||||
int offset = 0; /*!< addr offset to addr in reg */
|
||||
uint64_t data_store = 0; /*!< real data store */
|
||||
int i;
|
||||
|
||||
if (compressed)
|
||||
{
|
||||
/* compressed instruction should not get this fault. */
|
||||
goto on_error;
|
||||
}
|
||||
else
|
||||
{
|
||||
uint32_t instruct = *(uint32_t*)epc;
|
||||
uint8_t opcode = instruct & 0x7F;
|
||||
|
||||
len = (instruct >> 12) & 7;
|
||||
dst = (instruct >> 15) & 0x1F;
|
||||
src = (instruct >> 20) & 0x1F;
|
||||
offset = ((instruct >> 7) & 0x1F) | ((instruct >> 20) & 0xFE0);
|
||||
len = 1 << len;
|
||||
switch (opcode)
|
||||
{
|
||||
case 0x23: /*!< load */
|
||||
break;
|
||||
case 0x27: /*!< fpu store */
|
||||
fpu = 1;
|
||||
break;
|
||||
default:
|
||||
goto on_error;
|
||||
}
|
||||
}
|
||||
|
||||
if (offset >> 11)
|
||||
offset = -((offset & 0x3FF) + 1);
|
||||
|
||||
addr = (uint64_t)((uint64_t)regs[dst] + offset);
|
||||
|
||||
if (fpu)
|
||||
data_store = fregs[src];
|
||||
else
|
||||
data_store = regs[src];
|
||||
|
||||
for (i = 0; i < len; ++i)
|
||||
*((uint8_t*)addr + i) = (data_store >> (i * 8)) & 0xFF;
|
||||
|
||||
LOGV(TAG, "misaligned store recovered at %08lx. len:%02d,addr:%08lx,reg:%02d,data:%016lx,float:%1d", (uint64_t)epc, len, (uint64_t)addr, src, data_store, fpu);
|
||||
|
||||
return epc + (compressed ? 2 : 4);
|
||||
on_error:
|
||||
dump_core("misaligned store", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t __attribute__((weak))
|
||||
handle_fault_store(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
dump_core("fault store", cause, epc, regs, fregs);
|
||||
exit(1337);
|
||||
return epc;
|
||||
}
|
||||
|
||||
uintptr_t handle_syscall(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32])
|
||||
{
|
||||
|
||||
static uintptr_t (*const cause_table[])(uintptr_t cause, uintptr_t epc, uintptr_t regs[32], uintptr_t fregs[32]) = {
|
||||
[CAUSE_MISALIGNED_FETCH] = handle_misaligned_fetch,
|
||||
[CAUSE_FAULT_FETCH] = handle_fault_fetch,
|
||||
[CAUSE_ILLEGAL_INSTRUCTION] = handle_illegal_instruction,
|
||||
[CAUSE_BREAKPOINT] = handle_breakpoint,
|
||||
[CAUSE_MISALIGNED_LOAD] = handle_misaligned_load,
|
||||
[CAUSE_FAULT_LOAD] = handle_fault_load,
|
||||
[CAUSE_MISALIGNED_STORE] = handle_misaligned_store,
|
||||
[CAUSE_FAULT_STORE] = handle_fault_store,
|
||||
[CAUSE_USER_ECALL] = handle_ecall_u,
|
||||
[CAUSE_SUPERVISOR_ECALL] = handle_ecall_h,
|
||||
[CAUSE_HYPERVISOR_ECALL] = handle_ecall_s,
|
||||
[CAUSE_MACHINE_ECALL] = handle_ecall_m,
|
||||
};
|
||||
|
||||
return cause_table[cause](cause, epc, regs, fregs);
|
||||
}
|
|
@ -0,0 +1,64 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "encoding.h"
|
||||
#include "clint.h"
|
||||
#include "sysctl.h"
|
||||
|
||||
volatile struct clint_t* const clint = (volatile struct clint_t*)CLINT_BASE_ADDR;
|
||||
|
||||
int clint_ipi_init(void)
|
||||
{
|
||||
/* Clear the Machine-Software bit in MIE */
|
||||
clear_csr(mie, MIP_MSIP);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clint_ipi_enable(void)
|
||||
{
|
||||
/* Enable interrupts in general */
|
||||
set_csr(mstatus, MSTATUS_MIE);
|
||||
/* Set the Machine-Software bit in MIE */
|
||||
set_csr(mie, MIP_MSIP);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clint_ipi_disable(void)
|
||||
{
|
||||
/* Clear the Machine-Software bit in MIE */
|
||||
clear_csr(mie, MIP_MSIP);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clint_ipi_send(size_t hart_id)
|
||||
{
|
||||
if (hart_id >= CLINT_NUM_HARTS)
|
||||
return -1;
|
||||
clint->msip[hart_id].msip = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int clint_ipi_clear(size_t hart_id)
|
||||
{
|
||||
if (hart_id >= CLINT_NUM_HARTS)
|
||||
return -1;
|
||||
if (clint->msip[hart_id].msip)
|
||||
{
|
||||
clint->msip[hart_id].msip = 0;
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,92 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_AES_H
|
||||
#define _DRIVER_AES_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "encoding.h"
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct _aes_mode_ctl
|
||||
{
|
||||
/* set the first bit and second bit 00:ecb; 01:cbc,10:aes_gcm */
|
||||
uint32_t cipher_mode : 3;
|
||||
/* [4:3]:00:128; 01:192; 10:256;11:reserved*/
|
||||
uint32_t kmode : 2;
|
||||
uint32_t endian : 6;
|
||||
uint32_t stream_mode : 3;
|
||||
uint32_t reserved : 18;
|
||||
} __attribute__((packed, aligned(4))) aes_mode_ctl;
|
||||
|
||||
/**
|
||||
* @brief AES
|
||||
*/
|
||||
typedef struct _aes
|
||||
{
|
||||
uint32_t aes_key[4];
|
||||
/* 0: encrption ; 1: dencrption */
|
||||
uint32_t encrypt_sel;
|
||||
/**
|
||||
* [1:0], Set the first bit and second bit 00:ecb; 01:cbc;
|
||||
* 10,11:aes_gcm
|
||||
*/
|
||||
aes_mode_ctl mode_ctl;
|
||||
uint32_t aes_iv[4];
|
||||
/* aes interrupt enable */
|
||||
uint32_t aes_endian;
|
||||
/* aes interrupt flag */
|
||||
uint32_t aes_finish;
|
||||
/* gcm add data begin address */
|
||||
uint32_t dma_sel;
|
||||
/* gcm add data end address */
|
||||
uint32_t gb_aad_end_adr;
|
||||
/* gcm plantext/ciphter text data begin address */
|
||||
uint32_t gb_pc_ini_adr;
|
||||
/* gcm plantext/ciphter text data end address */
|
||||
uint32_t gb_pc_end_adr;
|
||||
/* gcm plantext/ciphter text data */
|
||||
uint32_t aes_text_data;
|
||||
/* AAD data */
|
||||
uint32_t aes_aad_data;
|
||||
/**
|
||||
* [1:0],00:check not finish; 01: check fail; 10: check success;11:
|
||||
* reversed
|
||||
*/
|
||||
uint32_t tag_chk;
|
||||
/* data can input flag 1: data can input; 0 : data cannot input */
|
||||
uint32_t data_in_flag;
|
||||
/* gcm input tag for compare with the calculate tag */
|
||||
uint32_t gcm_in_tag[4];
|
||||
/* gcm plantext/ciphter text data */
|
||||
uint32_t aes_out_data;
|
||||
uint32_t gb_aes_en;
|
||||
/* data can output flag 1: data ready 0: data not ready */
|
||||
uint32_t data_out_flag;
|
||||
/* allow tag input when use GCM */
|
||||
uint32_t tag_in_flag;
|
||||
uint32_t tag_clear;
|
||||
uint32_t gcm_out_tag[4];
|
||||
uint32_t aes_key_ext[4];
|
||||
} __attribute__((packed, aligned(4))) aes_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_AES_H */
|
|
@ -0,0 +1,331 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_AUDIO_BF_H
|
||||
#define _DRIVER_AUDIO_BF_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern volatile struct audio_bf_reg_t* const audio_bf;
|
||||
|
||||
enum en_bf_dir
|
||||
{
|
||||
BF_DIR0 = 0,
|
||||
BF_DIR1,
|
||||
BF_DIR2,
|
||||
BF_DIR3,
|
||||
BF_DIR4,
|
||||
BF_DIR5,
|
||||
BF_DIR6,
|
||||
BF_DIR7,
|
||||
BF_DIR8,
|
||||
BF_DIR9,
|
||||
BF_DIR10,
|
||||
BF_DIR11,
|
||||
BF_DIR12,
|
||||
BF_DIR13,
|
||||
BF_DIR14,
|
||||
BF_DIR15,
|
||||
};
|
||||
|
||||
struct audio_bf_ch_cfg_t
|
||||
{
|
||||
/**
|
||||
* BF unit sound channel enable control bits.
|
||||
* Bit 'x' corresponds to enable bit for sound channel 'x' (x = 0, 1, 2,
|
||||
* . . ., 7). BF sound channels are related with I2S host RX channels.
|
||||
* BF sound channel 0/1 correspond to the left/right channel of I2S RX0;
|
||||
* BF channel 2/3 correspond to left/right channels of I2S RX1; and
|
||||
* things like that. 0x1: writing '1' to enable the corresponding BF
|
||||
* sound channel. 0x0: writing '0' to close the corresponding BF sound
|
||||
* channel.
|
||||
*/
|
||||
uint32_t bf_sound_ch_en : 8;
|
||||
/**
|
||||
* Target direction select for valid voice output.
|
||||
* When the source voice direaction searching is done, software can use
|
||||
* this field to select one from 16 sound directions for the following
|
||||
* voice recognition. 0x0: select sound direction 0; 0x1: select sound
|
||||
* direction 1; . . . . . . 0xF: select sound direction 15.
|
||||
*/
|
||||
uint32_t bf_target_dir : 4;
|
||||
/**
|
||||
* This is the audio sample gain factor. Using this gain factor to
|
||||
* enhance or reduce the stength of the sum of at most 8 source
|
||||
* sound channel outputs. This is a unsigned 11-bit fix-point number,
|
||||
* bit 10 is integer part and bit 9~0 are the fractional part.
|
||||
*/
|
||||
uint32_t audio_gain : 11;
|
||||
uint32_t reserved1 : 1;
|
||||
/**
|
||||
* audio data source configure parameter. This parameter controls where
|
||||
* the audio data source comes from. 0x0: audio data directly sourcing
|
||||
* from audio_bf internal buffer; 0x1: audio data sourcing from
|
||||
* FFT result buffer.
|
||||
*/
|
||||
uint32_t data_src_mode : 1;
|
||||
uint32_t reserved2 : 3;
|
||||
/**
|
||||
* write enable for bf_sound_ch_en parameter.
|
||||
* 0x1: allowing updates made to 'bf_sound_ch_en'.
|
||||
* Access Mode: write only
|
||||
*/
|
||||
uint32_t we_bf_sound_ch_en : 1;
|
||||
/**
|
||||
* write enable for bf_target_dir parameter.
|
||||
* 0x1: allowing updates made to 'bf_target_dir'.
|
||||
* Access Mode: write only
|
||||
*/
|
||||
uint32_t we_bf_target_dir : 1;
|
||||
/**
|
||||
* write enable for audio_gain parameter.
|
||||
* 0x1: allowing updates made to 'audio_gain'.
|
||||
* Access Mode: write only
|
||||
*/
|
||||
uint32_t we_audio_gain : 1;
|
||||
/**
|
||||
* write enable for data_out_mode parameter.
|
||||
* 0x1: allowing updates made to 'data_src_mode'.
|
||||
*/
|
||||
uint32_t we_data_src_mode : 1;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_ctl_t
|
||||
{
|
||||
/**
|
||||
* Sound direction searching enable bit.
|
||||
* Software writes '1' to start sound direction searching function.
|
||||
* When all the sound sample buffers are filled full, this bit is
|
||||
* cleared by hardware (this sample buffers are used for direction
|
||||
* detect only). 0x1: enable direction searching.
|
||||
*/
|
||||
uint32_t bf_dir_search_en : 1;
|
||||
/*
|
||||
*use this parameter to reset all the control logic on direction search processing path. This bit is self-clearing.
|
||||
* 0x1: apply reset to direction searching control logic;
|
||||
* 0x0: No operation.
|
||||
*/
|
||||
uint32_t search_path_reset : 1;
|
||||
uint32_t reserved : 2;
|
||||
/**
|
||||
* Valid voice sample stream generation enable bit.
|
||||
* After sound direction searching is done, software can configure this
|
||||
* bit to generate a stream of voice samples for voice recognition. 0x1:
|
||||
* enable output of voice sample stream. 0x0: stop the voice samlpe
|
||||
* stream output.
|
||||
*/
|
||||
uint32_t bf_stream_gen_en : 1;
|
||||
/*
|
||||
*use this parameter to reset all the control logic on voice stream generating path. This bit is self-clearing.
|
||||
* 0x1: apply reset to voice stream generating control logic;
|
||||
* 0x0: No operation.
|
||||
*/
|
||||
uint32_t voice_gen_path_reset : 1;
|
||||
/*
|
||||
*use this parameter to switch to a new voice source direction. Software write '1' here and hardware will automatically clear it.
|
||||
* 0x1: write '1' here to request switching to new voice source direction.
|
||||
*/
|
||||
uint32_t update_voice_dir : 1;
|
||||
|
||||
uint32_t reserved1 : 1;
|
||||
//write enable for 'bf_dir_search_en' parameter.
|
||||
uint32_t we_bf_dir_search_en : 1;
|
||||
uint32_t we_search_path_rst : 1;
|
||||
uint32_t we_bf_stream_gen : 1;
|
||||
uint32_t we_voice_gen_path_rst : 1;
|
||||
uint32_t we_update_voice_dir : 1;
|
||||
uint32_t reserved2 : 19;
|
||||
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_dir_bidx_t
|
||||
{
|
||||
uint32_t dir_rd_idx0 : 6;
|
||||
uint32_t reserved : 2;
|
||||
uint32_t dir_rd_idx1 : 6;
|
||||
uint32_t reserved1 : 2;
|
||||
uint32_t dir_rd_idx2 : 6;
|
||||
uint32_t reserved2 : 2;
|
||||
uint32_t dir_rd_idx3 : 6;
|
||||
uint32_t reserved3 : 2;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_fir_coef_t
|
||||
{
|
||||
uint32_t fir_tap0 : 16;
|
||||
uint32_t fir_tap1 : 16;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_dwsz_cfg_t
|
||||
{
|
||||
/**
|
||||
* TThe down-sizing ratio used for direction searching.
|
||||
* 0x0: no down-sizing;
|
||||
* 0x1: 1/2 down sizing;
|
||||
* 0x2: 1/3 down sizing;
|
||||
* . . . . . .
|
||||
* 0xF: 1/16 down sizing.
|
||||
*/
|
||||
uint32_t dir_dwn_siz_rate : 4;
|
||||
/**
|
||||
* The down-sizing ratio used for voice stream generation.
|
||||
* 0x0: no down-sizing;
|
||||
* 0x1: 1/2 down sizing;
|
||||
* 0x2: 1/3 down sizing;
|
||||
* . . . . . .
|
||||
* 0xF: 1/16 down sizing.
|
||||
*/
|
||||
uint32_t voc_dwn_siz_rate : 4;
|
||||
/**
|
||||
* This bit field is used to perform sample precision reduction when
|
||||
* the source sound sample (from I2S0 host receiving channels)
|
||||
* precision is 20/24/32 bits.
|
||||
* 0x0: take bits 15~0 from the source sound sample;
|
||||
* 0x1: take bits 16~1 from the source sound sample;
|
||||
* 0x2: take bits 17~2 from the source sound sample;
|
||||
* . . . . . .
|
||||
* 0x10: take bits 31~16 from the source sound sample;
|
||||
*/
|
||||
uint32_t smpl_shift_bits : 5;
|
||||
uint32_t reserved : 19;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_fft_cfg_t
|
||||
{
|
||||
uint32_t fft_shift_factor : 9;
|
||||
uint32_t reserved1 : 3;
|
||||
uint32_t fft_enable : 1;
|
||||
uint32_t reserved2 : 19;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_int_stat_t
|
||||
{
|
||||
/**
|
||||
* sound direction searching data ready interrupt event.
|
||||
* Writing '1' to clear this interrupt event.
|
||||
* 0x1: data is ready for sound direction detect;
|
||||
* 0x0: no event.
|
||||
*/
|
||||
uint32_t dir_search_data_rdy : 1;
|
||||
/**
|
||||
* voice output stream buffer data ready interrupt event.
|
||||
* When a block of 512 voice samples are collected, this interrupt event
|
||||
* is asserted. Writing '1' to clear this interrupt event. 0x1: voice
|
||||
* output stream buffer data is ready; 0x0: no event.
|
||||
*/
|
||||
uint32_t voc_buf_data_rdy : 1;
|
||||
uint32_t reserved : 30;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_int_mask_t
|
||||
{
|
||||
/**
|
||||
* This is the interrupt mask to dir searching data ready interrupt.
|
||||
* 0x1: mask off this interrupt;
|
||||
* 0x0: enable this interrupt.
|
||||
*/
|
||||
uint32_t dir_data_rdy_msk : 1;
|
||||
/**
|
||||
* This is the interrupt mask to voice output stream buffer ready
|
||||
* interrupt. 0x1: mask off this interrupt; 0x0: enable this interrupt.
|
||||
*/
|
||||
uint32_t voc_buf_rdy_msk : 1;
|
||||
uint32_t reserved : 30;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct audio_bf_reg_t
|
||||
{
|
||||
/* 0x200 */
|
||||
struct audio_bf_ch_cfg_t bf_ch_cfg_reg;
|
||||
/* 0x204 */
|
||||
struct audio_bf_ctl_t bf_ctl_reg;
|
||||
/* 0x208 */
|
||||
struct audio_bf_dir_bidx_t bf_dir_bidx[16][2];
|
||||
/* 0x288 */
|
||||
struct audio_bf_fir_coef_t bf_pre_fir0_coef[9];
|
||||
/* 0x2ac */
|
||||
struct audio_bf_fir_coef_t bf_post_fir0_coef[9];
|
||||
/* 0x2d0 */
|
||||
struct audio_bf_fir_coef_t bf_pre_fir1_coef[9];
|
||||
/* 0x2f4 */
|
||||
struct audio_bf_fir_coef_t bf_post_fir1_coef[9];
|
||||
/* 0x318 */
|
||||
struct audio_bf_dwsz_cfg_t bf_dwsz_cfg_reg;
|
||||
/* 0x31c */
|
||||
struct audio_bf_fft_cfg_t bf_fft_cfg_reg;
|
||||
/* 0x320 */
|
||||
/**
|
||||
* This is the read register for system DMA to read data stored in
|
||||
* sample out buffers (the sample out buffers are used for sound
|
||||
* direction detect). Each data contains two sound samples.
|
||||
*/
|
||||
volatile uint32_t sobuf_dma_rdata;
|
||||
/* 0x324 */
|
||||
/**
|
||||
* This is the read register for system DMA to read data stored in voice
|
||||
* out buffers (the voice out buffers are used for voice recognition).
|
||||
* Each data contains two sound samples.
|
||||
*/
|
||||
volatile uint32_t vobuf_dma_rdata;
|
||||
/* 0x328 */
|
||||
struct audio_bf_int_stat_t bf_int_stat_reg;
|
||||
/* 0x32c */
|
||||
struct audio_bf_int_mask_t bf_int_mask_reg;
|
||||
/* 0x330 */
|
||||
uint32_t saturation_counter;
|
||||
/* 0x334 */
|
||||
uint32_t saturation_limits;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
void audio_bf_set_audio_gain(uint16_t gain);
|
||||
void audio_bf_set_smpl_shift(uint8_t smpl_shift);
|
||||
uint8_t audio_bf_get_smpl_shift(void);
|
||||
void audio_bf_set_channel_enabled(uint8_t channel_bit);
|
||||
void audio_bf_set_direction_delay(uint8_t dir_num, uint8_t* dir_bidx);
|
||||
void audio_bf_set_fft_shift_factor(uint8_t enable_flag, uint16_t shift_factor);
|
||||
void audio_bf_set_down_size(uint8_t dir_dwn_siz, uint8_t voc_dwn_siz);
|
||||
void audio_bf_set_interrupt_mask(uint8_t dir_int_mask, uint8_t voc_int_mask);
|
||||
|
||||
void audio_bf_dir_enable(void);
|
||||
void audio_bf_dir_reset(void);
|
||||
void audio_bf_dir_set_prev_fir(uint16_t* fir_coef);
|
||||
void audio_bf_dir_set_post_fir(uint16_t* fir_coef);
|
||||
void audio_bf_dir_set_down_size(uint8_t dir_dwn_size);
|
||||
void audio_bf_dir_set_interrupt_mask(uint8_t dir_int_mask);
|
||||
void audio_bf_dir_clear_int_state(void);
|
||||
|
||||
void audio_bf_voc_enable(uint8_t enable_flag);
|
||||
void audio_bf_voc_reset(void);
|
||||
void audio_bf_voc_set_direction(enum en_bf_dir direction);
|
||||
void audio_bf_voc_set_prev_fir(uint16_t* fir_coef);
|
||||
void audio_bf_voc_set_post_fir(uint16_t* fir_coef);
|
||||
void audio_bf_voc_set_down_size(uint8_t voc_dwn_size);
|
||||
void audio_bf_voc_set_interrupt_mask(uint8_t voc_int_mask);
|
||||
void audio_bf_voc_clear_int_state(void);
|
||||
void audio_bf_voc_reset_saturation_counter(void);
|
||||
uint32_t audio_bf_voc_get_saturation_counter(void);
|
||||
void audio_bf_voc_set_saturation_limit(uint16_t upper, uint16_t bottom);
|
||||
uint32_t audio_bf_voc_get_saturation_limit(void);
|
||||
|
||||
void audio_bf_print_setting(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_AUDIO_BF_H */
|
|
@ -0,0 +1,189 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief The CLINT block holds memory-mapped control and status registers
|
||||
* associated with local interrupts for a Coreplex.
|
||||
*
|
||||
* @note CLINT RAM Layout
|
||||
*
|
||||
* | Address -| Description |
|
||||
* |------------|---------------------------------|
|
||||
* | 0x02000000 | msip for hart 0 |
|
||||
* | 0x02000004 | msip for hart 1 |
|
||||
* | ... | ... |
|
||||
* | 0x02003FF8 | msip for hart 4094 |
|
||||
* | | |
|
||||
* | 0x02004000 | mtimecmp for hart 0 |
|
||||
* | 0x02004008 | mtimecmp for hart 1 |
|
||||
* | ... | ... |
|
||||
* | 0x0200BFF0 | mtimecmp For hart 4094 |
|
||||
* | 0x0200BFF8 | mtime |
|
||||
* | | |
|
||||
* | 0x0200C000 | Reserved |
|
||||
* | ... | ... |
|
||||
* | 0x0200EFFC | Reserved |
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_CLINT_H
|
||||
#define _DRIVER_CLINT_H
|
||||
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
/* Register address offsets */
|
||||
#define CLINT_MSIP (0x0000)
|
||||
#define CLINT_MSIP_SIZE (0x4)
|
||||
#define CLINT_MTIMECMP (0x4000)
|
||||
#define CLINT_MTIMECMP_SIZE (0x8)
|
||||
#define CLINT_MTIME (0xBFF8)
|
||||
#define CLINT_MTIME_SIZE (0x8)
|
||||
/* Max number of cores */
|
||||
#define CLINT_MAX_HARTS (4095)
|
||||
/* Real number of cores */
|
||||
#define CLINT_NUM_HARTS (2)
|
||||
/* Clock frequency division factor */
|
||||
#define CLINT_CLOCK_DIV (50)
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief MSIP Registers
|
||||
*
|
||||
* Machine-mode software interrupts are generated by writing to a
|
||||
* per-hart memory-mapped control register. The msip registers are
|
||||
* 32-bit wide WARL registers, where the LSB is reflected in the
|
||||
* msip bit of the associated hart’s mip register. Other bits in
|
||||
* the msip registers are hardwired to zero. The mapping supports
|
||||
* up to 4095 machine-mode harts.
|
||||
*/
|
||||
struct clint_msip_t
|
||||
{
|
||||
uint32_t msip : 1; /*!< Bit 0 is msip */
|
||||
uint32_t zero : 31; /*!< Bits [32:1] is 0 */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Timer compare Registers Machine-mode timer interrupts are
|
||||
* generated by a real-time counter and a per-hart comparator. The
|
||||
* mtime register is a 64-bit read-only register that contains the
|
||||
* current value of the real-time counter. Each mtimecmp register
|
||||
* holds its hart’s time comparator. A timer interrupt is pending
|
||||
* whenever mtime is greater than or equal to the value in a
|
||||
* hart’s mtimecmp register. The timer interrupt is reflected in
|
||||
* the mtip bit of the associated hart’s mip register.
|
||||
*/
|
||||
typedef uint64_t clint_mtimecmp_t;
|
||||
|
||||
/**
|
||||
* @brief Timer Registers
|
||||
*
|
||||
* The mtime register has a 64-bit precision on all RV32, RV64,
|
||||
* and RV128 systems. Platforms provide a 64-bit memory-mapped
|
||||
* machine-mode timer compare register (mtimecmp), which causes a
|
||||
* timer interrupt to be posted when the mtime register contains a
|
||||
* value greater than or equal to the value in the mtimecmp
|
||||
* register. The interrupt remains posted until it is cleared by
|
||||
* writing the mtimecmp register. The interrupt will only be taken
|
||||
* if interrupts are enabled and the MTIE bit is set in the mie
|
||||
* register.
|
||||
*/
|
||||
typedef uint64_t clint_mtime_t;
|
||||
|
||||
/**
|
||||
* @brief CLINT object
|
||||
*
|
||||
* Coreplex-Local INTerrupts, which includes software interrupts,
|
||||
* local timer interrupts, and other interrupts routed directly to
|
||||
* a core.
|
||||
*/
|
||||
struct clint_t
|
||||
{
|
||||
/* 0x0000 to 0x3FF8, MSIP Registers */
|
||||
struct clint_msip_t msip[CLINT_MAX_HARTS];
|
||||
/* Resverd space, do not use */
|
||||
uint32_t resv0;
|
||||
/* 0x4000 to 0xBFF0, Timer Compare Registers */
|
||||
clint_mtimecmp_t mtimecmp[CLINT_MAX_HARTS];
|
||||
/* 0xBFF8, Time Register */
|
||||
clint_mtime_t mtime;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Clint object instanse
|
||||
*/
|
||||
extern volatile struct clint_t* const clint;
|
||||
|
||||
/**
|
||||
* @brief Initialize local interprocessor interrupt
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int clint_ipi_init(void);
|
||||
|
||||
/**
|
||||
* @brief Enable local interprocessor interrupt
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int clint_ipi_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable local interprocessor interrupt
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int clint_ipi_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Send local interprocessor interrupt to core by hart id
|
||||
*
|
||||
* @param[in] hart_id The hart identifier
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int clint_ipi_send(size_t hart_id);
|
||||
|
||||
/**
|
||||
* @brief Clear local interprocessor interrupt
|
||||
*
|
||||
* @param[in] hart_id The hart identifier
|
||||
*
|
||||
* @return result
|
||||
* - 1 An IPI was pending
|
||||
* - 0 Non IPI was pending
|
||||
* - -1 Fail
|
||||
*/
|
||||
int clint_ipi_clear(size_t hart_id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_CLINT_H */
|
||||
|
|
@ -0,0 +1,289 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_COMMON_H
|
||||
#define _DRIVER_COMMON_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
#include <cstdbool>
|
||||
#include <cstddef>
|
||||
#include <cstdint>
|
||||
#else /* __cplusplus */
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#define KENDRYTE_MIN(a, b) ((a) > (b) ? (b) : (a))
|
||||
#define KENDRYTE_MAX(a, b) ((a) > (b) ? (a) : (b))
|
||||
|
||||
#ifdef __ASSEMBLY__
|
||||
#define KENDRYTE_CAST(type, ptr) ptr
|
||||
#else /* __ASSEMBLY__ */
|
||||
/**
|
||||
* @brief Cast the pointer to specified pointer type.
|
||||
*
|
||||
* @param[in] type The pointer type to cast to
|
||||
* @param[in] ptr The pointer to apply the type cast to
|
||||
*/
|
||||
#define KENDRYTE_CAST(type, ptr) ((type)(ptr))
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/**
|
||||
* @addtogroup UTIL_RW_FUNC Memory Read/Write Utilities
|
||||
*
|
||||
* This section implements read and write functionality for various
|
||||
* memory untis. The memory unit terms used for these functions are
|
||||
* consistent with those used in the ARM Architecture Reference Manual
|
||||
* ARMv7-A and ARMv7-R edition manual. The terms used for units of memory are:
|
||||
*
|
||||
* Unit of Memory | Abbreviation | Size in Bits
|
||||
* :---------------|:-------------|:------------:
|
||||
* Byte | byte | 8
|
||||
* Half Word | hword | 16
|
||||
* Word | word | 32
|
||||
* Double Word | dword | 64
|
||||
*
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write the 8 bit byte to the destination address in device memory.
|
||||
*
|
||||
* @param[in] dest Write destination pointer address
|
||||
* @param[in] src 8 bit data byte to write to memory
|
||||
*/
|
||||
#define kendryte_write_byte(dest, src) \
|
||||
(*KENDRYTE_CAST(volatile uint8_t*, (dest)) = (src))
|
||||
|
||||
/**
|
||||
* @brief Read and return the 8 bit byte from the source address in device memory.
|
||||
*
|
||||
* @param[in] src Read source pointer address
|
||||
*
|
||||
* @return 8 bit data byte value
|
||||
*/
|
||||
#define kendryte_read_byte(src) (*KENDRYTE_CAST(volatile uint8_t*, (src)))
|
||||
|
||||
/**
|
||||
* @brief Write the 16 bit half word to the destination address in device memory.
|
||||
*
|
||||
* @param[in] dest Write destination pointer address
|
||||
* @param[in] src 16 bit data half word to write to memory
|
||||
*/
|
||||
#define kendryte_write_hword(dest, src) \
|
||||
(*KENDRYTE_CAST(volatile uint16_t*, (dest)) = (src))
|
||||
|
||||
/**
|
||||
* @brief Read and return the 16 bit half word from the source address in device
|
||||
*
|
||||
* @param[in] src Read source pointer address
|
||||
*
|
||||
* @return 16 bit data half word value
|
||||
*/
|
||||
#define kendryte_read_hword(src) (*KENDRYTE_CAST(volatile uint16_t*, (src)))
|
||||
|
||||
/**
|
||||
* @brief Write the 32 bit word to the destination address in device memory.
|
||||
*
|
||||
* @param[in] dest Write destination pointer address
|
||||
* @param[in] src 32 bit data word to write to memory
|
||||
*/
|
||||
#define kendryte_write_word(dest, src) \
|
||||
(*KENDRYTE_CAST(volatile uint32_t*, (dest)) = (src))
|
||||
|
||||
/**
|
||||
* @brief Read and return the 32 bit word from the source address in device memory.
|
||||
*
|
||||
* @param[in] src Read source pointer address
|
||||
*
|
||||
* @return 32 bit data half word value
|
||||
*/
|
||||
#define kendryte_read_word(src) (*KENDRYTE_CAST(volatile uint32_t*, (src)))
|
||||
|
||||
/**
|
||||
* @brief Write the 64 bit double word to the destination address in device memory.
|
||||
*
|
||||
* @param[in] dest Write destination pointer address
|
||||
* @param[in] src 64 bit data word to write to memory
|
||||
*/
|
||||
#define kendryte_write_dword(dest, src) \
|
||||
(*KENDRYTE_CAST(volatile uint64_t*, (dest)) = (src))
|
||||
|
||||
/**
|
||||
* @brief Read and return the 64 bit double word from the source address in device
|
||||
*
|
||||
* @param[in] src Read source pointer address
|
||||
*
|
||||
* @return 64 bit data half word value
|
||||
*/
|
||||
#define kendryte_read_dword(src) (*KENDRYTE_CAST(volatile uint64_t*, (src)))
|
||||
|
||||
/**
|
||||
* @brief Set selected bits in the 8 bit byte at the destination address in device
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to set in destination byte
|
||||
*/
|
||||
#define kendryte_setbits_byte(dest, bits) \
|
||||
(kendryte_write_byte(dest, kendryte_read_byte(dest) | (bits)))
|
||||
|
||||
/**
|
||||
* @brief Clear selected bits in the 8 bit byte at the destination address in device
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to clear in destination byte
|
||||
*/
|
||||
#define kendryte_clrbits_byte(dest, bits) \
|
||||
(kendryte_write_byte(dest, kendryte_read_byte(dest) & ~(bits)))
|
||||
|
||||
/**
|
||||
* @brief Change or toggle selected bits in the 8 bit byte at the destination address
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to change in destination byte
|
||||
*/
|
||||
#define kendryte_xorbits_byte(dest, bits) \
|
||||
(kendryte_write_byte(dest, kendryte_read_byte(dest) ^ (bits)))
|
||||
|
||||
/**
|
||||
* @brief Replace selected bits in the 8 bit byte at the destination address in device
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] msk Bits to replace in destination byte
|
||||
* @param[in] src Source bits to write to cleared bits in destination byte
|
||||
*/
|
||||
#define kendryte_replbits_byte(dest, msk, src) \
|
||||
(kendryte_write_byte(dest, (kendryte_read_byte(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
/**
|
||||
* @brief Set selected bits in the 16 bit halfword at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to set in destination halfword
|
||||
*/
|
||||
#define kendryte_setbits_hword(dest, bits) \
|
||||
(kendryte_write_hword(dest, kendryte_read_hword(dest) | (bits)))
|
||||
|
||||
/**
|
||||
* @brief Clear selected bits in the 16 bit halfword at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to clear in destination halfword
|
||||
*/
|
||||
#define kendryte_clrbits_hword(dest, bits) \
|
||||
(kendryte_write_hword(dest, kendryte_read_hword(dest) & ~(bits)))
|
||||
|
||||
/**
|
||||
* @brief Change or toggle selected bits in the 16 bit halfword at the destination
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to change in destination halfword
|
||||
*/
|
||||
#define kendryte_xorbits_hword(dest, bits) \
|
||||
(kendryte_write_hword(dest, kendryte_read_hword(dest) ^ (bits)))
|
||||
|
||||
/**
|
||||
* @brief Replace selected bits in the 16 bit halfword at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] msk Bits to replace in destination byte
|
||||
* @param[in] src Source bits to write to cleared bits in destination halfword
|
||||
*/
|
||||
#define kendryte_replbits_hword(dest, msk, src) \
|
||||
(kendryte_write_hword(dest, (kendryte_read_hword(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
/**
|
||||
* @brief Set selected bits in the 32 bit word at the destination address in device
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to set in destination word
|
||||
*/
|
||||
#define kendryte_setbits_word(dest, bits) \
|
||||
(kendryte_write_word(dest, kendryte_read_word(dest) | (bits)))
|
||||
|
||||
/**
|
||||
* @brief Clear selected bits in the 32 bit word at the destination address in device
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to clear in destination word
|
||||
*/
|
||||
#define kendryte_clrbits_word(dest, bits) \
|
||||
(kendryte_write_word(dest, kendryte_read_word(dest) & ~(bits)))
|
||||
|
||||
/**
|
||||
* @brief Change or toggle selected bits in the 32 bit word at the destination address
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to change in destination word
|
||||
*/
|
||||
#define kendryte_xorbits_word(dest, bits) \
|
||||
(kendryte_write_word(dest, kendryte_read_word(dest) ^ (bits)))
|
||||
|
||||
/**
|
||||
* @brief Replace selected bits in the 32 bit word at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] msk Bits to replace in destination word
|
||||
* @param[in] src Source bits to write to cleared bits in destination word
|
||||
*/
|
||||
#define kendryte_replbits_word(dest, msk, src) \
|
||||
(kendryte_write_word(dest, (kendryte_read_word(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
/**
|
||||
* @brief Set selected bits in the 64 bit doubleword at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to set in destination doubleword
|
||||
*/
|
||||
#define kendryte_setbits_dword(dest, bits) \
|
||||
(kendryte_write_dword(dest, kendryte_read_dword(dest) | (bits)))
|
||||
|
||||
/**
|
||||
* @brief Clear selected bits in the 64 bit doubleword at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to clear in destination doubleword
|
||||
*/
|
||||
#define kendryte_clrbits_dword(dest, bits) \
|
||||
(kendryte_write_dword(dest, kendryte_read_dword(dest) & ~(bits)))
|
||||
|
||||
/**
|
||||
* @brief Change or toggle selected bits in the 64 bit doubleword at the destination
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] bits Bits to change in destination doubleword
|
||||
*/
|
||||
#define kendryte_xorbits_dword(dest, bits) \
|
||||
(kendryte_write_dword(dest, kendryte_read_dword(dest) ^ (bits)))
|
||||
|
||||
/**
|
||||
* @brief Replace selected bits in the 64 bit doubleword at the destination address in
|
||||
*
|
||||
* @param[in] dest Destination pointer address
|
||||
* @param[in] msk its to replace in destination doubleword
|
||||
* @param[in] src Source bits to write to cleared bits in destination word
|
||||
*/
|
||||
#define kendryte_replbits_dword(dest, msk, src) \
|
||||
(kendryte_write_dword(dest, (kendryte_read_dword(dest) & ~(msk)) | ((src) & (msk))))
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
#endif /* _DRIVER_COMMON_H */
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,102 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_DVP_H
|
||||
#define _DRIVER_DVP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
/**
|
||||
* @brief DVP object
|
||||
*/
|
||||
struct dvp_t
|
||||
{
|
||||
volatile uint32_t dvp_cfg;
|
||||
volatile uint32_t r_addr;
|
||||
volatile uint32_t g_addr;
|
||||
volatile uint32_t b_addr;
|
||||
volatile uint32_t cmos_cfg;
|
||||
volatile uint32_t sccb_cfg;
|
||||
volatile uint32_t sccb_ctl;
|
||||
volatile uint32_t axi;
|
||||
volatile uint32_t sts;
|
||||
volatile uint32_t reverse;
|
||||
volatile uint32_t rgb_addr;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/* DVP Config Register */
|
||||
#define DVP_CFG_START_INT_ENABLE 0x00000001
|
||||
#define DVP_CFG_FINISH_INT_ENABLE 0x00000002
|
||||
#define DVP_CFG_AI_OUTPUT_ENABLE 0x00000004
|
||||
#define DVP_CFG_DISPLAY_OUTPUT_ENABLE 0x00000008
|
||||
#define DVP_CFG_AUTO_ENABLE 0x00000010
|
||||
#define DVP_CFG_BURST_SIZE_4BEATS 0x00000100
|
||||
#define DVP_CFG_FORMAT_MASK 0x00000600
|
||||
#define DVP_CFG_RGB_FORMAT 0x00000000
|
||||
#define DVP_CFG_YUV_FORMAT 0x00000200
|
||||
#define DVP_CFG_Y_FORMAT 0x00000600
|
||||
#define DVP_CFG_HREF_BURST_NUM_MASK 0x000FF000
|
||||
#define DVP_CFG_HREF_BURST_NUM(x) ((x) << 12)
|
||||
#define DVP_CFG_LINE_NUM_MASK 0x3FF00000
|
||||
#define DVP_CFG_LINE_NUM(x) ((x) << 20)
|
||||
|
||||
/* DVP CMOS Config Register */
|
||||
#define DVP_CMOS_CLK_DIV_MASK 0x000000FF
|
||||
#define DVP_CMOS_CLK_DIV(x) ((x) << 0)
|
||||
#define DVP_CMOS_CLK_ENABLE 0x00000100
|
||||
#define DVP_CMOS_RESET 0x00010000
|
||||
#define DVP_CMOS_POWER_DOWN 0x01000000
|
||||
|
||||
/* DVP SCCB Config Register */
|
||||
#define DVP_SCCB_BYTE_NUM_MASK 0x00000003
|
||||
#define DVP_SCCB_BYTE_NUM_2 0x00000001
|
||||
#define DVP_SCCB_BYTE_NUM_3 0x00000002
|
||||
#define DVP_SCCB_BYTE_NUM_4 0x00000003
|
||||
#define DVP_SCCB_SCL_LCNT_MASK 0x0000FF00
|
||||
#define DVP_SCCB_SCL_LCNT(x) ((x) << 8)
|
||||
#define DVP_SCCB_SCL_HCNT_MASK 0x00FF0000
|
||||
#define DVP_SCCB_SCL_HCNT(x) ((x) << 16)
|
||||
#define DVP_SCCB_RDATA_BYTE(x) ((x) >> 24)
|
||||
|
||||
/* DVP SCCB Control Register */
|
||||
#define DVP_SCCB_WRITE_ENABLE 0x00000001
|
||||
#define DVP_SCCB_DEVICE_ADDRESS(x) ((x) << 0)
|
||||
#define DVP_SCCB_REG_ADDRESS(x) ((x) << 8)
|
||||
#define DVP_SCCB_WDATA_BYTE0(x) ((x) << 16)
|
||||
#define DVP_SCCB_WDATA_BYTE1(x) ((x) << 24)
|
||||
|
||||
/* DVP AXI Register */
|
||||
#define DVP_AXI_GM_MLEN_MASK 0x000000FF
|
||||
#define DVP_AXI_GM_MLEN_1BYTE 0x00000000
|
||||
#define DVP_AXI_GM_MLEN_4BYTE 0x00000003
|
||||
|
||||
/* DVP STS Register */
|
||||
#define DVP_STS_FRAME_START 0x00000001
|
||||
#define DVP_STS_FRAME_START_WE 0x00000002
|
||||
#define DVP_STS_FRAME_FINISH 0x00000100
|
||||
#define DVP_STS_FRAME_FINISH_WE 0x00000200
|
||||
#define DVP_STS_DVP_EN 0x00010000
|
||||
#define DVP_STS_DVP_EN_WE 0x00020000
|
||||
#define DVP_STS_SCCB_EN 0x01000000
|
||||
#define DVP_STS_SCCB_EN_WE 0x02000000
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_DVP_H */
|
|
@ -0,0 +1,980 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief Field Programmable GPIO Array (FPIOA)
|
||||
*
|
||||
* The FPIOA peripheral supports the following features:
|
||||
*
|
||||
* - 48 IO with 256 functions
|
||||
*
|
||||
* - Schmitt trigger
|
||||
*
|
||||
* - Invert input and output
|
||||
*
|
||||
* - Pull up and pull down
|
||||
*
|
||||
* - Driving selector
|
||||
*
|
||||
* - Static input and output
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_FPIOA_H
|
||||
#define _DRIVER_FPIOA_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
/* Pad number settings */
|
||||
#define FPIOA_NUM_IO (48)
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief FPIOA IO functions
|
||||
*
|
||||
* @note FPIOA pin function table
|
||||
*
|
||||
* | Function | Name | Description |
|
||||
* |-----------|------------------|-----------------------------------|
|
||||
* | 0 | JTAG_TCLK | JTAG Test Clock |
|
||||
* | 1 | JTAG_TDI | JTAG Test Data In |
|
||||
* | 2 | JTAG_TMS | JTAG Test Mode Select |
|
||||
* | 3 | JTAG_TDO | JTAG Test Data Out |
|
||||
* | 4 | SPI0_D0 | SPI0 Data 0 |
|
||||
* | 5 | SPI0_D1 | SPI0 Data 1 |
|
||||
* | 6 | SPI0_D2 | SPI0 Data 2 |
|
||||
* | 7 | SPI0_D3 | SPI0 Data 3 |
|
||||
* | 8 | SPI0_D4 | SPI0 Data 4 |
|
||||
* | 9 | SPI0_D5 | SPI0 Data 5 |
|
||||
* | 10 | SPI0_D6 | SPI0 Data 6 |
|
||||
* | 11 | SPI0_D7 | SPI0 Data 7 |
|
||||
* | 12 | SPI0_SS0 | SPI0 Chip Select 0 |
|
||||
* | 13 | SPI0_SS1 | SPI0 Chip Select 1 |
|
||||
* | 14 | SPI0_SS2 | SPI0 Chip Select 2 |
|
||||
* | 15 | SPI0_SS3 | SPI0 Chip Select 3 |
|
||||
* | 16 | SPI0_ARB | SPI0 Arbitration |
|
||||
* | 17 | SPI0_SCLK | SPI0 Serial Clock |
|
||||
* | 18 | UARTHS_RX | UART High speed Receiver |
|
||||
* | 19 | UARTHS_TX | UART High speed Transmitter |
|
||||
* | 20 | CLK_IN1 | Clock Input 1 |
|
||||
* | 21 | CLK_IN2 | Clock Input 2 |
|
||||
* | 22 | CLK_SPI1 | Clock SPI1 |
|
||||
* | 23 | CLK_I2C1 | Clock I2C1 |
|
||||
* | 24 | GPIOHS0 | GPIO High speed 0 |
|
||||
* | 25 | GPIOHS1 | GPIO High speed 1 |
|
||||
* | 26 | GPIOHS2 | GPIO High speed 2 |
|
||||
* | 27 | GPIOHS3 | GPIO High speed 3 |
|
||||
* | 28 | GPIOHS4 | GPIO High speed 4 |
|
||||
* | 29 | GPIOHS5 | GPIO High speed 5 |
|
||||
* | 30 | GPIOHS6 | GPIO High speed 6 |
|
||||
* | 31 | GPIOHS7 | GPIO High speed 7 |
|
||||
* | 32 | GPIOHS8 | GPIO High speed 8 |
|
||||
* | 33 | GPIOHS9 | GPIO High speed 9 |
|
||||
* | 34 | GPIOHS10 | GPIO High speed 10 |
|
||||
* | 35 | GPIOHS11 | GPIO High speed 11 |
|
||||
* | 36 | GPIOHS12 | GPIO High speed 12 |
|
||||
* | 37 | GPIOHS13 | GPIO High speed 13 |
|
||||
* | 38 | GPIOHS14 | GPIO High speed 14 |
|
||||
* | 39 | GPIOHS15 | GPIO High speed 15 |
|
||||
* | 40 | GPIOHS16 | GPIO High speed 16 |
|
||||
* | 41 | GPIOHS17 | GPIO High speed 17 |
|
||||
* | 42 | GPIOHS18 | GPIO High speed 18 |
|
||||
* | 43 | GPIOHS19 | GPIO High speed 19 |
|
||||
* | 44 | GPIOHS20 | GPIO High speed 20 |
|
||||
* | 45 | GPIOHS21 | GPIO High speed 21 |
|
||||
* | 46 | GPIOHS22 | GPIO High speed 22 |
|
||||
* | 47 | GPIOHS23 | GPIO High speed 23 |
|
||||
* | 48 | GPIOHS24 | GPIO High speed 24 |
|
||||
* | 49 | GPIOHS25 | GPIO High speed 25 |
|
||||
* | 50 | GPIOHS26 | GPIO High speed 26 |
|
||||
* | 51 | GPIOHS27 | GPIO High speed 27 |
|
||||
* | 52 | GPIOHS28 | GPIO High speed 28 |
|
||||
* | 53 | GPIOHS29 | GPIO High speed 29 |
|
||||
* | 54 | GPIOHS30 | GPIO High speed 30 |
|
||||
* | 55 | GPIOHS31 | GPIO High speed 31 |
|
||||
* | 56 | GPIO0 | GPIO pin 0 |
|
||||
* | 57 | GPIO1 | GPIO pin 1 |
|
||||
* | 58 | GPIO2 | GPIO pin 2 |
|
||||
* | 59 | GPIO3 | GPIO pin 3 |
|
||||
* | 60 | GPIO4 | GPIO pin 4 |
|
||||
* | 61 | GPIO5 | GPIO pin 5 |
|
||||
* | 62 | GPIO6 | GPIO pin 6 |
|
||||
* | 63 | GPIO7 | GPIO pin 7 |
|
||||
* | 64 | UART1_RX | UART1 Receiver |
|
||||
* | 65 | UART1_TX | UART1 Transmitter |
|
||||
* | 66 | UART2_RX | UART2 Receiver |
|
||||
* | 67 | UART2_TX | UART2 Transmitter |
|
||||
* | 68 | UART3_RX | UART3 Receiver |
|
||||
* | 69 | UART3_TX | UART3 Transmitter |
|
||||
* | 70 | SPI1_D0 | SPI1 Data 0 |
|
||||
* | 71 | SPI1_D1 | SPI1 Data 1 |
|
||||
* | 72 | SPI1_D2 | SPI1 Data 2 |
|
||||
* | 73 | SPI1_D3 | SPI1 Data 3 |
|
||||
* | 74 | SPI1_D4 | SPI1 Data 4 |
|
||||
* | 75 | SPI1_D5 | SPI1 Data 5 |
|
||||
* | 76 | SPI1_D6 | SPI1 Data 6 |
|
||||
* | 77 | SPI1_D7 | SPI1 Data 7 |
|
||||
* | 78 | SPI1_SS0 | SPI1 Chip Select 0 |
|
||||
* | 79 | SPI1_SS1 | SPI1 Chip Select 1 |
|
||||
* | 80 | SPI1_SS2 | SPI1 Chip Select 2 |
|
||||
* | 81 | SPI1_SS3 | SPI1 Chip Select 3 |
|
||||
* | 82 | SPI1_ARB | SPI1 Arbitration |
|
||||
* | 83 | SPI1_SCLK | SPI1 Serial Clock |
|
||||
* | 84 | SPI_SLAVE_D0 | SPI Slave Data 0 |
|
||||
* | 85 | SPI_SLAVE_SS | SPI Slave Select |
|
||||
* | 86 | SPI_SLAVE_SCLK | SPI Slave Serial Clock |
|
||||
* | 87 | I2S0_MCLK | I2S0 Master Clock |
|
||||
* | 88 | I2S0_SCLK | I2S0 Serial Clock(BCLK) |
|
||||
* | 89 | I2S0_WS | I2S0 Word Select(LRCLK) |
|
||||
* | 90 | I2S0_IN_D0 | I2S0 Serial Data Input 0 |
|
||||
* | 91 | I2S0_IN_D1 | I2S0 Serial Data Input 1 |
|
||||
* | 92 | I2S0_IN_D2 | I2S0 Serial Data Input 2 |
|
||||
* | 93 | I2S0_IN_D3 | I2S0 Serial Data Input 3 |
|
||||
* | 94 | I2S0_OUT_D0 | I2S0 Serial Data Output 0 |
|
||||
* | 95 | I2S0_OUT_D1 | I2S0 Serial Data Output 1 |
|
||||
* | 96 | I2S0_OUT_D2 | I2S0 Serial Data Output 2 |
|
||||
* | 97 | I2S0_OUT_D3 | I2S0 Serial Data Output 3 |
|
||||
* | 98 | I2S1_MCLK | I2S1 Master Clock |
|
||||
* | 99 | I2S1_SCLK | I2S1 Serial Clock(BCLK) |
|
||||
* | 100 | I2S1_WS | I2S1 Word Select(LRCLK) |
|
||||
* | 101 | I2S1_IN_D0 | I2S1 Serial Data Input 0 |
|
||||
* | 102 | I2S1_IN_D1 | I2S1 Serial Data Input 1 |
|
||||
* | 103 | I2S1_IN_D2 | I2S1 Serial Data Input 2 |
|
||||
* | 104 | I2S1_IN_D3 | I2S1 Serial Data Input 3 |
|
||||
* | 105 | I2S1_OUT_D0 | I2S1 Serial Data Output 0 |
|
||||
* | 106 | I2S1_OUT_D1 | I2S1 Serial Data Output 1 |
|
||||
* | 107 | I2S1_OUT_D2 | I2S1 Serial Data Output 2 |
|
||||
* | 108 | I2S1_OUT_D3 | I2S1 Serial Data Output 3 |
|
||||
* | 109 | I2S2_MCLK | I2S2 Master Clock |
|
||||
* | 110 | I2S2_SCLK | I2S2 Serial Clock(BCLK) |
|
||||
* | 111 | I2S2_WS | I2S2 Word Select(LRCLK) |
|
||||
* | 112 | I2S2_IN_D0 | I2S2 Serial Data Input 0 |
|
||||
* | 113 | I2S2_IN_D1 | I2S2 Serial Data Input 1 |
|
||||
* | 114 | I2S2_IN_D2 | I2S2 Serial Data Input 2 |
|
||||
* | 115 | I2S2_IN_D3 | I2S2 Serial Data Input 3 |
|
||||
* | 116 | I2S2_OUT_D0 | I2S2 Serial Data Output 0 |
|
||||
* | 117 | I2S2_OUT_D1 | I2S2 Serial Data Output 1 |
|
||||
* | 118 | I2S2_OUT_D2 | I2S2 Serial Data Output 2 |
|
||||
* | 119 | I2S2_OUT_D3 | I2S2 Serial Data Output 3 |
|
||||
* | 120 | RESV0 | Reserved function |
|
||||
* | 121 | RESV1 | Reserved function |
|
||||
* | 122 | RESV2 | Reserved function |
|
||||
* | 123 | RESV3 | Reserved function |
|
||||
* | 124 | RESV4 | Reserved function |
|
||||
* | 125 | RESV5 | Reserved function |
|
||||
* | 126 | I2C0_SCLK | I2C0 Serial Clock |
|
||||
* | 127 | I2C0_SDA | I2C0 Serial Data |
|
||||
* | 128 | I2C1_SCLK | I2C1 Serial Clock |
|
||||
* | 129 | I2C1_SDA | I2C1 Serial Data |
|
||||
* | 130 | I2C2_SCLK | I2C2 Serial Clock |
|
||||
* | 131 | I2C2_SDA | I2C2 Serial Data |
|
||||
* | 132 | CMOS_XCLK | DVP System Clock |
|
||||
* | 133 | CMOS_RST | DVP System Reset |
|
||||
* | 134 | CMOS_PWND | DVP Power Down Mode |
|
||||
* | 135 | CMOS_VSYNC | DVP Vertical Sync |
|
||||
* | 136 | CMOS_HREF | DVP Horizontal Reference output |
|
||||
* | 137 | CMOS_PCLK | Pixel Clock |
|
||||
* | 138 | CMOS_D0 | Data Bit 0 |
|
||||
* | 139 | CMOS_D1 | Data Bit 1 |
|
||||
* | 140 | CMOS_D2 | Data Bit 2 |
|
||||
* | 141 | CMOS_D3 | Data Bit 3 |
|
||||
* | 142 | CMOS_D4 | Data Bit 4 |
|
||||
* | 143 | CMOS_D5 | Data Bit 5 |
|
||||
* | 144 | CMOS_D6 | Data Bit 6 |
|
||||
* | 145 | CMOS_D7 | Data Bit 7 |
|
||||
* | 146 | SCCB_SCLK | SCCB Serial Clock |
|
||||
* | 147 | SCCB_SDA | SCCB Serial Data |
|
||||
* | 148 | UART1_CTS | UART1 Clear To Send |
|
||||
* | 149 | UART1_DSR | UART1 Data Set Ready |
|
||||
* | 150 | UART1_DCD | UART1 Data Carrier Detect |
|
||||
* | 151 | UART1_RI | UART1 Ring Indicator |
|
||||
* | 152 | UART1_SIR_IN | UART1 Serial Infrared Input |
|
||||
* | 153 | UART1_DTR | UART1 Data Terminal Ready |
|
||||
* | 154 | UART1_RTS | UART1 Request To Send |
|
||||
* | 155 | UART1_OUT2 | UART1 User-designated Output 2 |
|
||||
* | 156 | UART1_OUT1 | UART1 User-designated Output 1 |
|
||||
* | 157 | UART1_SIR_OUT | UART1 Serial Infrared Output |
|
||||
* | 158 | UART1_BAUD | UART1 Transmit Clock Output |
|
||||
* | 159 | UART1_RE | UART1 Receiver Output Enable |
|
||||
* | 160 | UART1_DE | UART1 Driver Output Enable |
|
||||
* | 161 | UART1_RS485_EN | UART1 RS485 Enable |
|
||||
* | 162 | UART2_CTS | UART2 Clear To Send |
|
||||
* | 163 | UART2_DSR | UART2 Data Set Ready |
|
||||
* | 164 | UART2_DCD | UART2 Data Carrier Detect |
|
||||
* | 165 | UART2_RI | UART2 Ring Indicator |
|
||||
* | 166 | UART2_SIR_IN | UART2 Serial Infrared Input |
|
||||
* | 167 | UART2_DTR | UART2 Data Terminal Ready |
|
||||
* | 168 | UART2_RTS | UART2 Request To Send |
|
||||
* | 169 | UART2_OUT2 | UART2 User-designated Output 2 |
|
||||
* | 170 | UART2_OUT1 | UART2 User-designated Output 1 |
|
||||
* | 171 | UART2_SIR_OUT | UART2 Serial Infrared Output |
|
||||
* | 172 | UART2_BAUD | UART2 Transmit Clock Output |
|
||||
* | 173 | UART2_RE | UART2 Receiver Output Enable |
|
||||
* | 174 | UART2_DE | UART2 Driver Output Enable |
|
||||
* | 175 | UART2_RS485_EN | UART2 RS485 Enable |
|
||||
* | 176 | UART3_CTS | UART3 Clear To Send |
|
||||
* | 177 | UART3_DSR | UART3 Data Set Ready |
|
||||
* | 178 | UART3_DCD | UART3 Data Carrier Detect |
|
||||
* | 179 | UART3_RI | UART3 Ring Indicator |
|
||||
* | 180 | UART3_SIR_IN | UART3 Serial Infrared Input |
|
||||
* | 181 | UART3_DTR | UART3 Data Terminal Ready |
|
||||
* | 182 | UART3_RTS | UART3 Request To Send |
|
||||
* | 183 | UART3_OUT2 | UART3 User-designated Output 2 |
|
||||
* | 184 | UART3_OUT1 | UART3 User-designated Output 1 |
|
||||
* | 185 | UART3_SIR_OUT | UART3 Serial Infrared Output |
|
||||
* | 186 | UART3_BAUD | UART3 Transmit Clock Output |
|
||||
* | 187 | UART3_RE | UART3 Receiver Output Enable |
|
||||
* | 188 | UART3_DE | UART3 Driver Output Enable |
|
||||
* | 189 | UART3_RS485_EN | UART3 RS485 Enable |
|
||||
* | 190 | TIMER0_TOGGLE1 | TIMER0 Toggle Output 1 |
|
||||
* | 191 | TIMER0_TOGGLE2 | TIMER0 Toggle Output 2 |
|
||||
* | 192 | TIMER0_TOGGLE3 | TIMER0 Toggle Output 3 |
|
||||
* | 193 | TIMER0_TOGGLE4 | TIMER0 Toggle Output 4 |
|
||||
* | 194 | TIMER1_TOGGLE1 | TIMER1 Toggle Output 1 |
|
||||
* | 195 | TIMER1_TOGGLE2 | TIMER1 Toggle Output 2 |
|
||||
* | 196 | TIMER1_TOGGLE3 | TIMER1 Toggle Output 3 |
|
||||
* | 197 | TIMER1_TOGGLE4 | TIMER1 Toggle Output 4 |
|
||||
* | 198 | TIMER2_TOGGLE1 | TIMER2 Toggle Output 1 |
|
||||
* | 199 | TIMER2_TOGGLE2 | TIMER2 Toggle Output 2 |
|
||||
* | 200 | TIMER2_TOGGLE3 | TIMER2 Toggle Output 3 |
|
||||
* | 201 | TIMER2_TOGGLE4 | TIMER2 Toggle Output 4 |
|
||||
* | 202 | CLK_SPI2 | Clock SPI2 |
|
||||
* | 203 | CLK_I2C2 | Clock I2C2 |
|
||||
* | 222 | CONSTANT | Constant function |
|
||||
* | 224 | DEBUG0 | Debug function 0 |
|
||||
* | 225 | DEBUG1 | Debug function 1 |
|
||||
* | 226 | DEBUG2 | Debug function 2 |
|
||||
* | 227 | DEBUG3 | Debug function 3 |
|
||||
* | 228 | DEBUG4 | Debug function 4 |
|
||||
* | 229 | DEBUG5 | Debug function 5 |
|
||||
* | 230 | DEBUG6 | Debug function 6 |
|
||||
* | 231 | DEBUG7 | Debug function 7 |
|
||||
* | 232 | DEBUG8 | Debug function 8 |
|
||||
* | 233 | DEBUG9 | Debug function 9 |
|
||||
* | 234 | DEBUG10 | Debug function 10 |
|
||||
* | 235 | DEBUG11 | Debug function 11 |
|
||||
* | 236 | DEBUG12 | Debug function 12 |
|
||||
* | 237 | DEBUG13 | Debug function 13 |
|
||||
* | 238 | DEBUG14 | Debug function 14 |
|
||||
* | 239 | DEBUG15 | Debug function 15 |
|
||||
* | 240 | DEBUG16 | Debug function 16 |
|
||||
* | 241 | DEBUG17 | Debug function 17 |
|
||||
* | 242 | DEBUG18 | Debug function 18 |
|
||||
* | 243 | DEBUG19 | Debug function 19 |
|
||||
* | 244 | DEBUG20 | Debug function 20 |
|
||||
* | 245 | DEBUG21 | Debug function 21 |
|
||||
* | 246 | DEBUG22 | Debug function 22 |
|
||||
* | 247 | DEBUG23 | Debug function 23 |
|
||||
* | 248 | DEBUG24 | Debug function 24 |
|
||||
* | 249 | DEBUG25 | Debug function 25 |
|
||||
* | 250 | DEBUG26 | Debug function 26 |
|
||||
* | 251 | DEBUG27 | Debug function 27 |
|
||||
* | 252 | DEBUG28 | Debug function 28 |
|
||||
* | 253 | DEBUG29 | Debug function 29 |
|
||||
* | 254 | DEBUG30 | Debug function 30 |
|
||||
* | 255 | DEBUG31 | Debug function 31 |
|
||||
*
|
||||
* Any IO of FPIOA have 256 functions, it is a IO-function matrix.
|
||||
* All IO have default reset function, after reset, re-configure
|
||||
* IO function is required.
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
enum fpioa_function_e
|
||||
{
|
||||
FUNC_JTAG_TCLK = 0, /*!< JTAG Test Clock */
|
||||
FUNC_JTAG_TDI = 1, /*!< JTAG Test Data In */
|
||||
FUNC_JTAG_TMS = 2, /*!< JTAG Test Mode Select */
|
||||
FUNC_JTAG_TDO = 3, /*!< JTAG Test Data Out */
|
||||
FUNC_SPI0_D0 = 4, /*!< SPI0 Data 0 */
|
||||
FUNC_SPI0_D1 = 5, /*!< SPI0 Data 1 */
|
||||
FUNC_SPI0_D2 = 6, /*!< SPI0 Data 2 */
|
||||
FUNC_SPI0_D3 = 7, /*!< SPI0 Data 3 */
|
||||
FUNC_SPI0_D4 = 8, /*!< SPI0 Data 4 */
|
||||
FUNC_SPI0_D5 = 9, /*!< SPI0 Data 5 */
|
||||
FUNC_SPI0_D6 = 10, /*!< SPI0 Data 6 */
|
||||
FUNC_SPI0_D7 = 11, /*!< SPI0 Data 7 */
|
||||
FUNC_SPI0_SS0 = 12, /*!< SPI0 Chip Select 0 */
|
||||
FUNC_SPI0_SS1 = 13, /*!< SPI0 Chip Select 1 */
|
||||
FUNC_SPI0_SS2 = 14, /*!< SPI0 Chip Select 2 */
|
||||
FUNC_SPI0_SS3 = 15, /*!< SPI0 Chip Select 3 */
|
||||
FUNC_SPI0_ARB = 16, /*!< SPI0 Arbitration */
|
||||
FUNC_SPI0_SCLK = 17, /*!< SPI0 Serial Clock */
|
||||
FUNC_UARTHS_RX = 18, /*!< UART High speed Receiver */
|
||||
FUNC_UARTHS_TX = 19, /*!< UART High speed Transmitter */
|
||||
FUNC_CLK_IN1 = 20, /*!< Clock Input 1 */
|
||||
FUNC_CLK_IN2 = 21, /*!< Clock Input 2 */
|
||||
FUNC_CLK_SPI1 = 22, /*!< Clock SPI1 */
|
||||
FUNC_CLK_I2C1 = 23, /*!< Clock I2C1 */
|
||||
FUNC_GPIOHS0 = 24, /*!< GPIO High speed 0 */
|
||||
FUNC_GPIOHS1 = 25, /*!< GPIO High speed 1 */
|
||||
FUNC_GPIOHS2 = 26, /*!< GPIO High speed 2 */
|
||||
FUNC_GPIOHS3 = 27, /*!< GPIO High speed 3 */
|
||||
FUNC_GPIOHS4 = 28, /*!< GPIO High speed 4 */
|
||||
FUNC_GPIOHS5 = 29, /*!< GPIO High speed 5 */
|
||||
FUNC_GPIOHS6 = 30, /*!< GPIO High speed 6 */
|
||||
FUNC_GPIOHS7 = 31, /*!< GPIO High speed 7 */
|
||||
FUNC_GPIOHS8 = 32, /*!< GPIO High speed 8 */
|
||||
FUNC_GPIOHS9 = 33, /*!< GPIO High speed 9 */
|
||||
FUNC_GPIOHS10 = 34, /*!< GPIO High speed 10 */
|
||||
FUNC_GPIOHS11 = 35, /*!< GPIO High speed 11 */
|
||||
FUNC_GPIOHS12 = 36, /*!< GPIO High speed 12 */
|
||||
FUNC_GPIOHS13 = 37, /*!< GPIO High speed 13 */
|
||||
FUNC_GPIOHS14 = 38, /*!< GPIO High speed 14 */
|
||||
FUNC_GPIOHS15 = 39, /*!< GPIO High speed 15 */
|
||||
FUNC_GPIOHS16 = 40, /*!< GPIO High speed 16 */
|
||||
FUNC_GPIOHS17 = 41, /*!< GPIO High speed 17 */
|
||||
FUNC_GPIOHS18 = 42, /*!< GPIO High speed 18 */
|
||||
FUNC_GPIOHS19 = 43, /*!< GPIO High speed 19 */
|
||||
FUNC_GPIOHS20 = 44, /*!< GPIO High speed 20 */
|
||||
FUNC_GPIOHS21 = 45, /*!< GPIO High speed 21 */
|
||||
FUNC_GPIOHS22 = 46, /*!< GPIO High speed 22 */
|
||||
FUNC_GPIOHS23 = 47, /*!< GPIO High speed 23 */
|
||||
FUNC_GPIOHS24 = 48, /*!< GPIO High speed 24 */
|
||||
FUNC_GPIOHS25 = 49, /*!< GPIO High speed 25 */
|
||||
FUNC_GPIOHS26 = 50, /*!< GPIO High speed 26 */
|
||||
FUNC_GPIOHS27 = 51, /*!< GPIO High speed 27 */
|
||||
FUNC_GPIOHS28 = 52, /*!< GPIO High speed 28 */
|
||||
FUNC_GPIOHS29 = 53, /*!< GPIO High speed 29 */
|
||||
FUNC_GPIOHS30 = 54, /*!< GPIO High speed 30 */
|
||||
FUNC_GPIOHS31 = 55, /*!< GPIO High speed 31 */
|
||||
FUNC_GPIO0 = 56, /*!< GPIO pin 0 */
|
||||
FUNC_GPIO1 = 57, /*!< GPIO pin 1 */
|
||||
FUNC_GPIO2 = 58, /*!< GPIO pin 2 */
|
||||
FUNC_GPIO3 = 59, /*!< GPIO pin 3 */
|
||||
FUNC_GPIO4 = 60, /*!< GPIO pin 4 */
|
||||
FUNC_GPIO5 = 61, /*!< GPIO pin 5 */
|
||||
FUNC_GPIO6 = 62, /*!< GPIO pin 6 */
|
||||
FUNC_GPIO7 = 63, /*!< GPIO pin 7 */
|
||||
FUNC_UART1_RX = 64, /*!< UART1 Receiver */
|
||||
FUNC_UART1_TX = 65, /*!< UART1 Transmitter */
|
||||
FUNC_UART2_RX = 66, /*!< UART2 Receiver */
|
||||
FUNC_UART2_TX = 67, /*!< UART2 Transmitter */
|
||||
FUNC_UART3_RX = 68, /*!< UART3 Receiver */
|
||||
FUNC_UART3_TX = 69, /*!< UART3 Transmitter */
|
||||
FUNC_SPI1_D0 = 70, /*!< SPI1 Data 0 */
|
||||
FUNC_SPI1_D1 = 71, /*!< SPI1 Data 1 */
|
||||
FUNC_SPI1_D2 = 72, /*!< SPI1 Data 2 */
|
||||
FUNC_SPI1_D3 = 73, /*!< SPI1 Data 3 */
|
||||
FUNC_SPI1_D4 = 74, /*!< SPI1 Data 4 */
|
||||
FUNC_SPI1_D5 = 75, /*!< SPI1 Data 5 */
|
||||
FUNC_SPI1_D6 = 76, /*!< SPI1 Data 6 */
|
||||
FUNC_SPI1_D7 = 77, /*!< SPI1 Data 7 */
|
||||
FUNC_SPI1_SS0 = 78, /*!< SPI1 Chip Select 0 */
|
||||
FUNC_SPI1_SS1 = 79, /*!< SPI1 Chip Select 1 */
|
||||
FUNC_SPI1_SS2 = 80, /*!< SPI1 Chip Select 2 */
|
||||
FUNC_SPI1_SS3 = 81, /*!< SPI1 Chip Select 3 */
|
||||
FUNC_SPI1_ARB = 82, /*!< SPI1 Arbitration */
|
||||
FUNC_SPI1_SCLK = 83, /*!< SPI1 Serial Clock */
|
||||
FUNC_SPI_SLAVE_D0 = 84, /*!< SPI Slave Data 0 */
|
||||
FUNC_SPI_SLAVE_SS = 85, /*!< SPI Slave Select */
|
||||
FUNC_SPI_SLAVE_SCLK = 86, /*!< SPI Slave Serial Clock */
|
||||
FUNC_I2S0_MCLK = 87, /*!< I2S0 Master Clock */
|
||||
FUNC_I2S0_SCLK = 88, /*!< I2S0 Serial Clock(BCLK) */
|
||||
FUNC_I2S0_WS = 89, /*!< I2S0 Word Select(LRCLK) */
|
||||
FUNC_I2S0_IN_D0 = 90, /*!< I2S0 Serial Data Input 0 */
|
||||
FUNC_I2S0_IN_D1 = 91, /*!< I2S0 Serial Data Input 1 */
|
||||
FUNC_I2S0_IN_D2 = 92, /*!< I2S0 Serial Data Input 2 */
|
||||
FUNC_I2S0_IN_D3 = 93, /*!< I2S0 Serial Data Input 3 */
|
||||
FUNC_I2S0_OUT_D0 = 94, /*!< I2S0 Serial Data Output 0 */
|
||||
FUNC_I2S0_OUT_D1 = 95, /*!< I2S0 Serial Data Output 1 */
|
||||
FUNC_I2S0_OUT_D2 = 96, /*!< I2S0 Serial Data Output 2 */
|
||||
FUNC_I2S0_OUT_D3 = 97, /*!< I2S0 Serial Data Output 3 */
|
||||
FUNC_I2S1_MCLK = 98, /*!< I2S1 Master Clock */
|
||||
FUNC_I2S1_SCLK = 99, /*!< I2S1 Serial Clock(BCLK) */
|
||||
FUNC_I2S1_WS = 100, /*!< I2S1 Word Select(LRCLK) */
|
||||
FUNC_I2S1_IN_D0 = 101, /*!< I2S1 Serial Data Input 0 */
|
||||
FUNC_I2S1_IN_D1 = 102, /*!< I2S1 Serial Data Input 1 */
|
||||
FUNC_I2S1_IN_D2 = 103, /*!< I2S1 Serial Data Input 2 */
|
||||
FUNC_I2S1_IN_D3 = 104, /*!< I2S1 Serial Data Input 3 */
|
||||
FUNC_I2S1_OUT_D0 = 105, /*!< I2S1 Serial Data Output 0 */
|
||||
FUNC_I2S1_OUT_D1 = 106, /*!< I2S1 Serial Data Output 1 */
|
||||
FUNC_I2S1_OUT_D2 = 107, /*!< I2S1 Serial Data Output 2 */
|
||||
FUNC_I2S1_OUT_D3 = 108, /*!< I2S1 Serial Data Output 3 */
|
||||
FUNC_I2S2_MCLK = 109, /*!< I2S2 Master Clock */
|
||||
FUNC_I2S2_SCLK = 110, /*!< I2S2 Serial Clock(BCLK) */
|
||||
FUNC_I2S2_WS = 111, /*!< I2S2 Word Select(LRCLK) */
|
||||
FUNC_I2S2_IN_D0 = 112, /*!< I2S2 Serial Data Input 0 */
|
||||
FUNC_I2S2_IN_D1 = 113, /*!< I2S2 Serial Data Input 1 */
|
||||
FUNC_I2S2_IN_D2 = 114, /*!< I2S2 Serial Data Input 2 */
|
||||
FUNC_I2S2_IN_D3 = 115, /*!< I2S2 Serial Data Input 3 */
|
||||
FUNC_I2S2_OUT_D0 = 116, /*!< I2S2 Serial Data Output 0 */
|
||||
FUNC_I2S2_OUT_D1 = 117, /*!< I2S2 Serial Data Output 1 */
|
||||
FUNC_I2S2_OUT_D2 = 118, /*!< I2S2 Serial Data Output 2 */
|
||||
FUNC_I2S2_OUT_D3 = 119, /*!< I2S2 Serial Data Output 3 */
|
||||
FUNC_RESV0 = 120, /*!< Reserved function */
|
||||
FUNC_RESV1 = 121, /*!< Reserved function */
|
||||
FUNC_RESV2 = 122, /*!< Reserved function */
|
||||
FUNC_RESV3 = 123, /*!< Reserved function */
|
||||
FUNC_RESV4 = 124, /*!< Reserved function */
|
||||
FUNC_RESV5 = 125, /*!< Reserved function */
|
||||
FUNC_I2C0_SCLK = 126, /*!< I2C0 Serial Clock */
|
||||
FUNC_I2C0_SDA = 127, /*!< I2C0 Serial Data */
|
||||
FUNC_I2C1_SCLK = 128, /*!< I2C1 Serial Clock */
|
||||
FUNC_I2C1_SDA = 129, /*!< I2C1 Serial Data */
|
||||
FUNC_I2C2_SCLK = 130, /*!< I2C2 Serial Clock */
|
||||
FUNC_I2C2_SDA = 131, /*!< I2C2 Serial Data */
|
||||
FUNC_CMOS_XCLK = 132, /*!< DVP System Clock */
|
||||
FUNC_CMOS_RST = 133, /*!< DVP System Reset */
|
||||
FUNC_CMOS_PWND = 134, /*!< DVP Power Down Mode */
|
||||
FUNC_CMOS_VSYNC = 135, /*!< DVP Vertical Sync */
|
||||
FUNC_CMOS_HREF = 136, /*!< DVP Horizontal Reference output */
|
||||
FUNC_CMOS_PCLK = 137, /*!< Pixel Clock */
|
||||
FUNC_CMOS_D0 = 138, /*!< Data Bit 0 */
|
||||
FUNC_CMOS_D1 = 139, /*!< Data Bit 1 */
|
||||
FUNC_CMOS_D2 = 140, /*!< Data Bit 2 */
|
||||
FUNC_CMOS_D3 = 141, /*!< Data Bit 3 */
|
||||
FUNC_CMOS_D4 = 142, /*!< Data Bit 4 */
|
||||
FUNC_CMOS_D5 = 143, /*!< Data Bit 5 */
|
||||
FUNC_CMOS_D6 = 144, /*!< Data Bit 6 */
|
||||
FUNC_CMOS_D7 = 145, /*!< Data Bit 7 */
|
||||
FUNC_SCCB_SCLK = 146, /*!< SCCB Serial Clock */
|
||||
FUNC_SCCB_SDA = 147, /*!< SCCB Serial Data */
|
||||
FUNC_UART1_CTS = 148, /*!< UART1 Clear To Send */
|
||||
FUNC_UART1_DSR = 149, /*!< UART1 Data Set Ready */
|
||||
FUNC_UART1_DCD = 150, /*!< UART1 Data Carrier Detect */
|
||||
FUNC_UART1_RI = 151, /*!< UART1 Ring Indicator */
|
||||
FUNC_UART1_SIR_IN = 152, /*!< UART1 Serial Infrared Input */
|
||||
FUNC_UART1_DTR = 153, /*!< UART1 Data Terminal Ready */
|
||||
FUNC_UART1_RTS = 154, /*!< UART1 Request To Send */
|
||||
FUNC_UART1_OUT2 = 155, /*!< UART1 User-designated Output 2 */
|
||||
FUNC_UART1_OUT1 = 156, /*!< UART1 User-designated Output 1 */
|
||||
FUNC_UART1_SIR_OUT = 157, /*!< UART1 Serial Infrared Output */
|
||||
FUNC_UART1_BAUD = 158, /*!< UART1 Transmit Clock Output */
|
||||
FUNC_UART1_RE = 159, /*!< UART1 Receiver Output Enable */
|
||||
FUNC_UART1_DE = 160, /*!< UART1 Driver Output Enable */
|
||||
FUNC_UART1_RS485_EN = 161, /*!< UART1 RS485 Enable */
|
||||
FUNC_UART2_CTS = 162, /*!< UART2 Clear To Send */
|
||||
FUNC_UART2_DSR = 163, /*!< UART2 Data Set Ready */
|
||||
FUNC_UART2_DCD = 164, /*!< UART2 Data Carrier Detect */
|
||||
FUNC_UART2_RI = 165, /*!< UART2 Ring Indicator */
|
||||
FUNC_UART2_SIR_IN = 166, /*!< UART2 Serial Infrared Input */
|
||||
FUNC_UART2_DTR = 167, /*!< UART2 Data Terminal Ready */
|
||||
FUNC_UART2_RTS = 168, /*!< UART2 Request To Send */
|
||||
FUNC_UART2_OUT2 = 169, /*!< UART2 User-designated Output 2 */
|
||||
FUNC_UART2_OUT1 = 170, /*!< UART2 User-designated Output 1 */
|
||||
FUNC_UART2_SIR_OUT = 171, /*!< UART2 Serial Infrared Output */
|
||||
FUNC_UART2_BAUD = 172, /*!< UART2 Transmit Clock Output */
|
||||
FUNC_UART2_RE = 173, /*!< UART2 Receiver Output Enable */
|
||||
FUNC_UART2_DE = 174, /*!< UART2 Driver Output Enable */
|
||||
FUNC_UART2_RS485_EN = 175, /*!< UART2 RS485 Enable */
|
||||
FUNC_UART3_CTS = 176, /*!< UART3 Clear To Send */
|
||||
FUNC_UART3_DSR = 177, /*!< UART3 Data Set Ready */
|
||||
FUNC_UART3_DCD = 178, /*!< UART3 Data Carrier Detect */
|
||||
FUNC_UART3_RI = 179, /*!< UART3 Ring Indicator */
|
||||
FUNC_UART3_SIR_IN = 180, /*!< UART3 Serial Infrared Input */
|
||||
FUNC_UART3_DTR = 181, /*!< UART3 Data Terminal Ready */
|
||||
FUNC_UART3_RTS = 182, /*!< UART3 Request To Send */
|
||||
FUNC_UART3_OUT2 = 183, /*!< UART3 User-designated Output 2 */
|
||||
FUNC_UART3_OUT1 = 184, /*!< UART3 User-designated Output 1 */
|
||||
FUNC_UART3_SIR_OUT = 185, /*!< UART3 Serial Infrared Output */
|
||||
FUNC_UART3_BAUD = 186, /*!< UART3 Transmit Clock Output */
|
||||
FUNC_UART3_RE = 187, /*!< UART3 Receiver Output Enable */
|
||||
FUNC_UART3_DE = 188, /*!< UART3 Driver Output Enable */
|
||||
FUNC_UART3_RS485_EN = 189, /*!< UART3 RS485 Enable */
|
||||
FUNC_TIMER0_TOGGLE1 = 190, /*!< TIMER0 Toggle Output 1 */
|
||||
FUNC_TIMER0_TOGGLE2 = 191, /*!< TIMER0 Toggle Output 2 */
|
||||
FUNC_TIMER0_TOGGLE3 = 192, /*!< TIMER0 Toggle Output 3 */
|
||||
FUNC_TIMER0_TOGGLE4 = 193, /*!< TIMER0 Toggle Output 4 */
|
||||
FUNC_TIMER1_TOGGLE1 = 194, /*!< TIMER1 Toggle Output 1 */
|
||||
FUNC_TIMER1_TOGGLE2 = 195, /*!< TIMER1 Toggle Output 2 */
|
||||
FUNC_TIMER1_TOGGLE3 = 196, /*!< TIMER1 Toggle Output 3 */
|
||||
FUNC_TIMER1_TOGGLE4 = 197, /*!< TIMER1 Toggle Output 4 */
|
||||
FUNC_TIMER2_TOGGLE1 = 198, /*!< TIMER2 Toggle Output 1 */
|
||||
FUNC_TIMER2_TOGGLE2 = 199, /*!< TIMER2 Toggle Output 2 */
|
||||
FUNC_TIMER2_TOGGLE3 = 200, /*!< TIMER2 Toggle Output 3 */
|
||||
FUNC_TIMER2_TOGGLE4 = 201, /*!< TIMER2 Toggle Output 4 */
|
||||
FUNC_CLK_SPI2 = 202, /*!< Clock SPI2 */
|
||||
FUNC_CLK_I2C2 = 203, /*!< Clock I2C2 */
|
||||
FUNC_INTERNAL0 = 204, /*!< Internal function signal 0 */
|
||||
FUNC_INTERNAL1 = 205, /*!< Internal function signal 1 */
|
||||
FUNC_INTERNAL2 = 206, /*!< Internal function signal 2 */
|
||||
FUNC_INTERNAL3 = 207, /*!< Internal function signal 3 */
|
||||
FUNC_INTERNAL4 = 208, /*!< Internal function signal 4 */
|
||||
FUNC_INTERNAL5 = 209, /*!< Internal function signal 5 */
|
||||
FUNC_INTERNAL6 = 210, /*!< Internal function signal 6 */
|
||||
FUNC_INTERNAL7 = 211, /*!< Internal function signal 7 */
|
||||
FUNC_INTERNAL8 = 212, /*!< Internal function signal 8 */
|
||||
FUNC_INTERNAL9 = 213, /*!< Internal function signal 9 */
|
||||
FUNC_INTERNAL10 = 214, /*!< Internal function signal 10 */
|
||||
FUNC_INTERNAL11 = 215, /*!< Internal function signal 11 */
|
||||
FUNC_INTERNAL12 = 216, /*!< Internal function signal 12 */
|
||||
FUNC_INTERNAL13 = 219, /*!< Internal function signal 13 */
|
||||
FUNC_INTERNAL14 = 220, /*!< Internal function signal 14 */
|
||||
FUNC_INTERNAL15 = 221, /*!< Internal function signal 15 */
|
||||
FUNC_CONSTANT = 222, /*!< Constant function */
|
||||
FUNC_INTERNAL16 = 223, /*!< Internal function signal 16 */
|
||||
FUNC_DEBUG0 = 224, /*!< Debug function 0 */
|
||||
FUNC_DEBUG1 = 225, /*!< Debug function 1 */
|
||||
FUNC_DEBUG2 = 226, /*!< Debug function 2 */
|
||||
FUNC_DEBUG3 = 227, /*!< Debug function 3 */
|
||||
FUNC_DEBUG4 = 228, /*!< Debug function 4 */
|
||||
FUNC_DEBUG5 = 229, /*!< Debug function 5 */
|
||||
FUNC_DEBUG6 = 230, /*!< Debug function 6 */
|
||||
FUNC_DEBUG7 = 231, /*!< Debug function 7 */
|
||||
FUNC_DEBUG8 = 232, /*!< Debug function 8 */
|
||||
FUNC_DEBUG9 = 233, /*!< Debug function 9 */
|
||||
FUNC_DEBUG10 = 234, /*!< Debug function 10 */
|
||||
FUNC_DEBUG11 = 235, /*!< Debug function 11 */
|
||||
FUNC_DEBUG12 = 236, /*!< Debug function 12 */
|
||||
FUNC_DEBUG13 = 237, /*!< Debug function 13 */
|
||||
FUNC_DEBUG14 = 238, /*!< Debug function 14 */
|
||||
FUNC_DEBUG15 = 239, /*!< Debug function 15 */
|
||||
FUNC_DEBUG16 = 240, /*!< Debug function 16 */
|
||||
FUNC_DEBUG17 = 241, /*!< Debug function 17 */
|
||||
FUNC_DEBUG18 = 242, /*!< Debug function 18 */
|
||||
FUNC_DEBUG19 = 243, /*!< Debug function 19 */
|
||||
FUNC_DEBUG20 = 244, /*!< Debug function 20 */
|
||||
FUNC_DEBUG21 = 245, /*!< Debug function 21 */
|
||||
FUNC_DEBUG22 = 246, /*!< Debug function 22 */
|
||||
FUNC_DEBUG23 = 247, /*!< Debug function 23 */
|
||||
FUNC_DEBUG24 = 248, /*!< Debug function 24 */
|
||||
FUNC_DEBUG25 = 249, /*!< Debug function 25 */
|
||||
FUNC_DEBUG26 = 250, /*!< Debug function 26 */
|
||||
FUNC_DEBUG27 = 251, /*!< Debug function 27 */
|
||||
FUNC_DEBUG28 = 252, /*!< Debug function 28 */
|
||||
FUNC_DEBUG29 = 253, /*!< Debug function 29 */
|
||||
FUNC_DEBUG30 = 254, /*!< Debug function 30 */
|
||||
FUNC_DEBUG31 = 255, /*!< Debug function 31 */
|
||||
FUNC_MAX = 256, /*!< Function numbers */
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief FPIOA pull settings
|
||||
*
|
||||
* @note FPIOA pull settings description
|
||||
*
|
||||
* | PU | PD | Description |
|
||||
* |-----|-----|-----------------------------------|
|
||||
* | 0 | 0 | No Pull |
|
||||
* | 0 | 1 | Pull Down |
|
||||
* | 1 | 0 | Pull Up |
|
||||
* | 1 | 1 | Undefined |
|
||||
*
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
enum fpioa_pull_e
|
||||
{
|
||||
FPIOA_PULL_NONE, /*!< No Pull */
|
||||
FPIOA_PULL_DOWN, /*!< Pull Down */
|
||||
FPIOA_PULL_UP, /*!< Pull Up */
|
||||
FPIOA_PULL_MAX /*!< Count of pull settings */
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief FPIOA driving settings
|
||||
*
|
||||
* @note FPIOA driving settings description
|
||||
* There are 16 kinds of driving settings
|
||||
*
|
||||
* @note Low Level Output Current
|
||||
*
|
||||
* |DS[3:0] |Min(mA)|Typ(mA)|Max(mA)|
|
||||
* |--------|-------|-------|-------|
|
||||
* |0000 |3.2 |5.4 |8.3 |
|
||||
* |0001 |4.7 |8.0 |12.3 |
|
||||
* |0010 |6.3 |10.7 |16.4 |
|
||||
* |0011 |7.8 |13.2 |20.2 |
|
||||
* |0100 |9.4 |15.9 |24.2 |
|
||||
* |0101 |10.9 |18.4 |28.1 |
|
||||
* |0110 |12.4 |20.9 |31.8 |
|
||||
* |0111 |13.9 |23.4 |35.5 |
|
||||
*
|
||||
* @note High Level Output Current
|
||||
*
|
||||
* |DS[3:0] |Min(mA)|Typ(mA)|Max(mA)|
|
||||
* |--------|-------|-------|-------|
|
||||
* |0000 |5.0 |7.6 |11.2 |
|
||||
* |0001 |7.5 |11.4 |16.8 |
|
||||
* |0010 |10.0 |15.2 |22.3 |
|
||||
* |0011 |12.4 |18.9 |27.8 |
|
||||
* |0100 |14.9 |22.6 |33.3 |
|
||||
* |0101 |17.4 |26.3 |38.7 |
|
||||
* |0110 |19.8 |30.0 |44.1 |
|
||||
* |0111 |22.3 |33.7 |49.5 |
|
||||
*
|
||||
*/
|
||||
|
||||
/* clang-format off */
|
||||
enum fpioa_driving_e
|
||||
{
|
||||
FPIOA_DRIVING_0, /*!< 0000 */
|
||||
FPIOA_DRIVING_1, /*!< 0001 */
|
||||
FPIOA_DRIVING_2, /*!< 0010 */
|
||||
FPIOA_DRIVING_3, /*!< 0011 */
|
||||
FPIOA_DRIVING_4, /*!< 0100 */
|
||||
FPIOA_DRIVING_5, /*!< 0101 */
|
||||
FPIOA_DRIVING_6, /*!< 0110 */
|
||||
FPIOA_DRIVING_7, /*!< 0111 */
|
||||
FPIOA_DRIVING_8, /*!< 1000 */
|
||||
FPIOA_DRIVING_9, /*!< 1001 */
|
||||
FPIOA_DRIVING_10, /*!< 1010 */
|
||||
FPIOA_DRIVING_11, /*!< 1011 */
|
||||
FPIOA_DRIVING_12, /*!< 1100 */
|
||||
FPIOA_DRIVING_13, /*!< 1101 */
|
||||
FPIOA_DRIVING_14, /*!< 1110 */
|
||||
FPIOA_DRIVING_15, /*!< 1111 */
|
||||
FPIOA_DRIVING_MAX /*!< Count of driving settings */
|
||||
};
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief FPIOA IO
|
||||
*
|
||||
* FPIOA IO is the specific pin of the chip package. Every IO
|
||||
* has a 32bit width register that can independently implement
|
||||
* schmitt trigger, invert input, invert output, strong pull
|
||||
* up, driving selector, static input and static output. And more,
|
||||
* it can implement any pin of any peripheral devices.
|
||||
*
|
||||
* @note FPIOA IO's register bits Layout
|
||||
*
|
||||
* | Bits | Name |Description |
|
||||
* |-----------|----------|---------------------------------------------------|
|
||||
* | 31 | PAD_DI | Read current IO's data input. |
|
||||
* | 30:24 | NA | Reserved bits. |
|
||||
* | 23 | ST | Schmitt trigger. |
|
||||
* | 22 | DI_INV | Invert Data input. |
|
||||
* | 21 | IE_INV | Invert the input enable signal. |
|
||||
* | 20 | IE_EN | Input enable. It can disable or enable IO input. |
|
||||
* | 19 | SL | Slew rate control enable. |
|
||||
* | 18 | SPU | Strong pull up. |
|
||||
* | 17 | PD | Pull select: 0 for pull down, 1 for pull up. |
|
||||
* | 16 | PU | Pull enable. |
|
||||
* | 15 | DO_INV | Invert the result of data output select (DO_SEL). |
|
||||
* | 14 | DO_SEL | Data output select: 0 for DO, 1 for OE. |
|
||||
* | 13 | OE_INV | Invert the output enable signal. |
|
||||
* | 12 | OE_EN | Output enable.It can disable or enable IO output. |
|
||||
* | 11:8 | DS | Driving selector. |
|
||||
* | 7:0 | CH_SEL | Channel select from 256 input. |
|
||||
*
|
||||
*/
|
||||
struct fpioa_io_config_t
|
||||
{
|
||||
uint32_t ch_sel : 8;
|
||||
/*!< Channel select from 256 input. */
|
||||
uint32_t ds : 4;
|
||||
/*!< Driving selector. */
|
||||
uint32_t oe_en : 1;
|
||||
/*!< Static output enable, will AND with OE_INV. */
|
||||
uint32_t oe_inv : 1;
|
||||
/*!< Invert output enable. */
|
||||
uint32_t do_sel : 1;
|
||||
/*!< Data output select: 0 for DO, 1 for OE. */
|
||||
uint32_t do_inv : 1;
|
||||
/*!< Invert the result of data output select (DO_SEL). */
|
||||
uint32_t pu : 1;
|
||||
/*!< Pull up enable. 0 for nothing, 1 for pull up. */
|
||||
uint32_t pd : 1;
|
||||
/*!< Pull down enable. 0 for nothing, 1 for pull down. */
|
||||
uint32_t resv0 : 1;
|
||||
/*!< Reserved bits. */
|
||||
uint32_t sl : 1;
|
||||
/*!< Slew rate control enable. */
|
||||
uint32_t ie_en : 1;
|
||||
/*!< Static input enable, will AND with IE_INV. */
|
||||
uint32_t ie_inv : 1;
|
||||
/*!< Invert input enable. */
|
||||
uint32_t di_inv : 1;
|
||||
/*!< Invert Data input. */
|
||||
uint32_t st : 1;
|
||||
/*!< Schmitt trigger. */
|
||||
uint32_t resv1 : 7;
|
||||
/*!< Reserved bits. */
|
||||
uint32_t pad_di : 1;
|
||||
/*!< Read current IO's data input. */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief FPIOA tie setting
|
||||
*
|
||||
* FPIOA Object have 48 IO pin object and 256 bit input tie bits.
|
||||
* All SPI arbitration signal will tie high by default.
|
||||
*
|
||||
* @note FPIOA function tie bits RAM Layout
|
||||
*
|
||||
* | Address | Name |Description |
|
||||
* |-----------|------------------|----------------------------------|
|
||||
* | 0x000 | TIE_EN[31:0] | Input tie enable bits [31:0] |
|
||||
* | 0x004 | TIE_EN[63:32] | Input tie enable bits [63:32] |
|
||||
* | 0x008 | TIE_EN[95:64] | Input tie enable bits [95:64] |
|
||||
* | 0x00C | TIE_EN[127:96] | Input tie enable bits [127:96] |
|
||||
* | 0x010 | TIE_EN[159:128] | Input tie enable bits [159:128] |
|
||||
* | 0x014 | TIE_EN[191:160] | Input tie enable bits [191:160] |
|
||||
* | 0x018 | TIE_EN[223:192] | Input tie enable bits [223:192] |
|
||||
* | 0x01C | TIE_EN[255:224] | Input tie enable bits [255:224] |
|
||||
* | 0x020 | TIE_VAL[31:0] | Input tie value bits [31:0] |
|
||||
* | 0x024 | TIE_VAL[63:32] | Input tie value bits [63:32] |
|
||||
* | 0x028 | TIE_VAL[95:64] | Input tie value bits [95:64] |
|
||||
* | 0x02C | TIE_VAL[127:96] | Input tie value bits [127:96] |
|
||||
* | 0x030 | TIE_VAL[159:128] | Input tie value bits [159:128] |
|
||||
* | 0x034 | TIE_VAL[191:160] | Input tie value bits [191:160] |
|
||||
* | 0x038 | TIE_VAL[223:192] | Input tie value bits [223:192] |
|
||||
* | 0x03C | TIE_VAL[255:224] | Input tie value bits [255:224] |
|
||||
*
|
||||
* @note Function which input tie high by default
|
||||
*
|
||||
* | Name |Description |
|
||||
* |---------------|---------------------------------------|
|
||||
* | SPI0_ARB | Arbitration function of SPI master 0 |
|
||||
* | SPI1_ARB | Arbitration function of SPI master 1 |
|
||||
*
|
||||
* Tie high means the SPI Arbitration input is 1
|
||||
*
|
||||
*/
|
||||
struct fpioa_tie_t
|
||||
{
|
||||
uint32_t en[FUNC_MAX / 32];
|
||||
/*!< FPIOA GPIO multiplexer tie enable array */
|
||||
uint32_t val[FUNC_MAX / 32];
|
||||
/*!< FPIOA GPIO multiplexer tie value array */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief FPIOA Object
|
||||
*
|
||||
* FPIOA Object have 48 IO pin object and 256 bit input tie bits.
|
||||
* All SPI arbitration signal will tie high by default.
|
||||
*
|
||||
* @note FPIOA IO Pin RAM Layout
|
||||
*
|
||||
* | Address | Name |Description |
|
||||
* |-----------|----------|--------------------------------|
|
||||
* | 0x000 | PAD0 | FPIOA GPIO multiplexer io 0 |
|
||||
* | 0x004 | PAD1 | FPIOA GPIO multiplexer io 1 |
|
||||
* | 0x008 | PAD2 | FPIOA GPIO multiplexer io 2 |
|
||||
* | 0x00C | PAD3 | FPIOA GPIO multiplexer io 3 |
|
||||
* | 0x010 | PAD4 | FPIOA GPIO multiplexer io 4 |
|
||||
* | 0x014 | PAD5 | FPIOA GPIO multiplexer io 5 |
|
||||
* | 0x018 | PAD6 | FPIOA GPIO multiplexer io 6 |
|
||||
* | 0x01C | PAD7 | FPIOA GPIO multiplexer io 7 |
|
||||
* | 0x020 | PAD8 | FPIOA GPIO multiplexer io 8 |
|
||||
* | 0x024 | PAD9 | FPIOA GPIO multiplexer io 9 |
|
||||
* | 0x028 | PAD10 | FPIOA GPIO multiplexer io 10 |
|
||||
* | 0x02C | PAD11 | FPIOA GPIO multiplexer io 11 |
|
||||
* | 0x030 | PAD12 | FPIOA GPIO multiplexer io 12 |
|
||||
* | 0x034 | PAD13 | FPIOA GPIO multiplexer io 13 |
|
||||
* | 0x038 | PAD14 | FPIOA GPIO multiplexer io 14 |
|
||||
* | 0x03C | PAD15 | FPIOA GPIO multiplexer io 15 |
|
||||
* | 0x040 | PAD16 | FPIOA GPIO multiplexer io 16 |
|
||||
* | 0x044 | PAD17 | FPIOA GPIO multiplexer io 17 |
|
||||
* | 0x048 | PAD18 | FPIOA GPIO multiplexer io 18 |
|
||||
* | 0x04C | PAD19 | FPIOA GPIO multiplexer io 19 |
|
||||
* | 0x050 | PAD20 | FPIOA GPIO multiplexer io 20 |
|
||||
* | 0x054 | PAD21 | FPIOA GPIO multiplexer io 21 |
|
||||
* | 0x058 | PAD22 | FPIOA GPIO multiplexer io 22 |
|
||||
* | 0x05C | PAD23 | FPIOA GPIO multiplexer io 23 |
|
||||
* | 0x060 | PAD24 | FPIOA GPIO multiplexer io 24 |
|
||||
* | 0x064 | PAD25 | FPIOA GPIO multiplexer io 25 |
|
||||
* | 0x068 | PAD26 | FPIOA GPIO multiplexer io 26 |
|
||||
* | 0x06C | PAD27 | FPIOA GPIO multiplexer io 27 |
|
||||
* | 0x070 | PAD28 | FPIOA GPIO multiplexer io 28 |
|
||||
* | 0x074 | PAD29 | FPIOA GPIO multiplexer io 29 |
|
||||
* | 0x078 | PAD30 | FPIOA GPIO multiplexer io 30 |
|
||||
* | 0x07C | PAD31 | FPIOA GPIO multiplexer io 31 |
|
||||
* | 0x080 | PAD32 | FPIOA GPIO multiplexer io 32 |
|
||||
* | 0x084 | PAD33 | FPIOA GPIO multiplexer io 33 |
|
||||
* | 0x088 | PAD34 | FPIOA GPIO multiplexer io 34 |
|
||||
* | 0x08C | PAD35 | FPIOA GPIO multiplexer io 35 |
|
||||
* | 0x090 | PAD36 | FPIOA GPIO multiplexer io 36 |
|
||||
* | 0x094 | PAD37 | FPIOA GPIO multiplexer io 37 |
|
||||
* | 0x098 | PAD38 | FPIOA GPIO multiplexer io 38 |
|
||||
* | 0x09C | PAD39 | FPIOA GPIO multiplexer io 39 |
|
||||
* | 0x0A0 | PAD40 | FPIOA GPIO multiplexer io 40 |
|
||||
* | 0x0A4 | PAD41 | FPIOA GPIO multiplexer io 41 |
|
||||
* | 0x0A8 | PAD42 | FPIOA GPIO multiplexer io 42 |
|
||||
* | 0x0AC | PAD43 | FPIOA GPIO multiplexer io 43 |
|
||||
* | 0x0B0 | PAD44 | FPIOA GPIO multiplexer io 44 |
|
||||
* | 0x0B4 | PAD45 | FPIOA GPIO multiplexer io 45 |
|
||||
* | 0x0B8 | PAD46 | FPIOA GPIO multiplexer io 46 |
|
||||
* | 0x0BC | PAD47 | FPIOA GPIO multiplexer io 47 |
|
||||
*
|
||||
*/
|
||||
struct fpioa_t
|
||||
{
|
||||
struct fpioa_io_config_t io[FPIOA_NUM_IO];
|
||||
/*!< FPIOA GPIO multiplexer io array */
|
||||
struct fpioa_tie_t tie;
|
||||
/*!< FPIOA GPIO multiplexer tie */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief FPIOA object instanse
|
||||
*/
|
||||
extern volatile struct fpioa_t *const fpioa;
|
||||
|
||||
/**
|
||||
* @brief Initialize FPIOA user custom default settings
|
||||
*
|
||||
* @note This function will set all FPIOA pad registers to user-defined
|
||||
* values from kconfig
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_init(void);
|
||||
|
||||
/**
|
||||
* @brief Get IO configuration
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
* @param cfg Pointer to struct of IO configuration for specified IO
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_get_io(int number, struct fpioa_io_config_t *cfg);
|
||||
|
||||
/**
|
||||
* @brief Set IO configuration
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
* @param[in] cfg Pointer to struct of IO configuration for specified IO
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_io(int number, struct fpioa_io_config_t *cfg);
|
||||
|
||||
/**
|
||||
* @brief Set IO configuration with function number
|
||||
*
|
||||
* @note The default IO configuration which bind to function number will
|
||||
* set automatically
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
* @param[in] function The function enum number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_function_raw(int number, enum fpioa_function_e function);
|
||||
|
||||
/**
|
||||
* @brief Set only IO configuration with function number
|
||||
*
|
||||
* @note The default IO configuration which bind to function number will
|
||||
* set automatically
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
* @param[in] function The function enum number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_function(int number, enum fpioa_function_e function);
|
||||
|
||||
/**
|
||||
* @brief Set tie enable to function
|
||||
*
|
||||
* @param[in] function The function enum number
|
||||
* @param[in] enable Tie enable to set, 1 is enable, 0 is disable
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_tie_enable(enum fpioa_function_e function, int enable);
|
||||
|
||||
/**
|
||||
* @brief Set tie value to function
|
||||
*
|
||||
* @param[in] function The function enum number
|
||||
* @param[in] value Tie value to set, 1 is HIGH, 0 is LOW
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_tie_value(enum fpioa_function_e function, int value);
|
||||
|
||||
/**
|
||||
* @brief Set IO pull function
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
* @param[in] pull The pull enum number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_io_pull(int number, enum fpioa_pull_e pull);
|
||||
|
||||
/**
|
||||
* @brief Get IO pull function
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
*
|
||||
* @return result
|
||||
* - -1 Fail
|
||||
* - Other The pull enum number
|
||||
*/
|
||||
int fpioa_get_io_pull(int number);
|
||||
|
||||
/**
|
||||
* @brief Set IO driving
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
* @param[in] driving The driving enum number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int fpioa_set_io_driving(int number, enum fpioa_driving_e driving);
|
||||
|
||||
/**
|
||||
* @brief Get IO driving
|
||||
*
|
||||
* @param[in] number The IO number
|
||||
*
|
||||
* @return result
|
||||
* - -1 Fail
|
||||
* - Other The driving enum number
|
||||
*/
|
||||
int fpioa_get_io_driving(int number);
|
||||
|
||||
/**
|
||||
* @brief Get IO by function
|
||||
*
|
||||
* @param[in] function The function enum number
|
||||
*
|
||||
* @return result
|
||||
* - -1 Fail
|
||||
* - Other The IO number
|
||||
*/
|
||||
int fpioa_get_io_by_func(enum fpioa_function_e function);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_FPIOA_H */
|
||||
|
|
@ -0,0 +1,127 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_GPIO_H
|
||||
#define _DRIVER_GPIO_H
|
||||
|
||||
#include "platform.h"
|
||||
#include <inttypes.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Structure for accessing GPIO registers by individual bit
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t b0 : 1;
|
||||
uint32_t b1 : 1;
|
||||
uint32_t b2 : 1;
|
||||
uint32_t b3 : 1;
|
||||
uint32_t b4 : 1;
|
||||
uint32_t b5 : 1;
|
||||
uint32_t b6 : 1;
|
||||
uint32_t b7 : 1;
|
||||
uint32_t b8 : 1;
|
||||
uint32_t b9 : 1;
|
||||
uint32_t b10 : 1;
|
||||
uint32_t b11 : 1;
|
||||
uint32_t b12 : 1;
|
||||
uint32_t b13 : 1;
|
||||
uint32_t b14 : 1;
|
||||
uint32_t b15 : 1;
|
||||
uint32_t b16 : 1;
|
||||
uint32_t b17 : 1;
|
||||
uint32_t b18 : 1;
|
||||
uint32_t b19 : 1;
|
||||
uint32_t b20 : 1;
|
||||
uint32_t b21 : 1;
|
||||
uint32_t b22 : 1;
|
||||
uint32_t b23 : 1;
|
||||
uint32_t b24 : 1;
|
||||
uint32_t b25 : 1;
|
||||
uint32_t b26 : 1;
|
||||
uint32_t b27 : 1;
|
||||
uint32_t b28 : 1;
|
||||
uint32_t b29 : 1;
|
||||
uint32_t b30 : 1;
|
||||
uint32_t b31 : 1;
|
||||
} __attribute__((packed, aligned(4))) gpio_bits_t;
|
||||
|
||||
/**
|
||||
* @brief Structure of templates for accessing GPIO registers
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
/* 32x1 bit mode */
|
||||
uint32_t u32[1];
|
||||
/* 16x2 bit mode */
|
||||
uint16_t u16[2];
|
||||
/* 8x4 bit mode */
|
||||
uint8_t u8[4];
|
||||
/* 1 bit mode */
|
||||
gpio_bits_t bits;
|
||||
} __attribute__((packed, aligned(4))) gpio_access_tp_t;
|
||||
|
||||
/**
|
||||
* @brief The GPIO address map
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* Offset 0x00: Data (output) registers */
|
||||
gpio_access_tp_t data_output;
|
||||
/* Offset 0x04: Data direction registers */
|
||||
gpio_access_tp_t direction;
|
||||
/* Offset 0x08: Data source registers */
|
||||
gpio_access_tp_t source;
|
||||
/* Offset 0x10 - 0x2f: Unused registers, 9x4 bytes */
|
||||
uint32_t unused_0[9];
|
||||
/* Offset 0x30: Interrupt enable/disable registers */
|
||||
gpio_access_tp_t interrupt_enable;
|
||||
/* Offset 0x34: Interrupt mask registers */
|
||||
gpio_access_tp_t interrupt_mask;
|
||||
/* Offset 0x38: Interrupt level registers */
|
||||
gpio_access_tp_t interrupt_level;
|
||||
/* Offset 0x3c: Interrupt polarity registers */
|
||||
gpio_access_tp_t interrupt_polarity;
|
||||
/* Offset 0x40: Interrupt status registers */
|
||||
gpio_access_tp_t interrupt_status;
|
||||
/* Offset 0x44: Raw interrupt status registers */
|
||||
gpio_access_tp_t interrupt_status_raw;
|
||||
/* Offset 0x48: Interrupt debounce registers */
|
||||
gpio_access_tp_t interrupt_debounce;
|
||||
/* Offset 0x4c: Registers for clearing interrupts */
|
||||
gpio_access_tp_t interrupt_clear;
|
||||
/* Offset 0x50: External port (data input) registers */
|
||||
gpio_access_tp_t data_input;
|
||||
/* Offset 0x54 - 0x5f: Unused registers, 3x4 bytes */
|
||||
uint32_t unused_1[3];
|
||||
/* Offset 0x60: Sync level registers */
|
||||
gpio_access_tp_t sync_level;
|
||||
/* Offset 0x64: ID code */
|
||||
gpio_access_tp_t id_code;
|
||||
/* Offset 0x68: Interrupt both edge type */
|
||||
gpio_access_tp_t interrupt_bothedge;
|
||||
|
||||
} __attribute__((packed, aligned(4))) gpio_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_GPIO_H */
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_GPIOHS_H
|
||||
#define _DRIVER_GPIOHS_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
#include <stddef.h>
|
||||
#include "plic.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
/* Register address offsets */
|
||||
#define GPIOHS_INPUT_VAL (0x00)
|
||||
#define GPIOHS_INPUT_EN (0x04)
|
||||
#define GPIOHS_OUTPUT_EN (0x08)
|
||||
#define GPIOHS_OUTPUT_VAL (0x0C)
|
||||
#define GPIOHS_PULLUP_EN (0x10)
|
||||
#define GPIOHS_DRIVE (0x14)
|
||||
#define GPIOHS_RISE_IE (0x18)
|
||||
#define GPIOHS_RISE_IP (0x1C)
|
||||
#define GPIOHS_FALL_IE (0x20)
|
||||
#define GPIOHS_FALL_IP (0x24)
|
||||
#define GPIOHS_HIGH_IE (0x28)
|
||||
#define GPIOHS_HIGH_IP (0x2C)
|
||||
#define GPIOHS_LOW_IE (0x30)
|
||||
#define GPIOHS_LOW_IP (0x34)
|
||||
#define GPIOHS_IOF_EN (0x38)
|
||||
#define GPIOHS_IOF_SEL (0x3C)
|
||||
#define GPIOHS_OUTPUT_XOR (0x40)
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief GPIO bits raw object
|
||||
*/
|
||||
struct gpiohs_raw_t
|
||||
{
|
||||
/* Address offset 0x00 */
|
||||
uint32_t input_val;
|
||||
/* Address offset 0x04 */
|
||||
uint32_t input_en;
|
||||
/* Address offset 0x08 */
|
||||
uint32_t output_en;
|
||||
/* Address offset 0x0c */
|
||||
uint32_t output_val;
|
||||
/* Address offset 0x10 */
|
||||
uint32_t pullup_en;
|
||||
/* Address offset 0x14 */
|
||||
uint32_t drive;
|
||||
/* Address offset 0x18 */
|
||||
uint32_t rise_ie;
|
||||
/* Address offset 0x1c */
|
||||
uint32_t rise_ip;
|
||||
/* Address offset 0x20 */
|
||||
uint32_t fall_ie;
|
||||
/* Address offset 0x24 */
|
||||
uint32_t fall_ip;
|
||||
/* Address offset 0x28 */
|
||||
uint32_t high_ie;
|
||||
/* Address offset 0x2c */
|
||||
uint32_t high_ip;
|
||||
/* Address offset 0x30 */
|
||||
uint32_t low_ie;
|
||||
/* Address offset 0x34 */
|
||||
uint32_t low_ip;
|
||||
/* Address offset 0x38 */
|
||||
uint32_t iof_en;
|
||||
/* Address offset 0x3c */
|
||||
uint32_t iof_sel;
|
||||
/* Address offset 0x40 */
|
||||
uint32_t output_xor;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief GPIO bits object
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t b0 : 1;
|
||||
uint32_t b1 : 1;
|
||||
uint32_t b2 : 1;
|
||||
uint32_t b3 : 1;
|
||||
uint32_t b4 : 1;
|
||||
uint32_t b5 : 1;
|
||||
uint32_t b6 : 1;
|
||||
uint32_t b7 : 1;
|
||||
uint32_t b8 : 1;
|
||||
uint32_t b9 : 1;
|
||||
uint32_t b10 : 1;
|
||||
uint32_t b11 : 1;
|
||||
uint32_t b12 : 1;
|
||||
uint32_t b13 : 1;
|
||||
uint32_t b14 : 1;
|
||||
uint32_t b15 : 1;
|
||||
uint32_t b16 : 1;
|
||||
uint32_t b17 : 1;
|
||||
uint32_t b18 : 1;
|
||||
uint32_t b19 : 1;
|
||||
uint32_t b20 : 1;
|
||||
uint32_t b21 : 1;
|
||||
uint32_t b22 : 1;
|
||||
uint32_t b23 : 1;
|
||||
uint32_t b24 : 1;
|
||||
uint32_t b25 : 1;
|
||||
uint32_t b26 : 1;
|
||||
uint32_t b27 : 1;
|
||||
uint32_t b28 : 1;
|
||||
uint32_t b29 : 1;
|
||||
uint32_t b30 : 1;
|
||||
uint32_t b31 : 1;
|
||||
} __attribute__((packed, aligned(4))) gpiohs_bits_t;
|
||||
|
||||
/**
|
||||
* @brief GPIO bits multi access union
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
/* 32x1 bit mode */
|
||||
uint32_t u32[1];
|
||||
/* 16x2 bit mode */
|
||||
uint16_t u16[2];
|
||||
/* 8x4 bit mode */
|
||||
uint8_t u8[4];
|
||||
/* 1 bit mode */
|
||||
gpiohs_bits_t bits;
|
||||
} __attribute__((packed, aligned(4))) gpiohs_u32_t;
|
||||
|
||||
/**
|
||||
* @brief GPIO object
|
||||
*
|
||||
* The GPIO controller is a peripheral device mapped in the
|
||||
* internal memory map, discoverable in the Configuration String.
|
||||
* It is responsible for low-level configuration of the actual
|
||||
* GPIO pads on the device (direction, pull up-enable, and drive
|
||||
* value), as well as selecting between various sources of the
|
||||
* controls for these signals. The GPIO controller allows seperate
|
||||
* configuration of each of N GPIO bits.
|
||||
*
|
||||
* Once the interrupt is pending, it will remain set until a 1 is
|
||||
* written to the *_ip register at that bit.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/* Address offset 0x00, Input Values */
|
||||
gpiohs_u32_t input_val;
|
||||
/* Address offset 0x04, Input enable */
|
||||
gpiohs_u32_t input_en;
|
||||
/* Address offset 0x08, Output enable */
|
||||
gpiohs_u32_t output_en;
|
||||
/* Address offset 0x0c, Onput Values */
|
||||
gpiohs_u32_t output_val;
|
||||
/* Address offset 0x10, Internal Pull-Ups enable */
|
||||
gpiohs_u32_t pullup_en;
|
||||
/* Address offset 0x14, Drive Strength */
|
||||
gpiohs_u32_t drive;
|
||||
/* Address offset 0x18, Rise interrupt enable */
|
||||
gpiohs_u32_t rise_ie;
|
||||
/* Address offset 0x1c, Rise interrupt pending */
|
||||
gpiohs_u32_t rise_ip;
|
||||
/* Address offset 0x20, Fall interrupt enable */
|
||||
gpiohs_u32_t fall_ie;
|
||||
/* Address offset 0x24, Fall interrupt pending */
|
||||
gpiohs_u32_t fall_ip;
|
||||
/* Address offset 0x28, High interrupt enable */
|
||||
gpiohs_u32_t high_ie;
|
||||
/* Address offset 0x2c, High interrupt pending */
|
||||
gpiohs_u32_t high_ip;
|
||||
/* Address offset 0x30, Low interrupt enable */
|
||||
gpiohs_u32_t low_ie;
|
||||
/* Address offset 0x34, Low interrupt pending */
|
||||
gpiohs_u32_t low_ip;
|
||||
/* Address offset 0x38, HW I/O Function enable */
|
||||
gpiohs_u32_t iof_en;
|
||||
/* Address offset 0x3c, HW I/O Function select */
|
||||
gpiohs_u32_t iof_sel;
|
||||
/* Address offset 0x40, Output XOR (invert) */
|
||||
gpiohs_u32_t output_xor;
|
||||
} __attribute__((packed, aligned(4))) gpiohs_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_GPIOHS_H */
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_HARD_FFT_H
|
||||
#define _DRIVER_HARD_FFT_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief FFT algorithm accelerator register
|
||||
*
|
||||
* @note FFT algorithm accelerator register table
|
||||
*
|
||||
* | Offset | Name | Description |
|
||||
* |-----------|----------------|-------------------------------------|
|
||||
* | 0x00 | fft_input_fifo | input data fifo |
|
||||
* | 0x08 | fft_ctrl | fft ctrl reg |
|
||||
* | 0x10 | fifo_ctrl | fifo ctrl |
|
||||
* | 0x18 | intr_mask | interrupt mask |
|
||||
* | 0x20 | intr_clear | interrupt clear |
|
||||
* | 0x28 | fft_status | fft status reg |
|
||||
* | 0x30 | fft_status_raw | fft_status_raw |
|
||||
* | 0x38 | fft_output_fifo| fft_output_fifo |
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief input data fifo
|
||||
*
|
||||
* No. 0 Register (0x00)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_input_fifo : 64;
|
||||
} __attribute__((packed, aligned(8))) fft_fft_input_fifo_t;
|
||||
|
||||
/**
|
||||
* @brief fft ctrl reg
|
||||
*
|
||||
* No. 1 Register (0x08)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_point : 3;
|
||||
uint64_t fft_mode : 1;
|
||||
uint64_t fft_shift : 9;
|
||||
uint64_t fft_enable : 1;
|
||||
uint64_t dma_send : 1;
|
||||
uint64_t fft_input_mode : 2;
|
||||
uint64_t fft_data_mode : 1;
|
||||
uint64_t reserved : 46;
|
||||
} __attribute__((packed, aligned(8))) fft_fft_ctrl_t;
|
||||
|
||||
/**
|
||||
* @brief fifo ctrl
|
||||
*
|
||||
* No. 2 Register (0x10)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t resp_fifo_flush_n : 1;
|
||||
uint64_t cmd_fifo_flush_n : 1;
|
||||
uint64_t gs_fifo_flush_n : 1;
|
||||
uint64_t reserved : 61;
|
||||
} __attribute__((packed, aligned(8))) fft_fifo_ctrl_t;
|
||||
|
||||
/**
|
||||
* @brief interrupt mask
|
||||
*
|
||||
* No. 3 Register (0x18)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_done_mask : 1;
|
||||
uint64_t reserved : 63;
|
||||
} __attribute__((packed, aligned(8))) fft_intr_mask_t;
|
||||
|
||||
/**
|
||||
* @brief interrupt clear
|
||||
*
|
||||
* No. 4 Register (0x20)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_done_clear : 1;
|
||||
uint64_t reserved1 : 63;
|
||||
} __attribute__((packed, aligned(8))) fft_intr_clear_t;
|
||||
|
||||
/**
|
||||
* @brief fft status reg
|
||||
*
|
||||
* No. 5 Register (0x28)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_done_status : 1;
|
||||
uint64_t reserved1 : 63;
|
||||
} __attribute__((packed, aligned(8))) fft_fft_status_t;
|
||||
|
||||
/**
|
||||
* @brief fft_status_raw
|
||||
*
|
||||
* No. 6 Register (0x30)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_done_status_raw : 1;
|
||||
uint64_t reserved : 63;
|
||||
} __attribute__((packed, aligned(8))) fft_fft_status_raw_t;
|
||||
|
||||
/**
|
||||
* @brief fft_output_fifo
|
||||
*
|
||||
* No. 7 Register (0x38)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint64_t fft_output_fifo : 64;
|
||||
} __attribute__((packed, aligned(8))) fft_fft_output_fifo_t;
|
||||
|
||||
/**
|
||||
* @brief Fast Fourier transform (FFT) algorithm accelerator object
|
||||
*
|
||||
* A fast Fourier transform (FFT) algorithm computes the discrete
|
||||
* Fourier transform (DFT) of a sequence, or its inverse (IFFT).
|
||||
* Fourier analysis converts a signal from its original domain
|
||||
* (often time or space) to a representation in the frequency
|
||||
* domain and vice versa. An FFT rapidly computes such
|
||||
* transformations by factorizing the DFT matrix into a product of
|
||||
* sparse (mostly zero) factors.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/* No. 0 (0x00): input data fifo */
|
||||
fft_fft_input_fifo_t fft_input_fifo;
|
||||
/* No. 1 (0x08): fft ctrl reg */
|
||||
fft_fft_ctrl_t fft_ctrl;
|
||||
/* No. 2 (0x10): fifo ctrl */
|
||||
fft_fifo_ctrl_t fifo_ctrl;
|
||||
/* No. 3 (0x18): interrupt mask */
|
||||
fft_intr_mask_t intr_mask;
|
||||
/* No. 4 (0x20): interrupt clear */
|
||||
fft_intr_clear_t intr_clear;
|
||||
/* No. 5 (0x28): fft status reg */
|
||||
fft_fft_status_t fft_status;
|
||||
/* No. 6 (0x30): fft_status_raw */
|
||||
fft_fft_status_raw_t fft_status_raw;
|
||||
/* No. 7 (0x38): fft_output_fifo */
|
||||
fft_fft_output_fifo_t fft_output_fifo;
|
||||
} __attribute__((packed, aligned(8))) fft_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_FFT_H */
|
||||
|
|
@ -0,0 +1,330 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_I2C_H
|
||||
#define _DRIVER_I2C_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "dmac.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define I2C_MAX_NUM 3
|
||||
|
||||
/* clang-format off */
|
||||
struct i2c_t
|
||||
{
|
||||
/* I2C Control Register (0x00) */
|
||||
volatile uint32_t con;
|
||||
/* I2C Target Address Register (0x04) */
|
||||
volatile uint32_t tar;
|
||||
/* I2C Slave Address Register (0x08) */
|
||||
volatile uint32_t sar;
|
||||
/* reserved (0x0c) */
|
||||
volatile uint32_t resv1;
|
||||
/* I2C Data Buffer and Command Register (0x10) */
|
||||
volatile uint32_t data_cmd;
|
||||
/* I2C Standard Speed Clock SCL High Count Register (0x14) */
|
||||
volatile uint32_t ss_scl_hcnt;
|
||||
/* I2C Standard Speed Clock SCL Low Count Register (0x18) */
|
||||
volatile uint32_t ss_scl_lcnt;
|
||||
/* reserverd (0x1c-0x28) */
|
||||
volatile uint32_t resv2[4];
|
||||
/* I2C Interrupt Status Register (0x2c) */
|
||||
volatile uint32_t intr_stat;
|
||||
/* I2C Interrupt Mask Register (0x30) */
|
||||
volatile uint32_t intr_mask;
|
||||
/* I2C Raw Interrupt Status Register (0x34) */
|
||||
volatile uint32_t raw_intr_stat;
|
||||
/* I2C Receive FIFO Threshold Register (0x38) */
|
||||
volatile uint32_t rx_tl;
|
||||
/* I2C Transmit FIFO Threshold Register (0x3c) */
|
||||
volatile uint32_t tx_tl;
|
||||
/* I2C Clear Combined and Individual Interrupt Register (0x40) */
|
||||
volatile uint32_t clr_intr;
|
||||
/* I2C Clear RX_UNDER Interrupt Register (0x44) */
|
||||
volatile uint32_t clr_rx_under;
|
||||
/* I2C Clear RX_OVER Interrupt Register (0x48) */
|
||||
volatile uint32_t clr_rx_over;
|
||||
/* I2C Clear TX_OVER Interrupt Register (0x4c) */
|
||||
volatile uint32_t clr_tx_over;
|
||||
/* I2C Clear RD_REQ Interrupt Register (0x50) */
|
||||
volatile uint32_t clr_rd_req;
|
||||
/* I2C Clear TX_ABRT Interrupt Register (0x54) */
|
||||
volatile uint32_t clr_tx_abrt;
|
||||
/* I2C Clear RX_DONE Interrupt Register (0x58) */
|
||||
volatile uint32_t clr_rx_done;
|
||||
/* I2C Clear ACTIVITY Interrupt Register (0x5c) */
|
||||
volatile uint32_t clr_activity;
|
||||
/* I2C Clear STOP_DET Interrupt Register (0x60) */
|
||||
volatile uint32_t clr_stop_det;
|
||||
/* I2C Clear START_DET Interrupt Register (0x64) */
|
||||
volatile uint32_t clr_start_det;
|
||||
/* I2C Clear GEN_CALL Interrupt Register (0x68) */
|
||||
volatile uint32_t clr_gen_call;
|
||||
/* I2C Enable Register (0x6c) */
|
||||
volatile uint32_t enable;
|
||||
/* I2C Status Register (0x70) */
|
||||
volatile uint32_t status;
|
||||
/* I2C Transmit FIFO Level Register (0x74) */
|
||||
volatile uint32_t txflr;
|
||||
/* I2C Receive FIFO Level Register (0x78) */
|
||||
volatile uint32_t rxflr;
|
||||
/* I2C SDA Hold Time Length Register (0x7c) */
|
||||
volatile uint32_t sda_hold;
|
||||
/* I2C Transmit Abort Source Register (0x80) */
|
||||
volatile uint32_t tx_abrt_source;
|
||||
/* reserved (0x84) */
|
||||
volatile uint32_t resv3;
|
||||
/* I2C DMA Control Register (0x88) */
|
||||
volatile uint32_t dma_cr;
|
||||
/* I2C DMA Transmit Data Level Register (0x8c) */
|
||||
volatile uint32_t dma_tdlr;
|
||||
/* I2C DMA Receive Data Level Register (0x90) */
|
||||
volatile uint32_t dma_rdlr;
|
||||
/* I2C SDA Setup Register (0x94) */
|
||||
volatile uint32_t sda_setup;
|
||||
/* I2C ACK General Call Register (0x98) */
|
||||
volatile uint32_t general_call;
|
||||
/* I2C Enable Status Register (0x9c) */
|
||||
volatile uint32_t enable_status;
|
||||
/* I2C SS, FS or FM+ spike suppression limit (0xa0) */
|
||||
volatile uint32_t fs_spklen;
|
||||
/* reserved (0xa4-0xf0) */
|
||||
volatile uint32_t resv4[20];
|
||||
/* I2C Component Parameter Register 1 (0xf4) */
|
||||
volatile uint32_t comp_param_1;
|
||||
/* I2C Component Version Register (0xf8) */
|
||||
volatile uint32_t comp_version;
|
||||
/* I2C Component Type Register (0xfc) */
|
||||
volatile uint32_t comp_type;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/* I2C Control Register*/
|
||||
#define I2C_CON_MASTER_MODE 0x00000001U
|
||||
#define I2C_CON_SPEED_MASK 0x00000006U
|
||||
#define I2C_CON_SPEED(x) ((x) << 1)
|
||||
#define I2C_CON_10BITADDR_SLAVE 0x00000008U
|
||||
#define I2C_CON_RESTART_EN 0x00000020U
|
||||
#define I2C_CON_SLAVE_DISABLE 0x00000040U
|
||||
#define I2C_CON_STOP_DET_IFADDRESSED 0x00000080U
|
||||
#define I2C_CON_TX_EMPTY_CTRL 0x00000100U
|
||||
|
||||
/* I2C Target Address Register*/
|
||||
#define I2C_TAR_ADDRESS_MASK 0x000003FFU
|
||||
#define I2C_TAR_ADDRESS(x) ((x) << 0)
|
||||
#define I2C_TAR_GC_OR_START 0x00000400U
|
||||
#define I2C_TAR_SPECIAL 0x00000800U
|
||||
#define I2C_TAR_10BITADDR_MASTER 0x00001000U
|
||||
|
||||
/* I2C Slave Address Register*/
|
||||
#define I2C_SAR_ADDRESS_MASK 0x000003FFU
|
||||
#define I2C_SAR_ADDRESS(x) ((x) << 0)
|
||||
|
||||
/* I2C Rx/Tx Data Buffer and Command Register*/
|
||||
#define I2C_DATA_CMD_CMD 0x00000100U
|
||||
#define I2C_DATA_CMD_DATA_MASK 0x000000FFU
|
||||
#define I2C_DATA_CMD_DATA(x) ((x) << 0)
|
||||
|
||||
/* Standard Speed I2C Clock SCL High Count Register*/
|
||||
#define I2C_SS_SCL_HCNT_COUNT_MASK 0x0000FFFFU
|
||||
#define I2C_SS_SCL_HCNT_COUNT(x) ((x) << 0)
|
||||
|
||||
/* Standard Speed I2C Clock SCL Low Count Register*/
|
||||
#define I2C_SS_SCL_LCNT_COUNT_MASK 0x0000FFFFU
|
||||
#define I2C_SS_SCL_LCNT_COUNT(x) ((x) << 0)
|
||||
|
||||
/* I2C Interrupt Status Register*/
|
||||
#define I2C_INTR_STAT_RX_UNDER 0x00000001U
|
||||
#define I2C_INTR_STAT_RX_OVER 0x00000002U
|
||||
#define I2C_INTR_STAT_RX_FULL 0x00000004U
|
||||
#define I2C_INTR_STAT_TX_OVER 0x00000008U
|
||||
#define I2C_INTR_STAT_TX_EMPTY 0x00000010U
|
||||
#define I2C_INTR_STAT_RD_REQ 0x00000020U
|
||||
#define I2C_INTR_STAT_TX_ABRT 0x00000040U
|
||||
#define I2C_INTR_STAT_RX_DONE 0x00000080U
|
||||
#define I2C_INTR_STAT_ACTIVITY 0x00000100U
|
||||
#define I2C_INTR_STAT_STOP_DET 0x00000200U
|
||||
#define I2C_INTR_STAT_START_DET 0x00000400U
|
||||
#define I2C_INTR_STAT_GEN_CALL 0x00000800U
|
||||
|
||||
/* I2C Interrupt Mask Register*/
|
||||
#define I2C_INTR_MASK_RX_UNDER 0x00000001U
|
||||
#define I2C_INTR_MASK_RX_OVER 0x00000002U
|
||||
#define I2C_INTR_MASK_RX_FULL 0x00000004U
|
||||
#define I2C_INTR_MASK_TX_OVER 0x00000008U
|
||||
#define I2C_INTR_MASK_TX_EMPTY 0x00000010U
|
||||
#define I2C_INTR_MASK_RD_REQ 0x00000020U
|
||||
#define I2C_INTR_MASK_TX_ABRT 0x00000040U
|
||||
#define I2C_INTR_MASK_RX_DONE 0x00000080U
|
||||
#define I2C_INTR_MASK_ACTIVITY 0x00000100U
|
||||
#define I2C_INTR_MASK_STOP_DET 0x00000200U
|
||||
#define I2C_INTR_MASK_START_DET 0x00000400U
|
||||
#define I2C_INTR_MASK_GEN_CALL 0x00000800U
|
||||
|
||||
/* I2C Raw Interrupt Status Register*/
|
||||
#define I2C_RAW_INTR_MASK_RX_UNDER 0x00000001U
|
||||
#define I2C_RAW_INTR_MASK_RX_OVER 0x00000002U
|
||||
#define I2C_RAW_INTR_MASK_RX_FULL 0x00000004U
|
||||
#define I2C_RAW_INTR_MASK_TX_OVER 0x00000008U
|
||||
#define I2C_RAW_INTR_MASK_TX_EMPTY 0x00000010U
|
||||
#define I2C_RAW_INTR_MASK_RD_REQ 0x00000020U
|
||||
#define I2C_RAW_INTR_MASK_TX_ABRT 0x00000040U
|
||||
#define I2C_RAW_INTR_MASK_RX_DONE 0x00000080U
|
||||
#define I2C_RAW_INTR_MASK_ACTIVITY 0x00000100U
|
||||
#define I2C_RAW_INTR_MASK_STOP_DET 0x00000200U
|
||||
#define I2C_RAW_INTR_MASK_START_DET 0x00000400U
|
||||
#define I2C_RAW_INTR_MASK_GEN_CALL 0x00000800U
|
||||
|
||||
/* I2C Receive FIFO Threshold Register*/
|
||||
#define I2C_RX_TL_VALUE_MASK 0x00000007U
|
||||
#define I2C_RX_TL_VALUE(x) ((x) << 0)
|
||||
|
||||
/* I2C Transmit FIFO Threshold Register*/
|
||||
#define I2C_TX_TL_VALUE_MASK 0x00000007U
|
||||
#define I2C_TX_TL_VALUE(x) ((x) << 0)
|
||||
|
||||
/* Clear Combined and Individual Interrupt Register*/
|
||||
#define I2C_CLR_INTR_CLR 0x00000001U
|
||||
|
||||
/* Clear RX_UNDER Interrupt Register*/
|
||||
#define I2C_CLR_RX_UNDER_CLR 0x00000001U
|
||||
|
||||
/* Clear RX_OVER Interrupt Register*/
|
||||
#define I2C_CLR_RX_OVER_CLR 0x00000001U
|
||||
|
||||
/* Clear TX_OVER Interrupt Register*/
|
||||
#define I2C_CLR_TX_OVER_CLR 0x00000001U
|
||||
|
||||
/* Clear RD_REQ Interrupt Register*/
|
||||
#define I2C_CLR_RD_REQ_CLR 0x00000001U
|
||||
|
||||
/* Clear TX_ABRT Interrupt Register*/
|
||||
#define I2C_CLR_TX_ABRT_CLR 0x00000001U
|
||||
|
||||
/* Clear RX_DONE Interrupt Register*/
|
||||
#define I2C_CLR_RX_DONE_CLR 0x00000001U
|
||||
|
||||
/* Clear ACTIVITY Interrupt Register*/
|
||||
#define I2C_CLR_ACTIVITY_CLR 0x00000001U
|
||||
|
||||
/* Clear STOP_DET Interrupt Register*/
|
||||
#define I2C_CLR_STOP_DET_CLR 0x00000001U
|
||||
|
||||
/* Clear START_DET Interrupt Register*/
|
||||
#define I2C_CLR_START_DET_CLR 0x00000001U
|
||||
|
||||
/* Clear GEN_CALL Interrupt Register*/
|
||||
#define I2C_CLR_GEN_CALL_CLR 0x00000001U
|
||||
|
||||
/* I2C Enable Register*/
|
||||
#define I2C_ENABLE_ENABLE 0x00000001U
|
||||
#define I2C_ENABLE_ABORT 0x00000002U
|
||||
#define I2C_ENABLE_TX_CMD_BLOCK 0x00000004U
|
||||
|
||||
/* I2C Status Register*/
|
||||
#define I2C_STATUS_ACTIVITY 0x00000001U
|
||||
#define I2C_STATUS_TFNF 0x00000002U
|
||||
#define I2C_STATUS_TFE 0x00000004U
|
||||
#define I2C_STATUS_RFNE 0x00000008U
|
||||
#define I2C_STATUS_RFF 0x00000010U
|
||||
#define I2C_STATUS_MST_ACTIVITY 0x00000020U
|
||||
#define I2C_STATUS_SLV_ACTIVITY 0x00000040U
|
||||
|
||||
/* I2C Transmit FIFO Level Register*/
|
||||
#define I2C_TXFLR_VALUE_MASK 0x00000007U
|
||||
#define I2C_TXFLR_VALUE(x) ((x) << 0)
|
||||
|
||||
/* I2C Receive FIFO Level Register*/
|
||||
#define I2C_RXFLR_VALUE_MASK 0x00000007U
|
||||
#define I2C_RXFLR_VALUE(x) ((x) << 0)
|
||||
|
||||
/* I2C SDA Hold Time Length Register*/
|
||||
#define I2C_SDA_HOLD_TX_MASK 0x0000FFFFU
|
||||
#define I2C_SDA_HOLD_TX(x) ((x) << 0)
|
||||
#define I2C_SDA_HOLD_RX_MASK 0x00FF0000U
|
||||
#define I2C_SDA_HOLD_RX(x) ((x) << 16)
|
||||
|
||||
/* I2C Transmit Abort Source Register*/
|
||||
#define I2C_TX_ABRT_SOURCE_7B_ADDR_NOACK 0x00000001U
|
||||
#define I2C_TX_ABRT_SOURCE_10B_ADDR1_NOACK 0x00000002U
|
||||
#define I2C_TX_ABRT_SOURCE_10B_ADDR2_NOACK 0x00000004U
|
||||
#define I2C_TX_ABRT_SOURCE_TXDATA_NOACK 0x00000008U
|
||||
#define I2C_TX_ABRT_SOURCE_GCALL_NOACK 0x00000010U
|
||||
#define I2C_TX_ABRT_SOURCE_GCALL_READ 0x00000020U
|
||||
#define I2C_TX_ABRT_SOURCE_HS_ACKDET 0x00000040U
|
||||
#define I2C_TX_ABRT_SOURCE_SBYTE_ACKDET 0x00000080U
|
||||
#define I2C_TX_ABRT_SOURCE_HS_NORSTRT 0x00000100U
|
||||
#define I2C_TX_ABRT_SOURCE_SBYTE_NORSTRT 0x00000200U
|
||||
#define I2C_TX_ABRT_SOURCE_10B_RD_NORSTRT 0x00000400U
|
||||
#define I2C_TX_ABRT_SOURCE_MASTER_DIS 0x00000800U
|
||||
#define I2C_TX_ABRT_SOURCE_MST_ARBLOST 0x00001000U
|
||||
#define I2C_TX_ABRT_SOURCE_SLVFLUSH_TXFIFO 0x00002000U
|
||||
#define I2C_TX_ABRT_SOURCE_SLV_ARBLOST 0x00004000U
|
||||
#define I2C_TX_ABRT_SOURCE_SLVRD_INTX 0x00008000U
|
||||
#define I2C_TX_ABRT_SOURCE_USER_ABRT 0x00010000U
|
||||
|
||||
/* DMA Control Register*/
|
||||
#define I2C_DMA_CR_RDMAE 0x00000001U
|
||||
#define I2C_DMA_CR_TDMAE 0x00000002U
|
||||
|
||||
/* DMA Transmit Data Level Register*/
|
||||
#define I2C_DMA_TDLR_VALUE_MASK 0x00000007U
|
||||
#define I2C_DMA_TDLR_VALUE(x) ((x) << 0)
|
||||
|
||||
/* DMA Receive Data Level Register*/
|
||||
#define I2C_DMA_RDLR_VALUE_MASK 0x00000007U
|
||||
#define I2C_DMA_RDLR_VALUE(x) ((x) << 0)
|
||||
|
||||
/* I2C SDA Setup Register*/
|
||||
#define I2C_SDA_SETUP_VALUE_MASK 0x000000FFU
|
||||
#define I2C_SDA_SETUP_VALUE(x) ((x) << 0)
|
||||
|
||||
/* I2C ACK General Call Register*/
|
||||
#define I2C_ACK_GENERAL_CALL_ENABLE 0x00000001U
|
||||
|
||||
/* I2C Enable Status Register*/
|
||||
#define I2C_ENABLE_STATUS_IC_ENABLE 0x00000001U
|
||||
#define I2C_ENABLE_STATUS_SLV_DIS_BUSY 0x00000002U
|
||||
#define I2C_ENABLE_STATUS_SLV_RX_DATA_LOST 0x00000004U
|
||||
|
||||
/* I2C SS, FS or FM+ spike suppression limit*/
|
||||
#define I2C_FS_SPKLEN_VALUE_MASK 0x000000FFU
|
||||
#define I2C_FS_SPKLEN_VALUE(x) ((x) << 0)
|
||||
|
||||
/* Component Parameter Register 1*/
|
||||
#define I2C_COMP_PARAM1_APB_DATA_WIDTH 0x00000003U
|
||||
#define I2C_COMP_PARAM1_MAX_SPEED_MODE 0x0000000CU
|
||||
#define I2C_COMP_PARAM1_HC_COUNT_VALUES 0x00000010U
|
||||
#define I2C_COMP_PARAM1_INTR_IO 0x00000020U
|
||||
#define I2C_COMP_PARAM1_HAS_DMA 0x00000040U
|
||||
#define I2C_COMP_PARAM1_ENCODED_PARAMS 0x00000080U
|
||||
#define I2C_COMP_PARAM1_RX_BUFFER_DEPTH 0x0000FF00U
|
||||
#define I2C_COMP_PARAM1_TX_BUFFER_DEPTH 0x00FF0000U
|
||||
|
||||
/* I2C Component Version Register*/
|
||||
#define I2C_COMP_VERSION_VALUE 0xFFFFFFFFU
|
||||
|
||||
/* I2C Component Type Register*/
|
||||
#define I2C_COMP_TYPE_VALUE 0xFFFFFFFFU
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_I2C_H */
|
|
@ -0,0 +1,628 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_I2S_H
|
||||
#define _DRIVER_I2S_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
#include "io.h"
|
||||
#include "dmac.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define I2S0_IN_D0 90
|
||||
#define I2S0_SCLK 88
|
||||
#define I2S0_WS 89
|
||||
|
||||
enum i2s_device_num_t
|
||||
{
|
||||
I2S_DEVICE_0 = 0,
|
||||
I2S_DEVICE_1 = 1,
|
||||
I2S_DEVICE_2 = 2,
|
||||
I2S_DEVICE_MAX
|
||||
};
|
||||
|
||||
enum i2s_channel_num_t
|
||||
{
|
||||
CHANNEL_0 = 0,
|
||||
CHANNEL_1 = 1,
|
||||
CHANNEL_2 = 2,
|
||||
CHANNEL_3 = 3
|
||||
};
|
||||
|
||||
enum i2s_transmit_t
|
||||
{
|
||||
TRANSMITTER = 0,
|
||||
RECEIVER = 1
|
||||
};
|
||||
|
||||
enum i2s_work_mode_t
|
||||
{
|
||||
STANDARD_MODE = 1,
|
||||
RIGHT_JUSTIFYING_MODE = 2,
|
||||
LEFT_JUSTIFYING_MODE = 4
|
||||
};
|
||||
|
||||
enum sclk_gating_cycles_t
|
||||
{
|
||||
/* Clock gating is diable */
|
||||
NO_CLOCK_GATING = 0x0,
|
||||
/* Gating after 12 sclk cycles */
|
||||
CLOCK_CYCLES_12 = 0x1,
|
||||
/* Gating after 16 sclk cycles */
|
||||
CLOCK_CYCLES_16 = 0x2,
|
||||
/* Gating after 20 sclk cycles */
|
||||
CLOCK_CYCLES_20 = 0x3,
|
||||
/* Gating after 24 sclk cycles */
|
||||
CLOCK_CYCLES_24 = 0x4
|
||||
};
|
||||
|
||||
enum word_select_cycles_t
|
||||
{
|
||||
/* 16 sclk cycles */
|
||||
SCLK_CYCLES_16 = 0x0,
|
||||
/* 24 sclk cycles */
|
||||
SCLK_CYCLES_24 = 0x1,
|
||||
/* 32 sclk cycles */
|
||||
SCLK_CYCLES_32 = 0x2
|
||||
|
||||
};
|
||||
|
||||
enum word_length_t
|
||||
{
|
||||
/* Ignore the word length */
|
||||
IGNORE_WORD_LENGTH = 0x0,
|
||||
/* 12-bit data resolution of the receiver */
|
||||
RESOLUTION_12_BIT = 0x1,
|
||||
/* 16-bit data resolution of the receiver */
|
||||
RESOLUTION_16_BIT = 0x2,
|
||||
/* 20-bit data resolution of the receiver */
|
||||
RESOLUTION_20_BIT = 0x3,
|
||||
/* 24-bit data resolution of the receiver */
|
||||
RESOLUTION_24_BIT = 0x4,
|
||||
/* 32-bit data resolution of the receiver */
|
||||
RESOLUTION_32_BIT = 0x5
|
||||
};
|
||||
|
||||
enum fifo_threshold_t
|
||||
{
|
||||
/* Interrupt trigger when FIFO level is 1 */
|
||||
TRIGGER_LEVEL_1 = 0x0,
|
||||
/* Interrupt trigger when FIFO level is 2 */
|
||||
TRIGGER_LEVEL_2 = 0x1,
|
||||
/* Interrupt trigger when FIFO level is 3 */
|
||||
TRIGGER_LEVEL_3 = 0x2,
|
||||
/* Interrupt trigger when FIFO level is 4 */
|
||||
TRIGGER_LEVEL_4 = 0x3,
|
||||
/* Interrupt trigger when FIFO level is 5 */
|
||||
TRIGGER_LEVEL_5 = 0x4,
|
||||
/* Interrupt trigger when FIFO level is 6 */
|
||||
TRIGGER_LEVEL_6 = 0x5,
|
||||
/* Interrupt trigger when FIFO level is 7 */
|
||||
TRIGGER_LEVEL_7 = 0x6,
|
||||
/* Interrupt trigger when FIFO level is 8 */
|
||||
TRIGGER_LEVEL_8 = 0x7,
|
||||
/* Interrupt trigger when FIFO level is 9 */
|
||||
TRIGGER_LEVEL_9 = 0x8,
|
||||
/* Interrupt trigger when FIFO level is 10 */
|
||||
TRIGGER_LEVEL_10 = 0x9,
|
||||
/* Interrupt trigger when FIFO level is 11 */
|
||||
TRIGGER_LEVEL_11 = 0xa,
|
||||
/* Interrupt trigger when FIFO level is 12 */
|
||||
TRIGGER_LEVEL_12 = 0xb,
|
||||
/* Interrupt trigger when FIFO level is 13 */
|
||||
TRIGGER_LEVEL_13 = 0xc,
|
||||
/* Interrupt trigger when FIFO level is 14 */
|
||||
TRIGGER_LEVEL_14 = 0xd,
|
||||
/* Interrupt trigger when FIFO level is 15 */
|
||||
TRIGGER_LEVEL_15 = 0xe,
|
||||
/* Interrupt trigger when FIFO level is 16 */
|
||||
TRIGGER_LEVEL_16 = 0xf
|
||||
};
|
||||
|
||||
|
||||
struct i2s_ier_t
|
||||
{
|
||||
/* Bit 0 is ien, 0 for disable i2s and 1 for enable i2s */
|
||||
uint32_t ien : 1;
|
||||
/* Bits [31:1] is reserved */
|
||||
uint32_t resv : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union ier_u
|
||||
{
|
||||
struct i2s_ier_t ier;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_irer_t
|
||||
{
|
||||
/* Bit 0 is receiver block enable,
|
||||
* 0 for receiver disable
|
||||
* 1 for receiver enable
|
||||
*/
|
||||
uint32_t rxen : 1;
|
||||
/* Bits [31:1] is reserved */
|
||||
uint32_t resv : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union irer_u
|
||||
{
|
||||
struct i2s_irer_t irer;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_iter_t
|
||||
{
|
||||
uint32_t txen : 1;
|
||||
/* Bit 0 is transmitter block enable,
|
||||
* 0 for transmitter disable
|
||||
* 1 for transmitter enable
|
||||
*/
|
||||
uint32_t resv : 31;
|
||||
/* Bits [31:1] is reserved */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union iter_u
|
||||
{
|
||||
struct i2s_iter_t iter;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_cer_t
|
||||
{
|
||||
uint32_t clken : 1;
|
||||
/* Bit 0 is clock generation enable/disable,
|
||||
* 0 for clock generation disable,
|
||||
* 1 for clock generation enable
|
||||
*/
|
||||
uint32_t resv : 31;
|
||||
/* Bits [31:1] is reserved */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union cer_u
|
||||
{
|
||||
struct i2s_cer_t cer;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_ccr_t
|
||||
{
|
||||
/* Bits [2:0] is used to program the gating of sclk,
|
||||
* 0x0 for clock gating is diable,
|
||||
* 0x1 for gating after 12 sclk cycles
|
||||
* 0x2 for gating after 16 sclk cycles
|
||||
* 0x3 for gating after 20 sclk cycles
|
||||
* 0x4 for gating after 24 sclk cycles
|
||||
*/
|
||||
uint32_t clk_gate : 3;
|
||||
/* Bits [4:3] used program the number of sclk cycles for which the
|
||||
* word select line stayd in the left aligned or right aligned mode.
|
||||
* 0x0 for 16sclk cycles, 0x1 for 24 sclk cycles 0x2 for 32 sclk
|
||||
* cycles
|
||||
*/
|
||||
uint32_t clk_word_size : 2;
|
||||
/* Bit[5:7] is alignment mode setting.
|
||||
* 0x1 for standard i2s format
|
||||
* 0x2 for right aligned format
|
||||
* 0x4 for left aligned format
|
||||
*/
|
||||
uint32_t align_mode : 3;
|
||||
/* Bit[8] is DMA transmit enable control */
|
||||
uint32_t dma_tx_en : 1;
|
||||
/* Bit[9] is DMA receive enable control */
|
||||
uint32_t dma_rx_en : 1;
|
||||
uint32_t dma_divide_16 : 1;
|
||||
/* Bit[10] split 32bit data to two 16 bit data and filled in left
|
||||
* and right channel. Used with dma_tx_en or dma_rx_en
|
||||
*/
|
||||
uint32_t sign_expand_en : 1;
|
||||
uint32_t resv : 20;
|
||||
/* Bits [31:11] is reseved */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union ccr_u
|
||||
{
|
||||
struct i2s_ccr_t ccr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_rxffr_t
|
||||
{
|
||||
uint32_t rxffr : 1;
|
||||
/* Bit 0 is receiver FIFO reset,
|
||||
* 0 for does not flush RX FIFO, 1 for flush RX FIFO
|
||||
*/
|
||||
uint32_t resv : 31;
|
||||
/* Bits [31:1] is reserved */
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union rxffr_u
|
||||
{
|
||||
struct i2s_rxffr_t rxffr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_lrbrthr
|
||||
{
|
||||
uint32_t fifo : 16;
|
||||
/* Bits [15:0] if used data receive or transmit */
|
||||
uint32_t resv : 16;
|
||||
};
|
||||
|
||||
union lrbthr_u
|
||||
{
|
||||
struct i2s_lrbrthr buffer;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_rthr_t
|
||||
{
|
||||
/* Bits [15:0] is right stereo data transmitted serially
|
||||
* from transmit channel input
|
||||
*/
|
||||
uint32_t rthrx : 16;
|
||||
/* Bits [31:16] is reserved */
|
||||
uint32_t resv : 16;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union rthr_u
|
||||
{
|
||||
struct i2s_rthr_t rthr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_rer_t
|
||||
{
|
||||
/* Bit 0 is receive channel enable/disable, 0 for receive channel disable,
|
||||
*1 for receive channel enable
|
||||
*/
|
||||
uint32_t rxchenx : 1;
|
||||
/* Bits [31:1] is reseved */
|
||||
uint32_t resv : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union rer_u
|
||||
{
|
||||
struct i2s_rer_t rer;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_ter_t
|
||||
{
|
||||
/* Bit 0 is transmit channel enable/disable, 0 for transmit channel disable,
|
||||
* 1 for transmit channel enable
|
||||
*/
|
||||
uint32_t txchenx : 1;
|
||||
/* Bits [31:1] is reseved */
|
||||
uint32_t resv : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union ter_u
|
||||
{
|
||||
struct i2s_ter_t ter;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_rcr_tcr_t
|
||||
{
|
||||
/* Bits [2:0] is used to program desired data resolution of
|
||||
* receiver/transmitter,
|
||||
* 0x0 for ignore the word length
|
||||
* 0x1 for 12-bit data resolution of the receiver/transmitter,
|
||||
* 0x2 for 16-bit data resolution of the receiver/transmitter,
|
||||
* 0x3 for 20-bit data resolution of the receiver/transmitter,
|
||||
* 0x4 for 24-bit data resolution of the receiver/transmitter,
|
||||
* 0x5 for 32-bit data resolution of the receiver/transmitter
|
||||
*/
|
||||
uint32_t wlen : 3;
|
||||
/* Bits [31:3] is reseved */
|
||||
uint32_t resv : 29;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union rcr_tcr_u {
|
||||
struct i2s_rcr_tcr_t rcr_tcr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_isr_t {
|
||||
/* Bit 0 is status of receiver data avaliable interrupt
|
||||
* 0x0 for RX FIFO trigger level not reached
|
||||
* 0x1 for RX FIFO trigger level is reached
|
||||
*/
|
||||
uint32_t rxda : 1;
|
||||
/* Bit 1 is status of data overrun interrupt for rx channel
|
||||
* 0x0 for RX FIFO write valid
|
||||
* 0x1 for RX FIFO write overrun
|
||||
*/
|
||||
uint32_t rxfo : 1;
|
||||
/* Bits [3:2] is reserved */
|
||||
uint32_t resv1 : 2;
|
||||
/* Bit 4 is status of transmit empty triger interrupt
|
||||
* 0x0 for TX FIFO triiger level is reach
|
||||
* 0x1 for TX FIFO trigger level is not reached
|
||||
*/
|
||||
uint32_t txfe : 1;
|
||||
/* BIt 5 is status of data overrun interrupt for the TX channel
|
||||
* 0x0 for TX FIFO write valid
|
||||
* 0x1 for TX FIFO write overrun
|
||||
*/
|
||||
uint32_t txfo : 1;
|
||||
/* BIts [31:6] is reserved */
|
||||
uint32_t resv2 : 26;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union isr_u {
|
||||
struct i2s_isr_t isr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_imr_t
|
||||
{
|
||||
/* Bit 0 is mask RX FIFO data available interrupt
|
||||
* 0x0 for unmask RX FIFO data available interrupt
|
||||
* 0x1 for mask RX FIFO data available interrupt
|
||||
*/
|
||||
uint32_t rxdam : 1;
|
||||
/* Bit 1 is mask RX FIFO overrun interrupt
|
||||
* 0x0 for unmask RX FIFO overrun interrupt
|
||||
* 0x1 for mask RX FIFO overrun interrupt
|
||||
*/
|
||||
uint32_t rxfom : 1;
|
||||
/* Bits [3:2] is reserved */
|
||||
uint32_t resv1 : 2;
|
||||
/* Bit 4 is mask TX FIFO empty interrupt,
|
||||
* 0x0 for unmask TX FIFO empty interrupt,
|
||||
* 0x1 for mask TX FIFO empty interrupt
|
||||
*/
|
||||
uint32_t txfem : 1;
|
||||
/* BIt 5 is mask TX FIFO overrun interrupt
|
||||
* 0x0 for mask TX FIFO overrun interrupt
|
||||
* 0x1 for unmash TX FIFO overrun interrupt
|
||||
*/
|
||||
uint32_t txfom : 1;
|
||||
/* Bits [31:6] is reserved */
|
||||
uint32_t resv2 : 26;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union imr_u
|
||||
{
|
||||
struct i2s_imr_t imr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_ror_t
|
||||
{
|
||||
/* Bit 0 is read this bit to clear RX FIFO data overrun interrupt
|
||||
* 0x0 for RX FIFO write valid,
|
||||
*0x1 for RX FIFO write overrun
|
||||
*/
|
||||
uint32_t rxcho : 1;
|
||||
/* Bits [31:1] is reserved */
|
||||
uint32_t resv : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union ror_u
|
||||
{
|
||||
struct i2s_ror_t ror;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_tor_t
|
||||
{
|
||||
/* Bit 0 is read this bit to clear TX FIFO data overrun interrupt
|
||||
* 0x0 for TX FIFO write valid,
|
||||
*0x1 for TX FIFO write overrun
|
||||
*/
|
||||
uint32_t txcho : 1;
|
||||
/* Bits [31:1] is reserved */
|
||||
uint32_t resv : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union tor_u
|
||||
{
|
||||
struct i2s_tor_t tor;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_rfcr_t
|
||||
{
|
||||
/* Bits [3:0] is used program the trigger level in the RX FIFO at
|
||||
* which the receiver data available interrupt generate,
|
||||
* 0x0 for interrupt trigger when FIFO level is 1,
|
||||
* 0x2 for interrupt trigger when FIFO level is 2,
|
||||
* 0x3 for interrupt trigger when FIFO level is 4,
|
||||
* 0x4 for interrupt trigger when FIFO level is 5,
|
||||
* 0x5 for interrupt trigger when FIFO level is 6,
|
||||
* 0x6 for interrupt trigger when FIFO level is 7,
|
||||
* 0x7 for interrupt trigger when FIFO level is 8,
|
||||
* 0x8 for interrupt trigger when FIFO level is 9,
|
||||
* 0x9 for interrupt trigger when FIFO level is 10,
|
||||
* 0xa for interrupt trigger when FIFO level is 11,
|
||||
* 0xb for interrupt trigger when FIFO level is 12,
|
||||
* 0xc for interrupt trigger when FIFO level is 13,
|
||||
* 0xd for interrupt trigger when FIFO level is 14,
|
||||
* 0xe for interrupt trigger when FIFO level is 15,
|
||||
* 0xf for interrupt trigger when FIFO level is 16
|
||||
*/
|
||||
uint32_t rxchdt : 4;
|
||||
/* Bits [31:4] is reserved */
|
||||
uint32_t rsvd_rfcrx : 28;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union rfcr_u
|
||||
{
|
||||
struct i2s_rfcr_t rfcr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_tfcr_t
|
||||
{
|
||||
/* Bits [3:0] is used program the trigger level in the TX FIFO at
|
||||
* which the receiver data available interrupt generate,
|
||||
* 0x0 for interrupt trigger when FIFO level is 1,
|
||||
* 0x2 for interrupt trigger when FIFO level is 2,
|
||||
* 0x3 for interrupt trigger when FIFO level is 4,
|
||||
* 0x4 for interrupt trigger when FIFO level is 5,
|
||||
* 0x5 for interrupt trigger when FIFO level is 6,
|
||||
* 0x6 for interrupt trigger when FIFO level is 7,
|
||||
* 0x7 for interrupt trigger when FIFO level is 8,
|
||||
* 0x8 for interrupt trigger when FIFO level is 9,
|
||||
* 0x9 for interrupt trigger when FIFO level is 10,
|
||||
* 0xa for interrupt trigger when FIFO level is 11,
|
||||
* 0xb for interrupt trigger when FIFO level is 12,
|
||||
* 0xc for interrupt trigger when FIFO level is 13,
|
||||
* 0xd for interrupt trigger when FIFO level is 14,
|
||||
* 0xe for interrupt trigger when FIFO level is 15,
|
||||
* 0xf for interrupt trigger when FIFO level is 16
|
||||
*/
|
||||
uint32_t txchet : 4;
|
||||
/* Bits [31:4] is reserved */
|
||||
uint32_t rsvd_tfcrx : 28;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union tfcr_u
|
||||
{
|
||||
struct i2s_tfcr_t tfcr;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_rff_t
|
||||
{
|
||||
/* Bit 0 is receiver channel FIFO reset,
|
||||
* 0x0 for does not flush an individual RX FIFO,
|
||||
* 0x1 for flush an indiviadual RX FIFO
|
||||
*/
|
||||
uint32_t rxchfr : 1;
|
||||
/*< Bits [31:1] is reserved ,write only */
|
||||
uint32_t rsvd_rffx : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union rff_u
|
||||
{
|
||||
struct i2s_rff_t rff;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_tff_t
|
||||
{
|
||||
/* Bit 0 is transmit channel FIFO reset,
|
||||
* 0x0 for does not flush an individual TX FIFO,
|
||||
* 0x1 for flush an indiviadual TX FIFO
|
||||
*/
|
||||
uint32_t rtxchfr : 1;
|
||||
/*< Bits [31:1] is reserved ,write only */
|
||||
uint32_t rsvd_rffx : 31;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
union tff_u
|
||||
{
|
||||
struct i2s_tff_t tff;
|
||||
uint32_t reg_data;
|
||||
};
|
||||
|
||||
struct i2s_channel_t
|
||||
{
|
||||
/* Left Receive or Left Transmit Register (0x20) */
|
||||
volatile uint32_t left_rxtx;
|
||||
/* Right Receive or Right Transmit Register (0x24) */
|
||||
volatile uint32_t right_rxtx;
|
||||
/* Receive Enable Register (0x28) */
|
||||
volatile uint32_t rer;
|
||||
/* Transmit Enable Register (0x2c) */
|
||||
volatile uint32_t ter;
|
||||
/* Receive Configuration Register (0x30) */
|
||||
volatile uint32_t rcr;
|
||||
/* Transmit Configuration Register (0x34) */
|
||||
volatile uint32_t tcr;
|
||||
/* Interrupt Status Register (0x38) */
|
||||
volatile uint32_t isr;
|
||||
/* Interrupt Mask Register (0x3c) */
|
||||
volatile uint32_t imr;
|
||||
/* Receive Overrun Register (0x40) */
|
||||
volatile uint32_t ror;
|
||||
/* Transmit Overrun Register (0x44) */
|
||||
volatile uint32_t tor;
|
||||
/* Receive FIFO Configuration Register (0x48) */
|
||||
volatile uint32_t rfcr;
|
||||
/* Transmit FIFO Configuration Register (0x4c) */
|
||||
volatile uint32_t tfcr;
|
||||
/* Receive FIFO Flush Register (0x50) */
|
||||
volatile uint32_t rff;
|
||||
/* Transmit FIFO Flush Register (0x54) */
|
||||
volatile uint32_t tff;
|
||||
/* reserved (0x58-0x5c) */
|
||||
volatile uint32_t reserved1[2];
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/****is* i2s.api/dw_i2s_portmap
|
||||
* NAME
|
||||
* i2s_t
|
||||
* DESCRIPTION
|
||||
* This is the structure used for accessing the i2s register
|
||||
* portmap.
|
||||
* EXAMPLE
|
||||
* struct i2s_t *portmap;
|
||||
* portmap = (struct dw_i2s_portmap *) DW_APB_I2S_BASE;
|
||||
* SOURCE
|
||||
*/
|
||||
struct i2s_t
|
||||
{
|
||||
/* I2S Enable Register (0x00) */
|
||||
volatile uint32_t ier;
|
||||
/* I2S Receiver Block Enable Register (0x04) */
|
||||
volatile uint32_t irer;
|
||||
/* I2S Transmitter Block Enable Register (0x08) */
|
||||
volatile uint32_t iter;
|
||||
/* Clock Enable Register (0x0c) */
|
||||
volatile uint32_t cer;
|
||||
/* Clock Configuration Register (0x10) */
|
||||
volatile uint32_t ccr;
|
||||
/* Receiver Block FIFO Reset Register (0x04) */
|
||||
volatile uint32_t rxffr;
|
||||
/* Transmitter Block FIFO Reset Register (0x18) */
|
||||
volatile uint32_t txffr;
|
||||
/* reserved (0x1c) */
|
||||
volatile uint32_t reserved1;
|
||||
volatile struct i2s_channel_t channel[4];
|
||||
/* reserved (0x118-0x1bc) */
|
||||
volatile uint32_t reserved2[40];
|
||||
/* Receiver Block DMA Register (0x1c0) */
|
||||
volatile uint32_t rxdma;
|
||||
/* Reset Receiver Block DMA Register (0x1c4) */
|
||||
volatile uint32_t rrxdma;
|
||||
/* Transmitter Block DMA Register (0x1c8) */
|
||||
volatile uint32_t txdma;
|
||||
/* Reset Transmitter Block DMA Register (0x1cc) */
|
||||
volatile uint32_t rtxdma;
|
||||
/* reserved (0x1d0-0x1ec) */
|
||||
volatile uint32_t reserved3[8];
|
||||
/* Component Parameter Register 2 (0x1f0) */
|
||||
volatile uint32_t i2s_comp_param_2;
|
||||
/* Component Parameter Register 1 (0x1f4) */
|
||||
volatile uint32_t i2s_comp_param_1;
|
||||
/* I2S Component Version Register (0x1f8) */
|
||||
volatile uint32_t i2s_comp_version_1;
|
||||
/* I2S Component Type Register (0x1fc) */
|
||||
volatile uint32_t i2s_comp_type;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
|
@ -0,0 +1,56 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_IO_H
|
||||
#define _DRIVER_IO_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define readb(addr) (*(volatile uint8_t*)(addr))
|
||||
#define readw(addr) (*(volatile uint16_t*)(addr))
|
||||
#define readl(addr) (*(volatile uint32_t*)(addr))
|
||||
#define readq(addr) (*(volatile uint64_t*)(addr))
|
||||
|
||||
#define writeb(v, addr) \
|
||||
{ \
|
||||
(*(volatile uint8_t*)(addr)) = (v); \
|
||||
}
|
||||
#define writew(v, addr) \
|
||||
{ \
|
||||
(*(volatile uint16_t*)(addr)) = (v); \
|
||||
}
|
||||
#define writel(v, addr) \
|
||||
{ \
|
||||
(*(volatile uint32_t*)(addr)) = (v); \
|
||||
}
|
||||
#define writeq(v, addr) \
|
||||
{ \
|
||||
(*(volatile uint64_t*)(addr)) = (v); \
|
||||
}
|
||||
|
||||
uint32_t get_bit_mask(volatile uint32_t* bits, uint32_t mask);
|
||||
void set_bit_mask(volatile uint32_t* bits, uint32_t mask, uint32_t value);
|
||||
uint32_t get_bit_idx(volatile uint32_t* bits, size_t idx);
|
||||
void set_bit_idx(volatile uint32_t* bits, size_t idx, uint32_t value);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_IO_H */
|
|
@ -0,0 +1,361 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_OTP_H
|
||||
#define _DRIVER_OTP_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* clang-format off */
|
||||
#define OTP_COMMON_DATA_ADDR 0x00000000U
|
||||
#define OTP_SYSTEM_DATA_ADDR 0x00003AD0U
|
||||
#define OTP_BISR_DATA_ADDR 0x00003DD0U
|
||||
#define OTP_BLOCK_CTL_ADDR 0x00003FD0U
|
||||
#define OTP_WIRED_REG_ADDR 0x00003FE0U
|
||||
#define OTP_AES_KEY_ADDR 0x00003FF0U
|
||||
|
||||
#define OTP_BUSY_FLAG 0x00000001U
|
||||
#define OTP_BYPASS_FLAG 0x00000002U
|
||||
#define OTP_TEST_FLAG 0x00000004U
|
||||
/* clang-format on */
|
||||
|
||||
enum otp_status_t
|
||||
{
|
||||
OTP_OK = 0,
|
||||
OTP_ERROR_TIMEOUT, /* operation timeout*/
|
||||
OTP_ERROR_ADDRESS, /* invalid address*/
|
||||
OTP_ERROR_WRITE, /* write error*/
|
||||
OTP_ERROR_BLANK, /* blank check error*/
|
||||
OTP_ERROR_BISR, /* bisr error*/
|
||||
OTP_ERROR_TESTDEC, /* testdec error*/
|
||||
OTP_ERROR_WRTEST, /* wrtest error*/
|
||||
OTP_ERROR_KEYCOMP, /* key is wrong*/
|
||||
OTP_ERROR_PARAM, /* param error*/
|
||||
OTP_ERROR_NULL, /* undefine error*/
|
||||
OTP_BLOCK_NORMAL, /* block can be written*/
|
||||
OTP_BLOCK_PROTECTED,/* block can not be written*/
|
||||
OTP_FUNC_ENABLE, /* function available*/
|
||||
OTP_FUNC_DISABLE, /* function unavailable*/
|
||||
OTP_FLAG_SET, /* flag set*/
|
||||
OTP_FLAG_UNSET, /* flag unset*/
|
||||
};
|
||||
|
||||
enum otp_data_block_t
|
||||
{
|
||||
COMMON_DATA_BLOCK1 = 0,
|
||||
COMMON_DATA_BLOCK2,
|
||||
COMMON_DATA_BLOCK3,
|
||||
COMMON_DATA_BLOCK4,
|
||||
COMMON_DATA_BLOCK5,
|
||||
COMMON_DATA_BLOCK6,
|
||||
COMMON_DATA_BLOCK7,
|
||||
COMMON_DATA_BLOCK8,
|
||||
COMMON_DATA_BLOCK9,
|
||||
COMMON_DATA_BLOCK10,
|
||||
COMMON_DATA_BLOCK11,
|
||||
COMMON_DATA_BLOCK12,
|
||||
COMMON_DATA_BLOCK13,
|
||||
COMMON_DATA_BLOCK14,
|
||||
COMMON_DATA_BLOCK15,
|
||||
DATA_BLOCK_RESERVE,
|
||||
SYSTEM_DATA_BLOCK1,
|
||||
SYSTEM_DATA_BLOCK2,
|
||||
SYSTEM_DATA_BLOCK3,
|
||||
SYSTEM_DATA_BLOCK4,
|
||||
SYSTEM_DATA_BLOCK5,
|
||||
SYSTEM_DATA_BLOCK6,
|
||||
SYSTEM_DATA_BLOCK7,
|
||||
SYSTEM_DATA_BLOCK8,
|
||||
SYSTEM_DATA_BLOCK9,
|
||||
SYSTEM_DATA_BLOCK10,
|
||||
SYSTEM_DATA_BLOCK11,
|
||||
SYSTEM_DATA_BLOCK12,
|
||||
SYSTEM_DATA_BLOCK13,
|
||||
SYSTEM_DATA_BLOCK14,
|
||||
SYSTEM_DATA_BLOCK15,
|
||||
SYSTEM_DATA_BLOCK16,
|
||||
SYSTEM_DATA_BLOCK17,
|
||||
SYSTEM_DATA_BLOCK18,
|
||||
SYSTEM_DATA_BLOCK19,
|
||||
SYSTEM_DATA_BLOCK20,
|
||||
SYSTEM_DATA_BLOCK21,
|
||||
SYSTEM_DATA_BLOCK22,
|
||||
SYSTEM_DATA_BLOCK23,
|
||||
SYSTEM_DATA_BLOCK24,
|
||||
SYSTEM_DATA_BLOCK25,
|
||||
SYSTEM_DATA_BLOCK26,
|
||||
SYSTEM_DATA_BLOCK27,
|
||||
SYSTEM_DATA_BLOCK28,
|
||||
SYSTEM_DATA_BLOCK29,
|
||||
SYSTEM_DATA_BLOCK30,
|
||||
SYSTEM_DATA_BLOCK31,
|
||||
SYSTEM_DATA_BLOCK32,
|
||||
SYSTEM_DATA_BLOCK33,
|
||||
SYSTEM_DATA_BLOCK34,
|
||||
SYSTEM_DATA_BLOCK35,
|
||||
SYSTEM_DATA_BLOCK36,
|
||||
SYSTEM_DATA_BLOCK37,
|
||||
SYSTEM_DATA_BLOCK38,
|
||||
SYSTEM_DATA_BLOCK39,
|
||||
SYSTEM_DATA_BLOCK40,
|
||||
SYSTEM_DATA_BLOCK41,
|
||||
SYSTEM_DATA_BLOCK42,
|
||||
SYSTEM_DATA_BLOCK43,
|
||||
SYSTEM_DATA_BLOCK44,
|
||||
SYSTEM_DATA_BLOCK45,
|
||||
SYSTEM_DATA_BLOCK46,
|
||||
SYSTEM_DATA_BLOCK47,
|
||||
SYSTEM_DATA_BLOCK48,
|
||||
DATA_BLOCK_MAX = 64,
|
||||
};
|
||||
|
||||
enum otp_func_reg_t
|
||||
{
|
||||
BLANK_TEST_DISABLE = 0,
|
||||
RAM_BISR_DISABLE,
|
||||
AES_WRITE_DISABLE,
|
||||
AES_VERIFY_DISABLE,
|
||||
JTAG_DISABLE,
|
||||
TEST_EN_DISABLE = 6,
|
||||
ISP_DISABLE,
|
||||
OTP_FUNC_FIRMWARE_CIPHER_DISABLE,
|
||||
FUNC_REG_MAX = 64,
|
||||
};
|
||||
|
||||
struct otp_t
|
||||
{
|
||||
volatile uint32_t otp_ceb;
|
||||
volatile uint32_t otp_test_mode;
|
||||
volatile uint32_t otp_mode;
|
||||
volatile uint32_t gb_otp_en;
|
||||
volatile uint32_t dat_in_finish;
|
||||
volatile uint32_t otp_bisr_fail;
|
||||
volatile uint32_t test_step;
|
||||
volatile uint32_t otp_pwrrdy;
|
||||
volatile uint32_t otp_last_dat;
|
||||
volatile uint32_t otp_data;
|
||||
volatile uint32_t otp_pwr_mode;
|
||||
volatile uint32_t otp_in_dat;
|
||||
volatile uint32_t otp_apb_adr;
|
||||
volatile uint32_t td_result;
|
||||
volatile uint32_t data_acp_flag;
|
||||
volatile uint32_t otp_adr_in_flag;
|
||||
volatile uint32_t wr_result;
|
||||
volatile uint32_t otp_thershold;
|
||||
volatile uint32_t bisr_finish;
|
||||
volatile uint32_t key_cmp_result;
|
||||
volatile uint32_t otp_cmp_key;
|
||||
volatile uint32_t cmp_result_rdy;
|
||||
volatile uint32_t otp_cle;
|
||||
volatile uint32_t data_blk_ctrl;
|
||||
volatile uint32_t otp_wrg_adr_flag;
|
||||
volatile uint32_t pro_wrong;
|
||||
volatile uint32_t otp_status;
|
||||
volatile uint32_t otp_pro_adr;
|
||||
volatile uint32_t blank_finish;
|
||||
volatile uint32_t bisr2otp_en;
|
||||
volatile uint32_t otp_cpu_ctrl;
|
||||
volatile uint32_t otp_web_cpu;
|
||||
volatile uint32_t otp_rstb_cpu;
|
||||
volatile uint32_t otp_seltm_cpu;
|
||||
volatile uint32_t otp_readen_cpu;
|
||||
volatile uint32_t otp_pgmen_cpu;
|
||||
volatile uint32_t otp_dle_cpu;
|
||||
volatile uint32_t otp_din_cpu;
|
||||
volatile uint32_t otp_cpumpen_cpu;
|
||||
volatile uint32_t otp_cle_cpu;
|
||||
volatile uint32_t otp_ceb_cpu;
|
||||
volatile uint32_t otp_adr_cpu;
|
||||
volatile uint32_t otp_dat_cpu;
|
||||
volatile uint32_t otp_data_rdy;
|
||||
volatile uint32_t block_flag_high;
|
||||
volatile uint32_t block_flag_low;
|
||||
volatile uint32_t reg_flag_high;
|
||||
volatile uint32_t reg_flag_low;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Init OTP
|
||||
*
|
||||
* @note The otp clock frequency is 12.5M by default
|
||||
*
|
||||
* @param[in] div bus_clk / otp_clk
|
||||
*/
|
||||
void otp_init(uint8_t div);
|
||||
|
||||
/**
|
||||
* @brief Enable otp test mode
|
||||
*/
|
||||
void otp_test_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable otp test mode
|
||||
*/
|
||||
void otp_test_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Enable key output to aes
|
||||
*/
|
||||
void otp_key_output_enable(void);
|
||||
|
||||
/**
|
||||
* @brief Disable key output to aes
|
||||
*/
|
||||
void otp_key_output_disable(void);
|
||||
|
||||
/**
|
||||
* @brief Get the wrong address when programming fails
|
||||
*
|
||||
* @return The wrong address
|
||||
*/
|
||||
uint32_t otp_wrong_address_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get OTP status
|
||||
*
|
||||
* @param[in] flag status flag
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_status_get(uint32_t flag);
|
||||
|
||||
/**
|
||||
* @brief Perform the blank check operation
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_blank_check(void);
|
||||
|
||||
/**
|
||||
* @brief Perform the testdec operation
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_testdec(void);
|
||||
|
||||
/**
|
||||
* @brief Perform the wrtest operation
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_wrtest(void);
|
||||
|
||||
/**
|
||||
* @brief Write data
|
||||
*
|
||||
* @param[in] addr Start programming address(bit)
|
||||
* @param[in] data_buf Need to write the data point
|
||||
* @param[in] length Need to write the data length(bit)
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_write_data(uint32_t addr, uint8_t *data_buf, uint32_t length);
|
||||
|
||||
/**
|
||||
* @brief Read data
|
||||
*
|
||||
* @param[in] addr Start read address(bit).
|
||||
* @param[in] data_buf Need to read the data point
|
||||
* @param[in] length Need to read the data length(bit)
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_read_data(uint32_t addr, uint8_t *data_buf, uint32_t length);
|
||||
|
||||
/**
|
||||
* @brief Write the key
|
||||
*
|
||||
* @param[in] data_buf The key data,length is 128 bits(4 words)
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_key_write(uint8_t *data_buf);
|
||||
|
||||
/**
|
||||
* @brief Compare the key
|
||||
*
|
||||
* @param[in] data_buf The key data,length is 128 bits(4 words)
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_key_compare(uint8_t *data_buf);
|
||||
|
||||
/**
|
||||
* @brief Data block write protect
|
||||
*
|
||||
* @param[in] block Need to write a protected data block
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_data_block_protect_set(enum otp_data_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Disable the specified function
|
||||
*
|
||||
* @param[in] reg Need to disable the function
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_func_reg_disable_set(enum otp_func_reg_t func);
|
||||
|
||||
/**
|
||||
* @brief Get the data block status
|
||||
*
|
||||
* @param[in] block The specified data block
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_data_block_protect_get(enum otp_data_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Get the function status
|
||||
*
|
||||
* @param[in] reg The specified function
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_func_reg_disable_get(enum otp_func_reg_t func);
|
||||
|
||||
/**
|
||||
* @brief Refresh the data block status
|
||||
*
|
||||
* @param[in] block The specified data block
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_data_block_protect_refresh(enum otp_data_block_t block);
|
||||
|
||||
/**
|
||||
* @brief Write data(bypass mode)
|
||||
*
|
||||
* @param[in] addr Start programming address(bit)
|
||||
* @param[in] data_buf Need to write the data point
|
||||
* @param[in] length Need to write the data length(bit)
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_soft_write(uint32_t addr, uint8_t *data_buf, uint32_t length);
|
||||
|
||||
/**
|
||||
* @brief Read data(bypass mode)
|
||||
*
|
||||
* @param[in] addr Start read address(bit).Be sure to align 16 bits
|
||||
* @param[in] data_buf Need to read the data point
|
||||
* @param[in] length Need to read the data length(half word/16bits)
|
||||
*
|
||||
* @return Results of the operation
|
||||
*/
|
||||
enum otp_status_t otp_soft_read(uint32_t addr, uint8_t *data_buf, uint32_t length);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,462 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief The PLIC complies with the RISC-V Privileged Architecture
|
||||
* specification, and can support a maximum of 1023 external
|
||||
* interrupt sources targeting up to 15,872 hart contexts.
|
||||
*
|
||||
* @note PLIC RAM Layout
|
||||
*
|
||||
* | Address | Description |
|
||||
* |-----------|---------------------------------|
|
||||
* |0x0C000000 | Reserved |
|
||||
* |0x0C000004 | source 1 priority |
|
||||
* |0x0C000008 | source 2 priority |
|
||||
* |... | ... |
|
||||
* |0x0C000FFC | source 1023 priority |
|
||||
* | | |
|
||||
* |0x0C001000 | Start of pending array |
|
||||
* |... | (read-only) |
|
||||
* |0x0C00107C | End of pending array |
|
||||
* |0x0C001080 | Reserved |
|
||||
* |... | ... |
|
||||
* |0x0C001FFF | Reserved |
|
||||
* | | |
|
||||
* |0x0C002000 | target 0 enables |
|
||||
* |0x0C002080 | target 1 enables |
|
||||
* |... | ... |
|
||||
* |0x0C1F1F80 | target 15871 enables |
|
||||
* |0x0C1F2000 | Reserved |
|
||||
* |... | ... |
|
||||
* |0x0C1FFFFC | Reserved |
|
||||
* | | |
|
||||
* |0x0C200000 | target 0 priority threshold |
|
||||
* |0x0C200004 | target 0 claim/complete |
|
||||
* |... | ... |
|
||||
* |0x0C201000 | target 1 priority threshold |
|
||||
* |0x0C201004 | target 1 claim/complete |
|
||||
* |... | ... |
|
||||
* |0x0FFFF000 | target 15871 priority threshold |
|
||||
* |0x0FFFF004 | target 15871 claim/complete |
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_PLIC_H
|
||||
#define _DRIVER_PLIC_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "encoding.h"
|
||||
#include "platform.h"
|
||||
|
||||
/* For c++ compatibility */
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
/* IRQ number settings */
|
||||
#define PLIC_NUM_SOURCES (IRQN_MAX - 1)
|
||||
#define PLIC_NUM_PRIORITIES (7)
|
||||
|
||||
/* Real number of cores */
|
||||
#define PLIC_NUM_HARTS (2)
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief PLIC External Interrupt Numbers
|
||||
*
|
||||
* @note PLIC interrupt sources
|
||||
*
|
||||
* | Source | Name | Description |
|
||||
* |--------|--------------------------|------------------------------------|
|
||||
* | 0 | IRQN_NO_INTERRUPT | The non-existent interrupt |
|
||||
* | 1 | IRQN_SPI0_INTERRUPT | SPI0 interrupt |
|
||||
* | 2 | IRQN_SPI1_INTERRUPT | SPI1 interrupt |
|
||||
* | 3 | IRQN_SPI_SLAVE_INTERRUPT | SPI_SLAVE interrupt |
|
||||
* | 4 | IRQN_SPI3_INTERRUPT | SPI3 interrupt |
|
||||
* | 5 | IRQN_I2S0_INTERRUPT | I2S0 interrupt |
|
||||
* | 6 | IRQN_I2S1_INTERRUPT | I2S1 interrupt |
|
||||
* | 7 | IRQN_I2S2_INTERRUPT | I2S2 interrupt |
|
||||
* | 8 | IRQN_I2C0_INTERRUPT | I2C0 interrupt |
|
||||
* | 9 | IRQN_I2C1_INTERRUPT | I2C1 interrupt |
|
||||
* | 10 | IRQN_I2C2_INTERRUPT | I2C2 interrupt |
|
||||
* | 11 | IRQN_UART1_INTERRUPT | UART1 interrupt |
|
||||
* | 12 | IRQN_UART2_INTERRUPT | UART2 interrupt |
|
||||
* | 13 | IRQN_UART3_INTERRUPT | UART3 interrupt |
|
||||
* | 14 | IRQN_TIMER0A_INTERRUPT | TIMER0 channel 0 or 1 interrupt |
|
||||
* | 15 | IRQN_TIMER0B_INTERRUPT | TIMER0 channel 2 or 3 interrupt |
|
||||
* | 16 | IRQN_TIMER1A_INTERRUPT | TIMER1 channel 0 or 1 interrupt |
|
||||
* | 17 | IRQN_TIMER1B_INTERRUPT | TIMER1 channel 2 or 3 interrupt |
|
||||
* | 18 | IRQN_TIMER2A_INTERRUPT | TIMER2 channel 0 or 1 interrupt |
|
||||
* | 19 | IRQN_TIMER2B_INTERRUPT | TIMER2 channel 2 or 3 interrupt |
|
||||
* | 20 | IRQN_RTC_INTERRUPT | RTC tick and alarm interrupt |
|
||||
* | 21 | IRQN_WDT0_INTERRUPT | Watching dog timer0 interrupt |
|
||||
* | 22 | IRQN_WDT1_INTERRUPT | Watching dog timer1 interrupt |
|
||||
* | 23 | IRQN_APB_GPIO_INTERRUPT | APB GPIO interrupt |
|
||||
* | 24 | IRQN_DVP_INTERRUPT | Digital video port interrupt |
|
||||
* | 25 | IRQN_AI_INTERRUPT | AI accelerator interrupt |
|
||||
* | 26 | IRQN_FFT_INTERRUPT | FFT accelerator interrupt |
|
||||
* | 27 | IRQN_DMA0_INTERRUPT | DMA channel0 interrupt |
|
||||
* | 28 | IRQN_DMA1_INTERRUPT | DMA channel1 interrupt |
|
||||
* | 29 | IRQN_DMA2_INTERRUPT | DMA channel2 interrupt |
|
||||
* | 30 | IRQN_DMA3_INTERRUPT | DMA channel3 interrupt |
|
||||
* | 31 | IRQN_DMA4_INTERRUPT | DMA channel4 interrupt |
|
||||
* | 32 | IRQN_DMA5_INTERRUPT | DMA channel5 interrupt |
|
||||
* | 33 | IRQN_UARTHS_INTERRUPT | Hi-speed UART0 interrupt |
|
||||
* | 34 | IRQN_GPIOHS0_INTERRUPT | Hi-speed GPIO0 interrupt |
|
||||
* | 35 | IRQN_GPIOHS1_INTERRUPT | Hi-speed GPIO1 interrupt |
|
||||
* | 36 | IRQN_GPIOHS2_INTERRUPT | Hi-speed GPIO2 interrupt |
|
||||
* | 37 | IRQN_GPIOHS3_INTERRUPT | Hi-speed GPIO3 interrupt |
|
||||
* | 38 | IRQN_GPIOHS4_INTERRUPT | Hi-speed GPIO4 interrupt |
|
||||
* | 39 | IRQN_GPIOHS5_INTERRUPT | Hi-speed GPIO5 interrupt |
|
||||
* | 40 | IRQN_GPIOHS6_INTERRUPT | Hi-speed GPIO6 interrupt |
|
||||
* | 41 | IRQN_GPIOHS7_INTERRUPT | Hi-speed GPIO7 interrupt |
|
||||
* | 42 | IRQN_GPIOHS8_INTERRUPT | Hi-speed GPIO8 interrupt |
|
||||
* | 43 | IRQN_GPIOHS9_INTERRUPT | Hi-speed GPIO9 interrupt |
|
||||
* | 44 | IRQN_GPIOHS10_INTERRUPT | Hi-speed GPIO10 interrupt |
|
||||
* | 45 | IRQN_GPIOHS11_INTERRUPT | Hi-speed GPIO11 interrupt |
|
||||
* | 46 | IRQN_GPIOHS12_INTERRUPT | Hi-speed GPIO12 interrupt |
|
||||
* | 47 | IRQN_GPIOHS13_INTERRUPT | Hi-speed GPIO13 interrupt |
|
||||
* | 48 | IRQN_GPIOHS14_INTERRUPT | Hi-speed GPIO14 interrupt |
|
||||
* | 49 | IRQN_GPIOHS15_INTERRUPT | Hi-speed GPIO15 interrupt |
|
||||
* | 50 | IRQN_GPIOHS16_INTERRUPT | Hi-speed GPIO16 interrupt |
|
||||
* | 51 | IRQN_GPIOHS17_INTERRUPT | Hi-speed GPIO17 interrupt |
|
||||
* | 52 | IRQN_GPIOHS18_INTERRUPT | Hi-speed GPIO18 interrupt |
|
||||
* | 53 | IRQN_GPIOHS19_INTERRUPT | Hi-speed GPIO19 interrupt |
|
||||
* | 54 | IRQN_GPIOHS20_INTERRUPT | Hi-speed GPIO20 interrupt |
|
||||
* | 55 | IRQN_GPIOHS21_INTERRUPT | Hi-speed GPIO21 interrupt |
|
||||
* | 56 | IRQN_GPIOHS22_INTERRUPT | Hi-speed GPIO22 interrupt |
|
||||
* | 57 | IRQN_GPIOHS23_INTERRUPT | Hi-speed GPIO23 interrupt |
|
||||
* | 58 | IRQN_GPIOHS24_INTERRUPT | Hi-speed GPIO24 interrupt |
|
||||
* | 59 | IRQN_GPIOHS25_INTERRUPT | Hi-speed GPIO25 interrupt |
|
||||
* | 60 | IRQN_GPIOHS26_INTERRUPT | Hi-speed GPIO26 interrupt |
|
||||
* | 61 | IRQN_GPIOHS27_INTERRUPT | Hi-speed GPIO27 interrupt |
|
||||
* | 62 | IRQN_GPIOHS28_INTERRUPT | Hi-speed GPIO28 interrupt |
|
||||
* | 63 | IRQN_GPIOHS29_INTERRUPT | Hi-speed GPIO29 interrupt |
|
||||
* | 64 | IRQN_GPIOHS30_INTERRUPT | Hi-speed GPIO30 interrupt |
|
||||
* | 65 | IRQN_GPIOHS31_INTERRUPT | Hi-speed GPIO31 interrupt |
|
||||
*
|
||||
*/
|
||||
/* clang-format off */
|
||||
typedef enum plic_irq_t
|
||||
{
|
||||
IRQN_NO_INTERRUPT = 0, /*!< The non-existent interrupt */
|
||||
IRQN_SPI0_INTERRUPT = 1, /*!< SPI0 interrupt */
|
||||
IRQN_SPI1_INTERRUPT = 2, /*!< SPI1 interrupt */
|
||||
IRQN_SPI_SLAVE_INTERRUPT = 3, /*!< SPI_SLAVE interrupt */
|
||||
IRQN_SPI3_INTERRUPT = 4, /*!< SPI3 interrupt */
|
||||
IRQN_I2S0_INTERRUPT = 5, /*!< I2S0 interrupt */
|
||||
IRQN_I2S1_INTERRUPT = 6, /*!< I2S1 interrupt */
|
||||
IRQN_I2S2_INTERRUPT = 7, /*!< I2S2 interrupt */
|
||||
IRQN_I2C0_INTERRUPT = 8, /*!< I2C0 interrupt */
|
||||
IRQN_I2C1_INTERRUPT = 9, /*!< I2C1 interrupt */
|
||||
IRQN_I2C2_INTERRUPT = 10, /*!< I2C2 interrupt */
|
||||
IRQN_UART1_INTERRUPT = 11, /*!< UART1 interrupt */
|
||||
IRQN_UART2_INTERRUPT = 12, /*!< UART2 interrupt */
|
||||
IRQN_UART3_INTERRUPT = 13, /*!< UART3 interrupt */
|
||||
IRQN_TIMER0A_INTERRUPT = 14, /*!< TIMER0 channel 0 or 1 interrupt */
|
||||
IRQN_TIMER0B_INTERRUPT = 15, /*!< TIMER0 channel 2 or 3 interrupt */
|
||||
IRQN_TIMER1A_INTERRUPT = 16, /*!< TIMER1 channel 0 or 1 interrupt */
|
||||
IRQN_TIMER1B_INTERRUPT = 17, /*!< TIMER1 channel 2 or 3 interrupt */
|
||||
IRQN_TIMER2A_INTERRUPT = 18, /*!< TIMER2 channel 0 or 1 interrupt */
|
||||
IRQN_TIMER2B_INTERRUPT = 19, /*!< TIMER2 channel 2 or 3 interrupt */
|
||||
IRQN_RTC_INTERRUPT = 20, /*!< RTC tick and alarm interrupt */
|
||||
IRQN_WDT0_INTERRUPT = 21, /*!< Watching dog timer0 interrupt */
|
||||
IRQN_WDT1_INTERRUPT = 22, /*!< Watching dog timer1 interrupt */
|
||||
IRQN_APB_GPIO_INTERRUPT = 23, /*!< APB GPIO interrupt */
|
||||
IRQN_DVP_INTERRUPT = 24, /*!< Digital video port interrupt */
|
||||
IRQN_AI_INTERRUPT = 25, /*!< AI accelerator interrupt */
|
||||
IRQN_FFT_INTERRUPT = 26, /*!< FFT accelerator interrupt */
|
||||
IRQN_DMA0_INTERRUPT = 27, /*!< DMA channel0 interrupt */
|
||||
IRQN_DMA1_INTERRUPT = 28, /*!< DMA channel1 interrupt */
|
||||
IRQN_DMA2_INTERRUPT = 29, /*!< DMA channel2 interrupt */
|
||||
IRQN_DMA3_INTERRUPT = 30, /*!< DMA channel3 interrupt */
|
||||
IRQN_DMA4_INTERRUPT = 31, /*!< DMA channel4 interrupt */
|
||||
IRQN_DMA5_INTERRUPT = 32, /*!< DMA channel5 interrupt */
|
||||
IRQN_UARTHS_INTERRUPT = 33, /*!< Hi-speed UART0 interrupt */
|
||||
IRQN_GPIOHS0_INTERRUPT = 34, /*!< Hi-speed GPIO0 interrupt */
|
||||
IRQN_GPIOHS1_INTERRUPT = 35, /*!< Hi-speed GPIO1 interrupt */
|
||||
IRQN_GPIOHS2_INTERRUPT = 36, /*!< Hi-speed GPIO2 interrupt */
|
||||
IRQN_GPIOHS3_INTERRUPT = 37, /*!< Hi-speed GPIO3 interrupt */
|
||||
IRQN_GPIOHS4_INTERRUPT = 38, /*!< Hi-speed GPIO4 interrupt */
|
||||
IRQN_GPIOHS5_INTERRUPT = 39, /*!< Hi-speed GPIO5 interrupt */
|
||||
IRQN_GPIOHS6_INTERRUPT = 40, /*!< Hi-speed GPIO6 interrupt */
|
||||
IRQN_GPIOHS7_INTERRUPT = 41, /*!< Hi-speed GPIO7 interrupt */
|
||||
IRQN_GPIOHS8_INTERRUPT = 42, /*!< Hi-speed GPIO8 interrupt */
|
||||
IRQN_GPIOHS9_INTERRUPT = 43, /*!< Hi-speed GPIO9 interrupt */
|
||||
IRQN_GPIOHS10_INTERRUPT = 44, /*!< Hi-speed GPIO10 interrupt */
|
||||
IRQN_GPIOHS11_INTERRUPT = 45, /*!< Hi-speed GPIO11 interrupt */
|
||||
IRQN_GPIOHS12_INTERRUPT = 46, /*!< Hi-speed GPIO12 interrupt */
|
||||
IRQN_GPIOHS13_INTERRUPT = 47, /*!< Hi-speed GPIO13 interrupt */
|
||||
IRQN_GPIOHS14_INTERRUPT = 48, /*!< Hi-speed GPIO14 interrupt */
|
||||
IRQN_GPIOHS15_INTERRUPT = 49, /*!< Hi-speed GPIO15 interrupt */
|
||||
IRQN_GPIOHS16_INTERRUPT = 50, /*!< Hi-speed GPIO16 interrupt */
|
||||
IRQN_GPIOHS17_INTERRUPT = 51, /*!< Hi-speed GPIO17 interrupt */
|
||||
IRQN_GPIOHS18_INTERRUPT = 52, /*!< Hi-speed GPIO18 interrupt */
|
||||
IRQN_GPIOHS19_INTERRUPT = 53, /*!< Hi-speed GPIO19 interrupt */
|
||||
IRQN_GPIOHS20_INTERRUPT = 54, /*!< Hi-speed GPIO20 interrupt */
|
||||
IRQN_GPIOHS21_INTERRUPT = 55, /*!< Hi-speed GPIO21 interrupt */
|
||||
IRQN_GPIOHS22_INTERRUPT = 56, /*!< Hi-speed GPIO22 interrupt */
|
||||
IRQN_GPIOHS23_INTERRUPT = 57, /*!< Hi-speed GPIO23 interrupt */
|
||||
IRQN_GPIOHS24_INTERRUPT = 58, /*!< Hi-speed GPIO24 interrupt */
|
||||
IRQN_GPIOHS25_INTERRUPT = 59, /*!< Hi-speed GPIO25 interrupt */
|
||||
IRQN_GPIOHS26_INTERRUPT = 60, /*!< Hi-speed GPIO26 interrupt */
|
||||
IRQN_GPIOHS27_INTERRUPT = 61, /*!< Hi-speed GPIO27 interrupt */
|
||||
IRQN_GPIOHS28_INTERRUPT = 62, /*!< Hi-speed GPIO28 interrupt */
|
||||
IRQN_GPIOHS29_INTERRUPT = 63, /*!< Hi-speed GPIO29 interrupt */
|
||||
IRQN_GPIOHS30_INTERRUPT = 64, /*!< Hi-speed GPIO30 interrupt */
|
||||
IRQN_GPIOHS31_INTERRUPT = 65, /*!< Hi-speed GPIO31 interrupt */
|
||||
IRQN_MAX
|
||||
} plic_irq_t;
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief Interrupt Source Priorities
|
||||
*
|
||||
* Each external interrupt source can be assigned a priority by
|
||||
* writing to its 32-bit memory-mapped priority register. The
|
||||
* number and value of supported priority levels can vary by
|
||||
* implementa- tion, with the simplest implementations having all
|
||||
* devices hardwired at priority 1, in which case, interrupts with
|
||||
* the lowest ID have the highest effective priority. The priority
|
||||
* registers are all WARL.
|
||||
*/
|
||||
struct plic_source_priorities_t
|
||||
{
|
||||
/* 0x0C000000: Reserved, 0x0C000004-0x0C000FFC: 1-1023 priorities */
|
||||
uint32_t priority[1024];
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Interrupt Pending Bits
|
||||
*
|
||||
* The current status of the interrupt source pending bits in the
|
||||
* PLIC core can be read from the pending array, organized as 32
|
||||
* words of 32 bits. The pending bit for interrupt ID N is stored
|
||||
* in bit (N mod 32) of word (N/32). Bit 0 of word 0, which
|
||||
* represents the non-existent interrupt source 0, is always
|
||||
* hardwired to zero. The pending bits are read-only. A pending
|
||||
* bit in the PLIC core can be cleared by setting enable bits to
|
||||
* only enable the desired interrupt, then performing a claim. A
|
||||
* pending bit can be set by instructing the associated gateway to
|
||||
* send an interrupt service request.
|
||||
*/
|
||||
struct plic_pending_bits_t {
|
||||
/* 0x0C001000-0x0C00107C: Bit 0 is zero, Bits 1-1023 is pending bits */
|
||||
uint32_t u32[32];
|
||||
/* 0x0C001080-0x0C001FFF: Reserved */
|
||||
uint8_t resv[0xF80];
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Target Interrupt Enables
|
||||
*
|
||||
* For each interrupt target, each device’s interrupt can be
|
||||
* enabled by setting the corresponding bit in that target’s
|
||||
* enables registers. The enables for a target are accessed as a
|
||||
* contiguous array of 32×32-bit words, packed the same way as the
|
||||
* pending bits. For each target, bit 0 of enable word 0
|
||||
* represents the non-existent interrupt ID 0 and is hardwired to
|
||||
* 0. Unused interrupt IDs are also hardwired to zero. The enables
|
||||
* arrays for different targets are packed contiguously in the
|
||||
* address space. Only 32-bit word accesses are supported by the
|
||||
* enables array in RV32 systems. Implementations can trap on
|
||||
* accesses to enables for non-existent targets, but must allow
|
||||
* access to the full enables array for any extant target,
|
||||
* treating all non-existent interrupt source’s enables as
|
||||
* hardwired to zero.
|
||||
*/
|
||||
struct plic_target_enables_t
|
||||
{
|
||||
/* 0x0C002000-0x0C1F1F80: target 0-15871 enables */
|
||||
struct
|
||||
{
|
||||
uint32_t enable[32];/* Offset 0x00-0x7C: Bit 0 is zero, Bits 1-1023 is bits*/
|
||||
} target[15872];
|
||||
|
||||
/* 0x0C1F2000-0x0C1FFFFC: Reserved, size 0xE000 */
|
||||
uint8_t resv[0xE000];
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief PLIC Targets
|
||||
*
|
||||
* Target Priority Thresholds The threshold for a pending
|
||||
* interrupt priority that can interrupt each target can be set in
|
||||
* the target’s threshold register. The threshold is a WARL field,
|
||||
* where different implementations can support different numbers
|
||||
* of thresholds. The simplest implementation has a threshold
|
||||
* hardwired to zero.
|
||||
*
|
||||
* Target Claim Each target can perform a claim by reading the
|
||||
* claim/complete register, which returns the ID of the highest
|
||||
* priority pending interrupt or zero if there is no pending
|
||||
* interrupt for the target. A successful claim will also
|
||||
* atomically clear the corresponding pending bit on the interrupt
|
||||
* source. A target can perform a claim at any time, even if the
|
||||
* EIP is not set. The claim operation is not affected by the
|
||||
* setting of the target’s priority threshold register.
|
||||
*
|
||||
* Target Completion A target signals it has completed running a
|
||||
* handler by writing the interrupt ID it received from the claim
|
||||
* to the claim/complete register. This is routed to the
|
||||
* corresponding interrupt gateway, which can now send another
|
||||
* interrupt request to the PLIC. The PLIC does not check whether
|
||||
* the completion ID is the same as the last claim ID for that
|
||||
* target. If the completion ID does not match an interrupt source
|
||||
* that is currently enabled for the target, the completion is
|
||||
* silently ignored.
|
||||
*/
|
||||
struct plic_target_t
|
||||
{
|
||||
/* 0x0C200000-0x0FFFF004: target 0-15871 */
|
||||
struct {
|
||||
uint32_t priority_threshold;/* Offset 0x000 */
|
||||
uint32_t claim_complete; /* Offset 0x004 */
|
||||
uint8_t resv[0xFF8]; /* Offset 0x008, Size 0xFF8 */
|
||||
} target[15872];
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Platform-Level Interrupt Controller
|
||||
*
|
||||
* PLIC is Platform-Level Interrupt Controller. The PLIC complies
|
||||
* with the RISC-V Privileged Architecture specification, and can
|
||||
* support a maximum of 1023 external interrupt sources targeting
|
||||
* up to 15,872 hart contexts.
|
||||
*/
|
||||
struct plic_t
|
||||
{
|
||||
/* 0x0C000000-0x0C000FFC */
|
||||
struct plic_source_priorities_t source_priorities;
|
||||
/* 0x0C001000-0x0C001FFF */
|
||||
const struct plic_pending_bits_t pending_bits;
|
||||
/* 0x0C002000-0x0C1FFFFC */
|
||||
struct plic_target_enables_t target_enables;
|
||||
/* 0x0C200000-0x0FFFF004 */
|
||||
struct plic_target_t targets;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
extern volatile struct plic_t *const plic;
|
||||
|
||||
/**
|
||||
* @brief Definitions for the interrupt callbacks
|
||||
*/
|
||||
typedef int (*plic_irq_callback_t)(void *ctx);
|
||||
|
||||
/**
|
||||
* @brief Initialize PLIC external interrupt
|
||||
*
|
||||
* @note This function will set MIP_MEIP. The MSTATUS_MIE must set by user.
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int plic_init(void);
|
||||
|
||||
/**
|
||||
* @brief Enable PLIC external interrupt
|
||||
*
|
||||
* @param[in] irq_number external interrupt number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
|
||||
int plic_irq_enable(plic_irq_t irq_number);
|
||||
|
||||
/**
|
||||
* @brief Disable PLIC external interrupt
|
||||
*
|
||||
* @param[in] irq_number The external interrupt number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int plic_irq_disable(plic_irq_t irq_number);
|
||||
|
||||
/**
|
||||
* @brief Set IRQ priority
|
||||
*
|
||||
* @param[in] irq_number The external interrupt number
|
||||
* @param[in] priority The priority of external interrupt number
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int plic_set_priority(plic_irq_t irq_number, uint32_t priority);
|
||||
|
||||
/**
|
||||
* @brief Get IRQ priority
|
||||
*
|
||||
* @param[in] irq_number The external interrupt number
|
||||
*
|
||||
* @return The priority of external interrupt number
|
||||
*/
|
||||
uint32_t plic_get_priority(plic_irq_t irq_number);
|
||||
|
||||
/**
|
||||
* @brief Claim an IRQ
|
||||
*
|
||||
* @return The current IRQ number
|
||||
*/
|
||||
uint32_t plic_irq_claim(void);
|
||||
|
||||
/**
|
||||
* @brief Complete an IRQ
|
||||
*
|
||||
* @param[in] source The source IRQ number to complete
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int plic_irq_complete(uint32_t source);
|
||||
|
||||
/**
|
||||
* @brief Register user callback function by IRQ number
|
||||
*
|
||||
* @param[in] irq The irq
|
||||
* @param[in] callback The callback
|
||||
* @param ctx The context
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int plic_irq_register(plic_irq_t irq, plic_irq_callback_t callback, void *ctx);
|
||||
|
||||
/**
|
||||
* @brief Deegister user callback function by IRQ number
|
||||
*
|
||||
* @param[in] irq The irq
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int plic_irq_deregister(plic_irq_t irq);
|
||||
|
||||
/* For c++ compatibility */
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_PLIC_H */
|
|
@ -0,0 +1,603 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/**
|
||||
* @file
|
||||
* @brief A real-time clock (RTC) is a computer clock that keeps track of
|
||||
* the current time.
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_RTC_H
|
||||
#define _DRIVER_RTC_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief RTC timer mode
|
||||
*
|
||||
* Timer mode selector
|
||||
* | Mode | Description |
|
||||
* |------|------------------------|
|
||||
* | 0 | Timer pause |
|
||||
* | 1 | Timer time running |
|
||||
* | 2 | Timer time setting |
|
||||
*/
|
||||
typedef enum _rtc_timer_mode_e
|
||||
{
|
||||
/* 0: Timer pause */
|
||||
RTC_TIMER_PAUSE,
|
||||
/* 1: Timer time running */
|
||||
RTC_TIMER_RUNNING,
|
||||
/* 2: Timer time setting */
|
||||
RTC_TIMER_SETTING,
|
||||
/* Max count of this enum*/
|
||||
RTC_TIMER_MAX
|
||||
}rtc_timer_mode_e;
|
||||
|
||||
/*
|
||||
* @brief RTC tick interrupt mode
|
||||
*
|
||||
* Tick interrupt mode selector
|
||||
* | Mode | Description |
|
||||
* |------|------------------------|
|
||||
* | 0 | Interrupt every second |
|
||||
* | 1 | Interrupt every minute |
|
||||
* | 2 | Interrupt every hour |
|
||||
* | 3 | Interrupt every day |
|
||||
*/
|
||||
typedef enum _rtc_tick_interrupt_mode_e
|
||||
{
|
||||
/* 0: Interrupt every second */
|
||||
RTC_INT_SECOND,
|
||||
/* 1: Interrupt every minute */
|
||||
RTC_INT_MINUTE,
|
||||
/* 2: Interrupt every hour */
|
||||
RTC_INT_HOUR,
|
||||
/* 3: Interrupt every day */
|
||||
RTC_INT_DAY,
|
||||
/* Max count of this enum*/
|
||||
RTC_INT_MAX
|
||||
}rtc_tick_interrupt_mode_e;
|
||||
|
||||
/**
|
||||
* @brief RTC mask structure
|
||||
*
|
||||
* RTC mask structure for common use
|
||||
*/
|
||||
struct rtc_mask_t {
|
||||
/* Reserved */
|
||||
uint32_t resv : 1;
|
||||
/* Second mask */
|
||||
uint32_t second : 1;
|
||||
/* Minute mask */
|
||||
uint32_t minute : 1;
|
||||
/* Hour mask */
|
||||
uint32_t hour : 1;
|
||||
/* Week mask */
|
||||
uint32_t week : 1;
|
||||
/* Day mask */
|
||||
uint32_t day : 1;
|
||||
/* Month mask */
|
||||
uint32_t month : 1;
|
||||
/* Year mask */
|
||||
uint32_t year : 1;
|
||||
} __attribute__((packed, aligned(1)));
|
||||
|
||||
/**
|
||||
* @brief RTC register
|
||||
*
|
||||
* @note RTC register table
|
||||
*
|
||||
* | Offset | Name | Description |
|
||||
* |-----------|----------------|-------------------------------------|
|
||||
* | 0x00 | date | Timer date information |
|
||||
* | 0x04 | time | Timer time information |
|
||||
* | 0x08 | alarm_date | Alarm date information |
|
||||
* | 0x0c | alarm_time | Alarm time information |
|
||||
* | 0x10 | initial_count | Timer counter initial value |
|
||||
* | 0x14 | current_count | Timer counter current value |
|
||||
* | 0x18 | interrupt_ctrl | RTC interrupt settings |
|
||||
* | 0x1c | register_ctrl | RTC register settings |
|
||||
* | 0x20 | reserved0 | Reserved |
|
||||
* | 0x24 | reserved1 | Reserved |
|
||||
* | 0x28 | extended | Timer extended information |
|
||||
*
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Timer date information
|
||||
*
|
||||
* No. 0 Register (0x00)
|
||||
*/
|
||||
struct rtc_date_t
|
||||
{
|
||||
/* Week. Range [0,6]. 0 is Sunday. */
|
||||
uint32_t week : 3;
|
||||
/* Reserved */
|
||||
uint32_t resv0 : 5;
|
||||
/* Day. Range [1,31] or [1,30] or [1,29] or [1,28] */
|
||||
uint32_t day : 5;
|
||||
/* Reserved */
|
||||
uint32_t resv1 : 3;
|
||||
/* Month. Range [1,12] */
|
||||
uint32_t month : 4;
|
||||
/* Year. Range [0,99] */
|
||||
uint32_t year : 12;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Timer time information
|
||||
*
|
||||
* No. 1 Register (0x04)
|
||||
*/
|
||||
struct rtc_time_t
|
||||
{
|
||||
/* Reserved */
|
||||
uint32_t resv0 : 10;
|
||||
/* Second. Range [0,59] */
|
||||
uint32_t second : 6;
|
||||
/* Minute. Range [0,59] */
|
||||
uint32_t minute : 6;
|
||||
/* Reserved */
|
||||
uint32_t resv1 : 2;
|
||||
/* Hour. Range [0,23] */
|
||||
uint32_t hour : 5;
|
||||
/* Reserved */
|
||||
uint32_t resv2 : 3;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Alarm date information
|
||||
*
|
||||
* No. 2 Register (0x08)
|
||||
*/
|
||||
struct rtc_alarm_date_t
|
||||
{
|
||||
/* Alarm Week. Range [0,6]. 0 is Sunday. */
|
||||
uint32_t week : 3;
|
||||
/* Reserved */
|
||||
uint32_t resv0 : 5;
|
||||
/* Alarm Day. Range [1,31] or [1,30] or [1,29] or [1,28] */
|
||||
uint32_t day : 5;
|
||||
/* Reserved */
|
||||
uint32_t resv1 : 3;
|
||||
/* Alarm Month. Range [1,12] */
|
||||
uint32_t month : 4;
|
||||
/* Alarm Year. Range [0,99] */
|
||||
uint32_t year : 12;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Alarm time information
|
||||
*
|
||||
* No. 3 Register (0x0c)
|
||||
*/
|
||||
struct rtc_alarm_time_t
|
||||
{
|
||||
/* Reserved */
|
||||
uint32_t resv0 : 10;
|
||||
/* Alarm Second. Range [0,59] */
|
||||
uint32_t second : 6;
|
||||
/* Alarm Minute. Range [0,59] */
|
||||
uint32_t minute : 6;
|
||||
/* Reserved */
|
||||
uint32_t resv1 : 2;
|
||||
/* Alarm Hour. Range [0,23] */
|
||||
uint32_t hour : 5;
|
||||
/* Reserved */
|
||||
uint32_t resv2 : 3;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Timer counter initial value
|
||||
*
|
||||
* No. 4 Register (0x10)
|
||||
*/
|
||||
struct rtc_initial_count_t
|
||||
{
|
||||
/* RTC counter initial value */
|
||||
uint32_t count : 32;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Timer counter current value
|
||||
*
|
||||
* No. 5 Register (0x14)
|
||||
*/
|
||||
struct rtc_current_count_t
|
||||
{
|
||||
/* RTC counter current value */
|
||||
uint32_t count : 32;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief RTC interrupt settings
|
||||
*
|
||||
* No. 6 Register (0x18)
|
||||
*/
|
||||
struct rtc_interrupt_ctrl_t
|
||||
{
|
||||
/* Reserved */
|
||||
uint32_t tick_enable : 1;
|
||||
/* Alarm interrupt enable */
|
||||
uint32_t alarm_enable : 1;
|
||||
/* Tick interrupt enable */
|
||||
uint32_t tick_int_mode : 2;
|
||||
/* Reserved */
|
||||
uint32_t resv : 20;
|
||||
/* Alarm compare mask for interrupt */
|
||||
uint32_t alarm_compare_mask : 8;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief RTC register settings
|
||||
*
|
||||
* No. 7 Register (0x1c)
|
||||
*/
|
||||
struct rtc_register_ctrl_t
|
||||
{
|
||||
/* RTC timer read enable */
|
||||
uint32_t read_enable : 1;
|
||||
/* RTC timer write enable */
|
||||
uint32_t write_enable : 1;
|
||||
/* Reserved */
|
||||
uint32_t resv0 : 11;
|
||||
/* RTC timer mask */
|
||||
uint32_t timer_mask : 8;
|
||||
/* RTC alarm mask */
|
||||
uint32_t alarm_mask : 8;
|
||||
/* RTC counter initial count value mask */
|
||||
uint32_t initial_count_mask : 1;
|
||||
/* RTC interrupt register mask */
|
||||
uint32_t interrupt_register_mask : 1;
|
||||
/* Reserved */
|
||||
uint32_t resv1 : 1;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Reserved
|
||||
*
|
||||
* No. 8 Register (0x20)
|
||||
*/
|
||||
struct rtc_reserved0_t
|
||||
{
|
||||
/* Reserved */
|
||||
uint32_t resv : 32;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Reserved
|
||||
*
|
||||
* No. 9 Register (0x24)
|
||||
*/
|
||||
struct rtc_reserved1_t
|
||||
{
|
||||
/* Reserved */
|
||||
uint32_t resv : 32;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/**
|
||||
* @brief Timer extended information
|
||||
*
|
||||
* No. 10 Register (0x28)
|
||||
*/
|
||||
struct rtc_extended_t
|
||||
{
|
||||
/* Century. Range [0,31] */
|
||||
uint32_t century : 5;
|
||||
/* Is leap year. 1 is leap year, 0 is not leap year */
|
||||
uint32_t leap_year : 1;
|
||||
/* Reserved */
|
||||
uint32_t resv : 26;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
|
||||
/**
|
||||
* @brief Real-time clock struct
|
||||
*
|
||||
* A real-time clock (RTC) is a computer clock that keeps track of
|
||||
* the current time.
|
||||
*/
|
||||
struct rtc_t
|
||||
{
|
||||
/* No. 0 (0x00): Timer date information */
|
||||
struct rtc_date_t date;
|
||||
/* No. 1 (0x04): Timer time information */
|
||||
struct rtc_time_t time;
|
||||
/* No. 2 (0x08): Alarm date information */
|
||||
struct rtc_alarm_date_t alarm_date;
|
||||
/* No. 3 (0x0c): Alarm time information */
|
||||
struct rtc_alarm_time_t alarm_time;
|
||||
/* No. 4 (0x10): Timer counter initial value */
|
||||
struct rtc_initial_count_t initial_count;
|
||||
/* No. 5 (0x14): Timer counter current value */
|
||||
struct rtc_current_count_t current_count;
|
||||
/* No. 6 (0x18): RTC interrupt settings */
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl;
|
||||
/* No. 7 (0x1c): RTC register settings */
|
||||
struct rtc_register_ctrl_t register_ctrl;
|
||||
/* No. 8 (0x20): Reserved */
|
||||
struct rtc_reserved0_t reserved0;
|
||||
/* No. 9 (0x24): Reserved */
|
||||
struct rtc_reserved1_t reserved1;
|
||||
/* No. 10 (0x28): Timer extended information */
|
||||
struct rtc_extended_t extended;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
|
||||
/**
|
||||
* @brief Real-time clock object
|
||||
*/
|
||||
extern volatile struct rtc_t *const rtc;
|
||||
extern volatile uint32_t *const rtc_base;
|
||||
/**
|
||||
* @brief Set RTC timer mode
|
||||
*
|
||||
* @param[in] timer_mode The timer mode
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_mode_set(rtc_timer_mode_e timer_mode);
|
||||
|
||||
/**
|
||||
* @brief Get RTC timer mode
|
||||
*
|
||||
* @return The timer mode
|
||||
*/
|
||||
rtc_timer_mode_e rtc_timer_get_mode(void);
|
||||
|
||||
/**
|
||||
* @brief Set date time to RTC
|
||||
*
|
||||
* @param[in] tm The Broken-down date time
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_set_tm(const struct tm *tm);
|
||||
|
||||
/**
|
||||
* @brief Get date time from RTC
|
||||
*
|
||||
* @return The Broken-down date time
|
||||
*/
|
||||
struct tm *rtc_timer_get_tm(void);
|
||||
|
||||
/**
|
||||
* @brief Set date time to Alarm
|
||||
*
|
||||
* @param[in] tm The Broken-down date time
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_set_alarm_tm(const struct tm *tm);
|
||||
|
||||
/**
|
||||
* @brief Get date time from Alarm
|
||||
*
|
||||
* @return The Broken-down date time
|
||||
*/
|
||||
struct tm *rtc_timer_get_alarm_tm(void);
|
||||
|
||||
/**
|
||||
* @brief Check if it is a leap year
|
||||
*
|
||||
* @param[in] year The year
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_year_is_leap(int year);
|
||||
|
||||
/**
|
||||
* @brief Get day of year from date
|
||||
*
|
||||
* @param[in] year The year
|
||||
* @param[in] month The month
|
||||
* @param[in] day The day
|
||||
*
|
||||
* @return The day of year from date
|
||||
*/
|
||||
int rtc_get_yday(int year, int month, int day);
|
||||
|
||||
/**
|
||||
* @brief Get the day of the week from date
|
||||
*
|
||||
* @param[in] year The year
|
||||
* @param[in] month The month
|
||||
* @param[in] day The day
|
||||
*
|
||||
* @return The day of the week.
|
||||
* Where Sunday = 0, Monday = 1, Tuesday = 2, Wednesday = 3,
|
||||
* Thursday = 4, Friday = 5, Saturday = 6.
|
||||
*/
|
||||
int rtc_get_wday(int year, int month, int day);
|
||||
|
||||
/**
|
||||
* @brief Set date time to RTC
|
||||
*
|
||||
* @param[in] year The year
|
||||
* @param[in] month The month
|
||||
* @param[in] day The day
|
||||
* @param[in] hour The hour
|
||||
* @param[in] minute The minute
|
||||
* @param[in] second The second
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_set(int year, int month, int day, int hour, int minute, int second);
|
||||
|
||||
/**
|
||||
* @brief Get date time from RTC
|
||||
*
|
||||
* @param year The year
|
||||
* @param month The month
|
||||
* @param day The day
|
||||
* @param hour The hour
|
||||
* @param minute The minute
|
||||
* @param second The second
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second);
|
||||
|
||||
/**
|
||||
* @brief Set date time to Alarm
|
||||
*
|
||||
* @param[in] year The year
|
||||
* @param[in] month The month
|
||||
* @param[in] day The day
|
||||
* @param[in] hour The hour
|
||||
* @param[in] minute The minute
|
||||
* @param[in] second The second
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_set_alarm(int year, int month, int day, int hour, int minute, int second);
|
||||
|
||||
/**
|
||||
* @brief Get date time from Alarm
|
||||
*
|
||||
* @param year The year
|
||||
* @param month The month
|
||||
* @param day The day
|
||||
* @param hour The hour
|
||||
* @param minute The minute
|
||||
* @param second The second
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_get_alarm(int *year, int *month, int *day, int *hour, int *minute, int *second);
|
||||
|
||||
/**
|
||||
* @brief Set rtc tick interrupt
|
||||
*
|
||||
* @param enable enable or disale rtc interrupt
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_tick_interrupt_set(int enable);
|
||||
|
||||
/**
|
||||
* @brief Get tick interrupt
|
||||
*
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Disable
|
||||
* - 1 Enable
|
||||
*/
|
||||
int rtc_tick_interrupt_get(void);
|
||||
|
||||
/**
|
||||
* @brief Set tick interrupt mode
|
||||
*
|
||||
* @param mode The mode interrumpted
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_tick_interrupt_mode_set(rtc_tick_interrupt_mode_e mode);
|
||||
|
||||
/**
|
||||
* @brief Get tick interrupt mode
|
||||
*
|
||||
* @return Tick interrupt mode
|
||||
*/
|
||||
rtc_tick_interrupt_mode_e rtc_tick_interrupt_mode_get(void);
|
||||
|
||||
/**
|
||||
* @brief Enable alarm interrupt
|
||||
*
|
||||
* @param enable Enable or disable alarm interrupt
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_alarm_interrupt_set(int enable);
|
||||
|
||||
/**
|
||||
* @brief Get alarm interrupt status
|
||||
*
|
||||
* @return Alarm interrupt status
|
||||
*/
|
||||
int rtc_alarm_interrupt_get(void);
|
||||
|
||||
/**
|
||||
* @brief Set alarm interrupt mask
|
||||
*
|
||||
* @param mask Alarm interrupt mask
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_alarm_interrupt_mask_set(struct rtc_mask_t mask);
|
||||
|
||||
/**
|
||||
* @brief Get alarm interrupt mask
|
||||
*
|
||||
* @return Alarm interrupt mask
|
||||
*/
|
||||
struct rtc_mask_t rtc_alarm_interrupt_mask_get(void);
|
||||
|
||||
/**
|
||||
* @brief Initialize RTC
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_init(void);
|
||||
|
||||
/**
|
||||
* @brief RTC timer set mode
|
||||
*
|
||||
* @param timer_mode timer mode
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int rtc_timer_set_mode(rtc_timer_mode_e timer_mode);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_RTC_H */
|
|
@ -0,0 +1,95 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _SHA256_H
|
||||
#define _SHA256_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "encoding.h"
|
||||
#include "platform.h"
|
||||
|
||||
#define DISABLE_SHA_DMA 0
|
||||
#define ENABLE_SHA_DMA 1
|
||||
|
||||
#define DISABLE_DOUBLE_SHA 0
|
||||
/**
|
||||
* @brief AES
|
||||
*
|
||||
*/
|
||||
struct sha256_t
|
||||
{
|
||||
uint32_t sha_result[8];
|
||||
uint32_t sha_data_in1;
|
||||
uint32_t sha_data_in2;
|
||||
uint32_t sha_data_num; /*1 unit represents 64 bytes*/
|
||||
uint32_t sha_status;
|
||||
uint32_t reserved0;
|
||||
uint32_t sha_input_ctrl;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
#define SHA256_HASH_SIZE 32
|
||||
|
||||
/* Hash size in 32-bit words */
|
||||
#define SHA256_HASH_WORDS 8
|
||||
|
||||
struct _SHA256Context
|
||||
{
|
||||
uint64_t totalLength;
|
||||
uint32_t hash[SHA256_HASH_WORDS];
|
||||
uint32_t bufferLength;
|
||||
union
|
||||
{
|
||||
uint32_t words[16];
|
||||
uint8_t bytes[64];
|
||||
} buffer;
|
||||
#ifdef RUNTIME_ENDIAN
|
||||
int littleEndian;
|
||||
#endif /* RUNTIME_ENDIAN */
|
||||
};
|
||||
|
||||
typedef struct _SHA256Context SHA256Context;
|
||||
|
||||
/**
|
||||
* @brief Sha256 initialize
|
||||
*
|
||||
* @param[in] dma_en Dma enable flag
|
||||
* @param[in] input_size Input size
|
||||
* @param[in] sc Sha256 Context point
|
||||
*
|
||||
* @return Result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int sha256_init(uint8_t dma_en, uint32_t input_size, SHA256Context *sc);
|
||||
|
||||
/**
|
||||
* @brief Sha256 update
|
||||
*
|
||||
* @param[in] sc Sha256 Context point
|
||||
* @param[in] data Input data point
|
||||
* @param[in] len Input data size
|
||||
*
|
||||
*/
|
||||
void sha256_update(SHA256Context *sc, const void *data, uint32_t len);
|
||||
|
||||
/**
|
||||
* @brief Sha256 final
|
||||
*
|
||||
* @param[in] sc Sha256 Context point
|
||||
* @param[out] hash Sha256 result
|
||||
*
|
||||
*/
|
||||
void sha256_final(SHA256Context *sc, uint8_t hash[SHA256_HASH_SIZE]);
|
||||
|
||||
#endif
|
|
@ -0,0 +1,107 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_SPI_H
|
||||
#define _DRIVER_SPI_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include "dmac.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
struct spi_t
|
||||
{
|
||||
/* SPI Control Register 0 (0x00)*/
|
||||
volatile uint32_t ctrlr0;
|
||||
/* SPI Control Register 1 (0x04)*/
|
||||
volatile uint32_t ctrlr1;
|
||||
/* SPI Enable Register (0x08)*/
|
||||
volatile uint32_t ssienr;
|
||||
/* SPI Microwire Control Register (0x0c)*/
|
||||
volatile uint32_t mwcr;
|
||||
/* SPI Slave Enable Register (0x10)*/
|
||||
volatile uint32_t ser;
|
||||
/* SPI Baud Rate Select (0x14)*/
|
||||
volatile uint32_t baudr;
|
||||
/* SPI Transmit FIFO Threshold Level (0x18)*/
|
||||
volatile uint32_t txftlr;
|
||||
/* SPI Receive FIFO Threshold Level (0x1c)*/
|
||||
volatile uint32_t rxftlr;
|
||||
/* SPI Transmit FIFO Level Register (0x20)*/
|
||||
volatile uint32_t txflr;
|
||||
/* SPI Receive FIFO Level Register (0x24)*/
|
||||
volatile uint32_t rxflr;
|
||||
/* SPI Status Register (0x28)*/
|
||||
volatile uint32_t sr;
|
||||
/* SPI Interrupt Mask Register (0x2c)*/
|
||||
volatile uint32_t imr;
|
||||
/* SPI Interrupt Status Register (0x30)*/
|
||||
volatile uint32_t isr;
|
||||
/* SPI Raw Interrupt Status Register (0x34)*/
|
||||
volatile uint32_t risr;
|
||||
/* SPI Transmit FIFO Overflow Interrupt Clear Register (0x38)*/
|
||||
volatile uint32_t txoicr;
|
||||
/* SPI Receive FIFO Overflow Interrupt Clear Register (0x3c)*/
|
||||
volatile uint32_t rxoicr;
|
||||
/* SPI Receive FIFO Underflow Interrupt Clear Register (0x40)*/
|
||||
volatile uint32_t rxuicr;
|
||||
/* SPI Multi-Master Interrupt Clear Register (0x44)*/
|
||||
volatile uint32_t msticr;
|
||||
/* SPI Interrupt Clear Register (0x48)*/
|
||||
volatile uint32_t icr;
|
||||
/* SPI DMA Control Register (0x4c)*/
|
||||
volatile uint32_t dmacr;
|
||||
/* SPI DMA Transmit Data Level (0x50)*/
|
||||
volatile uint32_t dmatdlr;
|
||||
/* SPI DMA Receive Data Level (0x54)*/
|
||||
volatile uint32_t dmardlr;
|
||||
/* SPI Identification Register (0x58)*/
|
||||
volatile uint32_t idr;
|
||||
/* SPI DWC_ssi component version (0x5c)*/
|
||||
volatile uint32_t ssic_version_id;
|
||||
/* SPI Data Register 0-36 (0x60 -- 0xec)*/
|
||||
volatile uint32_t dr[36];
|
||||
/* SPI RX Sample Delay Register (0xf0)*/
|
||||
volatile uint32_t rx_sample_delay;
|
||||
/* SPI SPI Control Register (0xf4)*/
|
||||
volatile uint32_t spi_ctrlr0;
|
||||
/* reserved (0xf8)*/
|
||||
volatile uint32_t resv;
|
||||
/* SPI XIP Mode bits (0xfc)*/
|
||||
volatile uint32_t xip_mode_bits;
|
||||
/* SPI XIP INCR transfer opcode (0x100)*/
|
||||
volatile uint32_t xip_incr_inst;
|
||||
/* SPI XIP WRAP transfer opcode (0x104)*/
|
||||
volatile uint32_t xip_wrap_inst;
|
||||
/* SPI XIP Control Register (0x108)*/
|
||||
volatile uint32_t xip_ctrl;
|
||||
/* SPI XIP Slave Enable Register (0x10c)*/
|
||||
volatile uint32_t xip_ser;
|
||||
/* SPI XIP Receive FIFO Overflow Interrupt Clear Register (0x110)*/
|
||||
volatile uint32_t xrxoicr;
|
||||
/* SPI XIP time out register for continuous transfers (0x114)*/
|
||||
volatile uint32_t xip_cnt_time_out;
|
||||
volatile uint32_t endian;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
/* clang-format on */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_SPI_H */
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,72 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_TIMER_H
|
||||
#define _DRIVER_TIMER_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
struct timer_channel_t
|
||||
{
|
||||
/* TIMER_N Load Count Register (0x00+(N-1)*0x14) */
|
||||
volatile uint32_t load_count;
|
||||
/* TIMER_N Current Value Register (0x04+(N-1)*0x14) */
|
||||
volatile uint32_t current_value;
|
||||
/* TIMER_N Control Register (0x08+(N-1)*0x14) */
|
||||
volatile uint32_t control;
|
||||
/* TIMER_N Interrupt Clear Register (0x0c+(N-1)*0x14) */
|
||||
volatile uint32_t eoi;
|
||||
/* TIMER_N Interrupt Status Register (0x10+(N-1)*0x14) */
|
||||
volatile uint32_t intr_stat;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct timer_t
|
||||
{
|
||||
/* TIMER_N Register (0x00-0x4c) */
|
||||
volatile struct timer_channel_t channel[4];
|
||||
/* reserverd (0x50-0x9c) */
|
||||
volatile uint32_t resv1[20];
|
||||
/* TIMER Interrupt Status Register (0xa0) */
|
||||
volatile uint32_t intr_stat;
|
||||
/* TIMER Interrupt Clear Register (0xa4) */
|
||||
volatile uint32_t eoi;
|
||||
/* TIMER Raw Interrupt Status Register (0xa8) */
|
||||
volatile uint32_t raw_intr_stat;
|
||||
/* TIMER Component Version Register (0xac) */
|
||||
volatile uint32_t comp_version;
|
||||
/* TIMER_N Load Count2 Register (0xb0-0xbc) */
|
||||
volatile uint32_t load_count2[4];
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
/* TIMER Control Register */
|
||||
#define TIMER_CR_ENABLE 0x00000001
|
||||
#define TIMER_CR_MODE_MASK 0x00000002
|
||||
#define TIMER_CR_FREE_MODE 0x00000000
|
||||
#define TIMER_CR_USER_MODE 0x00000002
|
||||
#define TIMER_CR_INTERRUPT_MASK 0x00000004
|
||||
#define TIMER_CR_PWM_ENABLE 0x00000008
|
||||
/* clang-format on */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_TIMER_H */
|
|
@ -0,0 +1,110 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Universal Asynchronous Receiver/Transmitter (UART)
|
||||
*
|
||||
* The UART peripheral supports the following features:
|
||||
*
|
||||
* - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
|
||||
* bit, 1 or 2 stop bits
|
||||
*
|
||||
* - 8-entry transmit and receive FIFO buffers with programmable
|
||||
* watermark interrupts
|
||||
*
|
||||
* - 16× Rx oversampling with 2/3 majority voting per bit
|
||||
*
|
||||
* The UART peripheral does not support hardware flow control or
|
||||
* other modem control signals, or synchronous serial data
|
||||
* tranfesrs.
|
||||
*
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_APBUART_H
|
||||
#define _DRIVER_APBUART_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct
|
||||
{
|
||||
union
|
||||
{
|
||||
volatile uint32_t RBR;
|
||||
volatile uint32_t DLL;
|
||||
volatile uint32_t THR;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile uint32_t DLH;
|
||||
volatile uint32_t IER;
|
||||
};
|
||||
|
||||
union
|
||||
{
|
||||
volatile uint32_t FCR;
|
||||
volatile uint32_t IIR;
|
||||
};
|
||||
|
||||
volatile uint32_t LCR;
|
||||
volatile uint32_t MCR;
|
||||
volatile uint32_t LSR;
|
||||
volatile uint32_t MSR;
|
||||
volatile uint32_t SCR;
|
||||
volatile uint32_t LPDLL;
|
||||
volatile uint32_t LPDLH;
|
||||
volatile uint32_t reserve[18];
|
||||
volatile uint32_t FAR;
|
||||
volatile uint32_t TFR;
|
||||
volatile uint32_t RFW;
|
||||
volatile uint32_t USR;
|
||||
volatile uint32_t TFL;
|
||||
volatile uint32_t RFL;
|
||||
volatile uint32_t SRR;
|
||||
volatile uint32_t SRTS;
|
||||
volatile uint32_t SBCR;
|
||||
volatile uint32_t SDMAM;
|
||||
volatile uint32_t SFE;
|
||||
volatile uint32_t SRT;
|
||||
volatile uint32_t STET;
|
||||
volatile uint32_t HTX;
|
||||
volatile uint32_t DMASA;
|
||||
volatile uint32_t TCR;
|
||||
volatile uint32_t DE_EN;
|
||||
volatile uint32_t RE_EN;
|
||||
volatile uint32_t DET;
|
||||
volatile uint32_t TAT;
|
||||
volatile uint32_t DLF;
|
||||
volatile uint32_t RAR;
|
||||
volatile uint32_t TAR;
|
||||
volatile uint32_t LCR_EXT;
|
||||
volatile uint32_t R[5];
|
||||
volatile uint32_t CPR;
|
||||
volatile uint32_t UCV;
|
||||
volatile uint32_t CTR;
|
||||
} uart_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_APBUART_H */
|
|
@ -0,0 +1,224 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* @brief Universal Asynchronous Receiver/Transmitter (UART)
|
||||
*
|
||||
* The UART peripheral supports the following features:
|
||||
*
|
||||
* - 8-N-1 and 8-N-2 formats: 8 data bits, no parity bit, 1 start
|
||||
* bit, 1 or 2 stop bits
|
||||
*
|
||||
* - 8-entry transmit and receive FIFO buffers with programmable
|
||||
* watermark interrupts
|
||||
*
|
||||
* - 16× Rx oversampling with 2/3 majority voting per bit
|
||||
*
|
||||
* The UART peripheral does not support hardware flow control or
|
||||
* other modem control signals, or synchronous serial data
|
||||
* tranfesrs.
|
||||
*
|
||||
* @note UART RAM Layout
|
||||
*
|
||||
* | Address | Name | Description |
|
||||
* |-----------|----------|---------------------------------|
|
||||
* | 0x000 | txdata | Transmit data register |
|
||||
* | 0x004 | rxdata | Receive data register |
|
||||
* | 0x008 | txctrl | Transmit control register |
|
||||
* | 0x00C | rxctrl | Receive control register |
|
||||
* | 0x010 | ie | UART interrupt enable |
|
||||
* | 0x014 | ip | UART Interrupt pending |
|
||||
* | 0x018 | div | Baud rate divisor |
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_UARTHS_H
|
||||
#define _DRIVER_UARTHS_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "platform.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
/* Register address offsets */
|
||||
#define UARTHS_REG_TXFIFO (0x00)
|
||||
#define UARTHS_REG_RXFIFO (0x04)
|
||||
#define UARTHS_REG_TXCTRL (0x08)
|
||||
#define UARTHS_REG_RXCTRL (0x0c)
|
||||
#define UARTHS_REG_IE (0x10)
|
||||
#define UARTHS_REG_IP (0x14)
|
||||
#define UARTHS_REG_DIV (0x18)
|
||||
|
||||
/* TXCTRL register */
|
||||
#define UARTHS_TXEN (0x01)
|
||||
#define UARTHS_TXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* RXCTRL register */
|
||||
#define UARTHS_RXEN (0x01)
|
||||
#define UARTHS_RXWM(x) (((x) & 0xffff) << 16)
|
||||
|
||||
/* IP register */
|
||||
#define UARTHS_IP_TXWM (0x01)
|
||||
#define UARTHS_IP_RXWM (0x02)
|
||||
/* clang-format on */
|
||||
|
||||
struct uarths_txdata_t
|
||||
{
|
||||
/* Bits [7:0] is data */
|
||||
uint32_t data : 8;
|
||||
/* Bits [30:8] is 0 */
|
||||
uint32_t zero : 23;
|
||||
/* Bit 31 is full status */
|
||||
uint32_t full : 1;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_rxdata_t
|
||||
{
|
||||
/* Bits [7:0] is data */
|
||||
uint32_t data : 8;
|
||||
/* Bits [30:8] is 0 */
|
||||
uint32_t zero : 23;
|
||||
/* Bit 31 is empty status */
|
||||
uint32_t empty : 1;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_txctrl_t
|
||||
{
|
||||
/* Bit 0 is txen, controls whether the Tx channel is active. */
|
||||
uint32_t txen : 1;
|
||||
/* Bit 1 is nstop, 0 for one stop bit and 1 for two stop bits */
|
||||
uint32_t nstop : 1;
|
||||
/* Bits [15:2] is reserved */
|
||||
uint32_t resv0 : 14;
|
||||
/* Bits [18:16] is threshold of interrupt triggers */
|
||||
uint32_t txcnt : 3;
|
||||
/* Bits [31:19] is reserved */
|
||||
uint32_t resv1 : 13;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_rxctrl_t
|
||||
{
|
||||
/* Bit 0 is txen, controls whether the Tx channel is active. */
|
||||
uint32_t rxen : 1;
|
||||
/* Bits [15:1] is reserved */
|
||||
uint32_t resv0 : 15;
|
||||
/* Bits [18:16] is threshold of interrupt triggers */
|
||||
uint32_t rxcnt : 3;
|
||||
/* Bits [31:19] is reserved */
|
||||
uint32_t resv1 : 13;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_ip_t
|
||||
{
|
||||
/* Bit 0 is txwm, raised less than txcnt */
|
||||
uint32_t txwm : 1;
|
||||
/* Bit 1 is txwm, raised greater than rxcnt */
|
||||
uint32_t rxwm : 1;
|
||||
/* Bits [31:2] is 0 */
|
||||
uint32_t zero : 30;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_ie_t
|
||||
{
|
||||
/* Bit 0 is txwm, raised less than txcnt */
|
||||
uint32_t txwm : 1;
|
||||
/* Bit 1 is txwm, raised greater than rxcnt */
|
||||
uint32_t rxwm : 1;
|
||||
/* Bits [31:2] is 0 */
|
||||
uint32_t zero : 30;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_div_t
|
||||
{
|
||||
/* Bits [31:2] is baud rate divisor register */
|
||||
uint32_t div : 16;
|
||||
/* Bits [31:16] is 0 */
|
||||
uint32_t zero : 16;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
struct uarths_t
|
||||
{
|
||||
/* Address offset 0x00 */
|
||||
struct uarths_txdata_t txdata;
|
||||
/* Address offset 0x04 */
|
||||
struct uarths_rxdata_t rxdata;
|
||||
/* Address offset 0x08 */
|
||||
struct uarths_txctrl_t txctrl;
|
||||
/* Address offset 0x0c */
|
||||
struct uarths_rxctrl_t rxctrl;
|
||||
/* Address offset 0x10 */
|
||||
struct uarths_ie_t ie;
|
||||
/* Address offset 0x14 */
|
||||
struct uarths_ip_t ip;
|
||||
/* Address offset 0x18 */
|
||||
struct uarths_div_t div;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
extern volatile struct uarths_t *const uarths;
|
||||
|
||||
/**
|
||||
* @brief Initialization Core UART
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int uart_init();
|
||||
|
||||
/**
|
||||
* @brief Put a char to UART
|
||||
*
|
||||
* @param[in] c The char to put
|
||||
*
|
||||
* @note If c is '\n', a '\r' will be appended automatically
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int uart_putchar(char c);
|
||||
|
||||
/**
|
||||
* @brief Send a string to UART
|
||||
*
|
||||
* @param[in] s The string to send
|
||||
*
|
||||
* @note The string must ending with '\0'
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - Other Fail
|
||||
*/
|
||||
int uart_puts(const char *s);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Get a byte from UART
|
||||
*
|
||||
* @return byte as int type from UART
|
||||
*/
|
||||
|
||||
int uart_getc(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_UARTHS_H */
|
|
@ -0,0 +1,189 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _DRIVER_WDT_H
|
||||
#define _DRIVER_WDT_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#include <plic.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* clang-format off */
|
||||
struct wdt_t
|
||||
{
|
||||
/* WDT Control Register (0x00) */
|
||||
volatile uint32_t cr;
|
||||
/* WDT Timeout Range Register (0x04) */
|
||||
volatile uint32_t torr;
|
||||
/* WDT Current Counter Value Register (0x08) */
|
||||
volatile uint32_t ccvr;
|
||||
/* WDT Counter Restart Register (0x0c) */
|
||||
volatile uint32_t crr;
|
||||
/* WDT Interrupt Status Register (0x10) */
|
||||
volatile uint32_t stat;
|
||||
/* WDT Interrupt Clear Register (0x14) */
|
||||
volatile uint32_t eoi;
|
||||
/* reserverd (0x18) */
|
||||
volatile uint32_t resv1;
|
||||
/* WDT Protection level Register (0x1c) */
|
||||
volatile uint32_t prot_level;
|
||||
/* reserved (0x20-0xe0) */
|
||||
volatile uint32_t resv4[49];
|
||||
/* WDT Component Parameters Register 5 (0xe4) */
|
||||
volatile uint32_t comp_param_5;
|
||||
/* WDT Component Parameters Register 4 (0xe8) */
|
||||
volatile uint32_t comp_param_4;
|
||||
/* WDT Component Parameters Register 3 (0xec) */
|
||||
volatile uint32_t comp_param_3;
|
||||
/* WDT Component Parameters Register 2 (0xf0) */
|
||||
volatile uint32_t comp_param_2;
|
||||
/* WDT Component Parameters Register 1 (0xf4) */
|
||||
volatile uint32_t comp_param_1;
|
||||
/* WDT Component Version Register (0xf8) */
|
||||
volatile uint32_t comp_version;
|
||||
/* WDT Component Type Register (0xfc) */
|
||||
volatile uint32_t comp_type;
|
||||
} __attribute__((packed, aligned(4)));
|
||||
|
||||
|
||||
#define WDT_RESET_ALL 0x00000000U
|
||||
#define WDT_RESET_CPU 0x00000001U
|
||||
|
||||
/* WDT Control Register */
|
||||
#define WDT_CR_ENABLE 0x00000001U
|
||||
#define WDT_CR_RMOD_MASK 0x00000002U
|
||||
#define WDT_CR_RMOD_RESET 0x00000000U
|
||||
#define WDT_CR_RMOD_INTERRUPT 0x00000002U
|
||||
#define WDT_CR_RPL_MASK 0x0000001CU
|
||||
#define WDT_CR_RPL(x) ((x) << 2)
|
||||
/* WDT Timeout Range Register */
|
||||
#define WDT_TORR_TOP_MASK 0x000000FFU
|
||||
#define WDT_TORR_TOP(x) ((x) << 4 | (x) << 0)
|
||||
/* WDT Current Counter Value Register */
|
||||
#define WDT_CCVR_MASK 0xFFFFFFFFU
|
||||
/* WDT Counter Restart Register */
|
||||
#define WDT_CRR_MASK 0x00000076U
|
||||
/* WDT Interrupt Status Register */
|
||||
#define WDT_STAT_MASK 0x00000001U
|
||||
/* WDT Interrupt Clear Register */
|
||||
#define WDT_EOI_MASK 0x00000001U
|
||||
/* WDT Protection level Register */
|
||||
#define WDT_PROT_LEVEL_MASK 0x00000007U
|
||||
/* WDT Component Parameter Register 5 */
|
||||
#define WDT_COMP_PARAM_5_CP_WDT_USER_TOP_MAX_MASK 0xFFFFFFFFU
|
||||
/* WDT Component Parameter Register 4 */
|
||||
#define WDT_COMP_PARAM_4_CP_WDT_USER_TOP_INIT_MAX_MASK 0xFFFFFFFFU
|
||||
/* WDT Component Parameter Register 3 */
|
||||
#define WDT_COMP_PARAM_3_CD_WDT_TOP_RST_MASK 0xFFFFFFFFU
|
||||
/* WDT Component Parameter Register 2 */
|
||||
#define WDT_COMP_PARAM_3_CP_WDT_CNT_RST_MASK 0xFFFFFFFFU
|
||||
/* WDT Component Parameter Register 1 */
|
||||
#define WDT_COMP_PARAM_1_WDT_ALWAYS_EN_MASK 0x00000001U
|
||||
#define WDT_COMP_PARAM_1_WDT_DFLT_RMOD_MASK 0x00000002U
|
||||
#define WDT_COMP_PARAM_1_WDT_DUAL_TOP_MASK 0x00000004U
|
||||
#define WDT_COMP_PARAM_1_WDT_HC_RMOD_MASK 0x00000008U
|
||||
#define WDT_COMP_PARAM_1_WDT_HC_RPL_MASK 0x00000010U
|
||||
#define WDT_COMP_PARAM_1_WDT_HC_TOP_MASK 0x00000020U
|
||||
#define WDT_COMP_PARAM_1_WDT_USE_FIX_TOP_MASK 0x00000040U
|
||||
#define WDT_COMP_PARAM_1_WDT_PAUSE_MASK 0x00000080U
|
||||
#define WDT_COMP_PARAM_1_APB_DATA_WIDTH_MASK 0x00000300U
|
||||
#define WDT_COMP_PARAM_1_WDT_DFLT_RPL_MASK 0x00001C00U
|
||||
#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_MASK 0x000F0000U
|
||||
#define WDT_COMP_PARAM_1_WDT_DFLT_TOP_INIT_MASK 0x00F00000U
|
||||
#define WDT_COMP_PARAM_1_WDT_CNT_WIDTH_MASK 0x1F000000U
|
||||
/* WDT Component Version Register */
|
||||
#define WDT_COMP_VERSION_MASK 0xFFFFFFFFU
|
||||
/* WDT Component Type Register */
|
||||
#define WDT_COMP_TYPE_MASK 0xFFFFFFFFU
|
||||
/* clang-format on */
|
||||
|
||||
/**
|
||||
* @brief WDT object instanse
|
||||
*/
|
||||
extern volatile struct wdt_t *const wdt[2];
|
||||
|
||||
/**
|
||||
* @brief Feed wdt
|
||||
*/
|
||||
void wdt_feed(uint8_t id);
|
||||
|
||||
/**
|
||||
* @brief Enable wdt
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
*
|
||||
*/
|
||||
void wdt_enable(uint8_t id);
|
||||
|
||||
/**
|
||||
* @brief Clear wdt interrupt
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
*
|
||||
*/
|
||||
void wdt_interrupt_clear(uint8_t id);
|
||||
|
||||
/**
|
||||
* @brief Clear wdt interrupt
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
* @param[in] mode Set wdt work mode
|
||||
*
|
||||
*/
|
||||
void wdt_response_mode(uint8_t id, uint8_t mode);
|
||||
|
||||
/**
|
||||
* @brief Set wdt timeout
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
* @param[in] timeout Wdt trigger time
|
||||
*
|
||||
*/
|
||||
void wdt_timeout_set(uint8_t id, uint8_t timeout);
|
||||
|
||||
/**
|
||||
* @brief Start wdt
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
* @param[in] toms Wdt trigger time
|
||||
*
|
||||
*/
|
||||
int wdt_start(uint8_t id, size_t toms);
|
||||
|
||||
/**
|
||||
* @brief Stop wdt
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
*
|
||||
*/
|
||||
void wdt_stop(uint8_t id);
|
||||
|
||||
/**
|
||||
* @brief Set wdt interrupt function
|
||||
*
|
||||
* @param[in] id Wdt id 0 or 1
|
||||
* @param[in] on_irq Wdt interrupt function
|
||||
*
|
||||
*/
|
||||
void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _DRIVER_WDT_H */
|
|
@ -0,0 +1,37 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <io.h>
|
||||
|
||||
uint32_t get_bit_mask(volatile uint32_t* bits, uint32_t mask)
|
||||
{
|
||||
return (*bits) & mask;
|
||||
}
|
||||
|
||||
void set_bit_mask(volatile uint32_t* bits, uint32_t mask, uint32_t value)
|
||||
{
|
||||
uint32_t org = (*bits) & ~mask;
|
||||
*bits = org | (value & mask);
|
||||
}
|
||||
|
||||
uint32_t get_bit_idx(volatile uint32_t* bits, size_t idx)
|
||||
{
|
||||
return ((*bits) & (1 << idx)) >> idx;
|
||||
}
|
||||
|
||||
void set_bit_idx(volatile uint32_t* bits, size_t idx, uint32_t value)
|
||||
{
|
||||
uint32_t org = (*bits) & ~(1 << idx);
|
||||
*bits = org | (value << idx);
|
||||
}
|
|
@ -0,0 +1,602 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "otp.h"
|
||||
#include "platform.h"
|
||||
#include "sysctl.h"
|
||||
|
||||
/* clang-format off */
|
||||
#define DELAY_TIMEOUT 0xFFFFFF
|
||||
#define WRTEST_NUM 0xA5
|
||||
/* clang-format on */
|
||||
|
||||
volatile struct otp_t* const otp = (volatile struct otp_t*)OTP_BASE_ADDR;
|
||||
|
||||
void otp_init(uint8_t div)
|
||||
{
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_OTP);
|
||||
otp->otp_cpu_ctrl = 0;
|
||||
otp->otp_thershold = div;
|
||||
otp->data_blk_ctrl = 0;
|
||||
otp->gb_otp_en = 0;
|
||||
otp->otp_pwr_mode = 0;
|
||||
otp->otp_web_cpu = 1;
|
||||
otp->otp_rstb_cpu = 1;
|
||||
otp->otp_seltm_cpu = 0;
|
||||
otp->otp_readen_cpu = 0;
|
||||
otp->otp_pgmen_cpu = 0;
|
||||
otp->otp_dle_cpu = 0;
|
||||
otp->otp_din_cpu = 0;
|
||||
otp->otp_cpumpen_cpu = 0;
|
||||
otp->otp_cle_cpu = 0;
|
||||
otp->otp_ceb_cpu = 1;
|
||||
otp->otp_adr_cpu = 0;
|
||||
otp->otp_dat_cpu = 0;
|
||||
}
|
||||
|
||||
void otp_test_enable(void)
|
||||
{
|
||||
otp->otp_cpu_ctrl = 0xCAAC;
|
||||
}
|
||||
|
||||
void otp_test_disable(void)
|
||||
{
|
||||
otp->otp_cpu_ctrl = 0;
|
||||
}
|
||||
|
||||
void otp_key_output_enable(void)
|
||||
{
|
||||
otp->gb_otp_en = 1;
|
||||
}
|
||||
|
||||
void otp_key_output_disable(void)
|
||||
{
|
||||
otp->gb_otp_en = 0;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_status_get(uint32_t flag)
|
||||
{
|
||||
if (otp->otp_status & flag)
|
||||
return OTP_FLAG_SET;
|
||||
return OTP_FLAG_UNSET;
|
||||
}
|
||||
|
||||
static enum otp_status_t otp_bisr_write(void)
|
||||
{
|
||||
uint32_t time_out = 0;
|
||||
|
||||
otp->otp_cle = 1;
|
||||
otp->otp_mode = 0x02;
|
||||
otp->otp_test_mode = 0x30;
|
||||
otp->test_step = 0;
|
||||
otp->otp_ceb = 0;
|
||||
while (otp->bisr_finish == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
otp->bisr_finish = 0;
|
||||
if (otp->pro_wrong)
|
||||
return OTP_ERROR_BISR;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
static enum otp_status_t otp_bisr_read(void)
|
||||
{
|
||||
uint32_t time_out = 0;
|
||||
|
||||
otp->otp_cle = 1;
|
||||
otp->otp_mode = 0x02;
|
||||
otp->otp_test_mode = 0x30;
|
||||
otp->test_step = 1;
|
||||
otp->otp_ceb = 0;
|
||||
while (otp->bisr_finish == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
otp->bisr_finish = 0;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_blank_check(void)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
uint32_t time_out = 0;
|
||||
|
||||
if (otp_func_reg_disable_get(BLANK_TEST_DISABLE) == OTP_FUNC_DISABLE)
|
||||
return OTP_FUNC_DISABLE;
|
||||
|
||||
otp->otp_cle = 1;
|
||||
otp->otp_mode = 0x02;
|
||||
otp->otp_test_mode = 0x24;
|
||||
otp->blank_finish = 0;
|
||||
otp->otp_ceb = 0;
|
||||
while (otp->blank_finish == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (otp->otp_bisr_fail)
|
||||
return OTP_ERROR_BLANK;
|
||||
|
||||
status = otp_bisr_write();
|
||||
if (status != OTP_OK)
|
||||
return status;
|
||||
status = otp_bisr_read();
|
||||
if (status != OTP_OK)
|
||||
return status;
|
||||
status = otp_func_reg_disable_set(BLANK_TEST_DISABLE);
|
||||
if (status != OTP_OK)
|
||||
return status;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_testdec(void)
|
||||
{
|
||||
uint32_t time_out = 0;
|
||||
|
||||
otp->otp_cle = 1;
|
||||
otp->otp_mode = 0x02;
|
||||
otp->otp_test_mode = 0x21;
|
||||
otp->otp_ceb = 0;
|
||||
while (otp->td_result == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (otp->td_result == 0x01)
|
||||
{
|
||||
otp->td_result = 0;
|
||||
return OTP_ERROR_TESTDEC;
|
||||
}
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_wrtest(void)
|
||||
{
|
||||
uint16_t addr, data, i, j;
|
||||
uint32_t time_out;
|
||||
|
||||
otp->otp_cle = 1;
|
||||
otp->otp_mode = 0x02;
|
||||
otp->otp_test_mode = 0x01;
|
||||
otp->test_step = 0;
|
||||
otp->data_acp_flag = 0;
|
||||
otp->otp_ceb = 0;
|
||||
addr = 0;
|
||||
for (i = 0; i < 128; i++)
|
||||
{
|
||||
data = WRTEST_NUM;
|
||||
for (j = 0; j < 8; j++)
|
||||
{
|
||||
if ((addr == 1023) || (data & 0x01))
|
||||
{
|
||||
time_out = 0;
|
||||
while (otp->otp_adr_in_flag == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
otp->otp_apb_adr = addr;
|
||||
if (addr == 1023)
|
||||
{
|
||||
otp->otp_in_dat = data & 0x01;
|
||||
otp->otp_last_dat = 0x01;
|
||||
}
|
||||
else
|
||||
otp->otp_in_dat = 0x01;
|
||||
otp->dat_in_finish = 0x01;
|
||||
time_out = 0;
|
||||
while (otp->data_acp_flag == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (otp->data_acp_flag == 0x01)
|
||||
{
|
||||
otp->data_acp_flag = 0;
|
||||
return OTP_ERROR_WRITE;
|
||||
}
|
||||
otp->data_acp_flag = 0;
|
||||
}
|
||||
data >>= 1;
|
||||
addr++;
|
||||
}
|
||||
}
|
||||
time_out = 0;
|
||||
while ((otp->wr_result & 0x04) == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
otp->wr_result &= 0xFFFFFFFB;
|
||||
|
||||
otp->otp_cle = 1;
|
||||
otp->otp_mode = 0x02;
|
||||
otp->otp_test_mode = 0x01;
|
||||
otp->test_step = 1;
|
||||
otp->data_acp_flag = 0;
|
||||
otp->otp_ceb = 0;
|
||||
addr = 0;
|
||||
for (i = 0; i < 128; i++)
|
||||
{
|
||||
time_out = 0;
|
||||
while (otp->otp_adr_in_flag == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
if (otp->wr_result == 0x01)
|
||||
{
|
||||
otp->wr_result = 0;
|
||||
return OTP_ERROR_WRTEST;
|
||||
}
|
||||
}
|
||||
otp->otp_in_dat = WRTEST_NUM;
|
||||
otp->otp_apb_adr = addr;
|
||||
if (i == 127)
|
||||
otp->otp_last_dat = 0x01;
|
||||
addr += 8;
|
||||
}
|
||||
time_out = 0;
|
||||
while ((otp->wr_result & 0x03) == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if ((otp->wr_result & 0x03) == 0x01)
|
||||
{
|
||||
otp->wr_result = 0;
|
||||
return OTP_ERROR_WRTEST;
|
||||
}
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
static enum otp_status_t otp_write_byte(uint32_t addr, uint8_t* data_buf, uint32_t length)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
uint8_t data, index;
|
||||
uint32_t time_out;
|
||||
|
||||
otp->otp_cle = 0;
|
||||
otp->otp_mode = 1;
|
||||
otp->data_acp_flag = 0;
|
||||
otp->otp_wrg_adr_flag = 0;
|
||||
otp->otp_ceb = 0;
|
||||
index = 0;
|
||||
addr *= 8;
|
||||
length *= 8;
|
||||
data = *data_buf++;
|
||||
while (length--)
|
||||
{
|
||||
if ((length == 0) || (data & 0x01))
|
||||
{
|
||||
time_out = 0;
|
||||
while (otp->otp_adr_in_flag == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
otp->otp_apb_adr = addr;
|
||||
if (length == 0)
|
||||
{
|
||||
otp->otp_in_dat = data & 0x01;
|
||||
otp->otp_last_dat = 1;
|
||||
}
|
||||
else
|
||||
otp->otp_in_dat = 1;
|
||||
otp->dat_in_finish = 1;
|
||||
time_out = 0;
|
||||
while (otp->data_acp_flag == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (otp->otp_wrg_adr_flag == 1)
|
||||
return OTP_ERROR_ADDRESS;
|
||||
if (otp->data_acp_flag == 1)
|
||||
return OTP_ERROR_WRITE;
|
||||
otp->data_acp_flag = 0;
|
||||
}
|
||||
data >>= 1;
|
||||
addr++;
|
||||
index++;
|
||||
if (index == 8)
|
||||
{
|
||||
index = 0;
|
||||
data = *data_buf++;
|
||||
}
|
||||
}
|
||||
|
||||
status = otp_bisr_write();
|
||||
if (status != OTP_OK)
|
||||
return status;
|
||||
status = otp_bisr_read();
|
||||
if (status != OTP_OK)
|
||||
return status;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
static enum otp_status_t otp_read_byte(uint32_t addr, uint8_t* data_buf, uint32_t length)
|
||||
{
|
||||
uint32_t time_out;
|
||||
|
||||
otp->otp_cle = 0;
|
||||
otp->otp_mode = 0;
|
||||
otp->otp_wrg_adr_flag = 0;
|
||||
otp->otp_ceb = 0;
|
||||
addr *= 8;
|
||||
while (length--)
|
||||
{
|
||||
time_out = 0;
|
||||
while (otp->otp_adr_in_flag == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (length == 0)
|
||||
otp->otp_last_dat = 1;
|
||||
otp->otp_apb_adr = addr;
|
||||
time_out = 0;
|
||||
while (otp->otp_data_rdy == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (otp->otp_wrg_adr_flag == 0x01)
|
||||
return OTP_ERROR_ADDRESS;
|
||||
*data_buf++ = otp->otp_data;
|
||||
addr += 8;
|
||||
}
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_write_data(uint32_t addr, uint8_t* data_buf, uint32_t length)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
|
||||
if (addr >= OTP_BISR_DATA_ADDR)
|
||||
return OTP_ERROR_ADDRESS;
|
||||
length = length <= OTP_BISR_DATA_ADDR - addr ? length : OTP_BISR_DATA_ADDR - addr;
|
||||
|
||||
status = otp_write_byte(addr, data_buf, length);
|
||||
if (status == OTP_ERROR_ADDRESS)
|
||||
status = OTP_BLOCK_PROTECTED;
|
||||
return status;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_read_data(uint32_t addr, uint8_t* data_buf, uint32_t length)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
|
||||
if (addr >= OTP_BISR_DATA_ADDR)
|
||||
return OTP_ERROR_ADDRESS;
|
||||
length = length <= OTP_BISR_DATA_ADDR - addr ? length : OTP_BISR_DATA_ADDR - addr;
|
||||
|
||||
status = otp_read_byte(addr, data_buf, length);
|
||||
if (status == OTP_ERROR_ADDRESS)
|
||||
status = OTP_ERROR_NULL;
|
||||
return status;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_key_write(uint8_t* data_buf)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
|
||||
status = otp_write_byte(OTP_AES_KEY_ADDR, data_buf, 16);
|
||||
if (status == OTP_ERROR_ADDRESS)
|
||||
status = OTP_FUNC_DISABLE;
|
||||
return status;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_key_compare(uint8_t* data_buf)
|
||||
{
|
||||
uint32_t time_out = 0;
|
||||
|
||||
otp->key_cmp_result = 0;
|
||||
otp->otp_cmp_key = ((uint32_t)data_buf[0] << 24) | ((uint32_t)data_buf[1] << 16) | ((uint32_t)data_buf[2] << 8) | (uint32_t)data_buf[3];
|
||||
otp->otp_cmp_key = ((uint32_t)data_buf[4] << 24) | ((uint32_t)data_buf[5] << 16) | ((uint32_t)data_buf[6] << 8) | (uint32_t)data_buf[7];
|
||||
otp->otp_cmp_key = ((uint32_t)data_buf[8] << 24) | ((uint32_t)data_buf[9] << 16) | ((uint32_t)data_buf[10] << 8) | (uint32_t)data_buf[11];
|
||||
otp->otp_cmp_key = ((uint32_t)data_buf[12] << 24) | ((uint32_t)data_buf[13] << 16) | ((uint32_t)data_buf[14] << 8) | (uint32_t)data_buf[15];
|
||||
while (otp->key_cmp_result == 0)
|
||||
{
|
||||
time_out++;
|
||||
if (time_out >= DELAY_TIMEOUT)
|
||||
return OTP_ERROR_TIMEOUT;
|
||||
}
|
||||
if (otp->key_cmp_result == 0x01)
|
||||
return OTP_ERROR_KEYCOMP;
|
||||
else if (otp->key_cmp_result == 0x03)
|
||||
return OTP_FUNC_DISABLE;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_data_block_protect_set(enum otp_data_block_t block)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
uint8_t value;
|
||||
|
||||
if (block >= DATA_BLOCK_MAX)
|
||||
return OTP_ERROR_PARAM;
|
||||
otp->data_blk_ctrl = 0x01;
|
||||
value = 0x03 << ((block % 4) * 2);
|
||||
status = otp_write_byte(OTP_BLOCK_CTL_ADDR + block / 4, &value, 1);
|
||||
otp->data_blk_ctrl = 0;
|
||||
return status;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_func_reg_disable_set(enum otp_func_reg_t func)
|
||||
{
|
||||
enum otp_status_t status;
|
||||
uint8_t value;
|
||||
|
||||
if (func >= FUNC_REG_MAX)
|
||||
return OTP_ERROR_PARAM;
|
||||
otp->data_blk_ctrl = 0x01;
|
||||
value = 0x03 << ((func % 4) * 2);
|
||||
status = otp_write_byte(OTP_WIRED_REG_ADDR + func / 4, &value, 1);
|
||||
otp->data_blk_ctrl = 0;
|
||||
return status;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_data_block_protect_get(enum otp_data_block_t block)
|
||||
{
|
||||
if (block < DATA_BLOCK_MAX / 2)
|
||||
{
|
||||
if (otp->block_flag_low & (0x01 << block))
|
||||
return OTP_BLOCK_PROTECTED;
|
||||
}
|
||||
else if (block < DATA_BLOCK_MAX)
|
||||
{
|
||||
if (otp->block_flag_high & (0x01 << (block - DATA_BLOCK_MAX / 2)))
|
||||
return OTP_BLOCK_PROTECTED;
|
||||
}
|
||||
else
|
||||
return OTP_ERROR_PARAM;
|
||||
return OTP_BLOCK_NORMAL;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_func_reg_disable_get(enum otp_func_reg_t func)
|
||||
{
|
||||
if (func < FUNC_REG_MAX / 2)
|
||||
{
|
||||
if (otp->reg_flag_low & (0x01 << func))
|
||||
return OTP_FUNC_DISABLE;
|
||||
}
|
||||
else if (func < FUNC_REG_MAX)
|
||||
{
|
||||
if (otp->reg_flag_high & (0x01 << (func - FUNC_REG_MAX / 2)))
|
||||
return OTP_FUNC_DISABLE;
|
||||
}
|
||||
else
|
||||
return OTP_ERROR_PARAM;
|
||||
return OTP_FUNC_ENABLE;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_data_block_protect_refresh(enum otp_data_block_t block)
|
||||
{
|
||||
uint8_t value;
|
||||
|
||||
if (block < DATA_BLOCK_MAX)
|
||||
return otp_read_byte(OTP_BLOCK_CTL_ADDR + block / 4, &value, 1);
|
||||
else
|
||||
return OTP_ERROR_PARAM;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_soft_write(uint32_t addr, uint8_t* data_buf, uint32_t length)
|
||||
{
|
||||
uint8_t data, index, count;
|
||||
|
||||
otp->otp_ceb_cpu = 1;
|
||||
otp->otp_cle_cpu = 0;
|
||||
otp->otp_seltm_cpu = 0;
|
||||
otp->otp_readen_cpu = 0;
|
||||
otp->otp_dle_cpu = 0;
|
||||
otp->otp_web_cpu = 1;
|
||||
otp->otp_cpumpen_cpu = 0;
|
||||
otp->otp_pgmen_cpu = 0;
|
||||
otp->otp_rstb_cpu = 1;
|
||||
|
||||
otp->otp_ceb_cpu = 0;
|
||||
otp->otp_rstb_cpu = 0;
|
||||
otp->otp_rstb_cpu = 1;
|
||||
|
||||
index = 0;
|
||||
addr *= 8;
|
||||
length *= 8;
|
||||
data = *data_buf++;
|
||||
while (length)
|
||||
{
|
||||
otp->otp_adr_cpu = addr;
|
||||
otp->otp_din_cpu = data & 0x01;
|
||||
otp->otp_dle_cpu = 1;
|
||||
otp->otp_web_cpu = 0;
|
||||
otp->otp_web_cpu = 1;
|
||||
otp->otp_dle_cpu = 0;
|
||||
count = 20;
|
||||
while (count--)
|
||||
{
|
||||
otp->otp_pgmen_cpu = 1;
|
||||
otp->otp_cpumpen_cpu = 1;
|
||||
otp->otp_web_cpu = 0;
|
||||
otp->otp_web_cpu = 1;
|
||||
otp->otp_cpumpen_cpu = 0;
|
||||
otp->otp_pgmen_cpu = 0;
|
||||
if (otp->otp_dat_cpu == 0)
|
||||
break;
|
||||
}
|
||||
if (otp->otp_dat_cpu & 0x01)
|
||||
break;
|
||||
data >>= 1;
|
||||
addr++;
|
||||
index++;
|
||||
if (index == 8)
|
||||
{
|
||||
index = 0;
|
||||
data = *data_buf++;
|
||||
}
|
||||
length--;
|
||||
}
|
||||
otp->otp_ceb_cpu = 1;
|
||||
if (length)
|
||||
return OTP_ERROR_WRITE;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
enum otp_status_t otp_soft_read(uint32_t addr, uint8_t* data_buf, uint32_t length)
|
||||
{
|
||||
otp->otp_ceb_cpu = 1;
|
||||
otp->otp_dle_cpu = 0;
|
||||
otp->otp_cle_cpu = 0;
|
||||
otp->otp_pgmen_cpu = 0;
|
||||
otp->otp_web_cpu = 1;
|
||||
otp->otp_readen_cpu = 0;
|
||||
otp->otp_rstb_cpu = 1;
|
||||
|
||||
otp->otp_ceb_cpu = 0;
|
||||
otp->otp_rstb_cpu = 0;
|
||||
otp->otp_rstb_cpu = 1;
|
||||
|
||||
while (length)
|
||||
{
|
||||
otp->otp_adr_cpu = addr;
|
||||
otp->otp_readen_cpu = 1;
|
||||
*data_buf++ = otp->otp_dat_cpu;
|
||||
otp->otp_readen_cpu = 0;
|
||||
addr += 8;
|
||||
length--;
|
||||
}
|
||||
otp->otp_ceb_cpu = 1;
|
||||
if (length)
|
||||
return OTP_ERROR_WRITE;
|
||||
return OTP_OK;
|
||||
}
|
||||
|
||||
uint32_t otp_wrong_address_get(void)
|
||||
{
|
||||
return otp->otp_pro_adr;
|
||||
}
|
|
@ -0,0 +1,563 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <stdlib.h>
|
||||
#include "encoding.h"
|
||||
#include "sysctl.h"
|
||||
#include "rtc.h"
|
||||
|
||||
volatile struct rtc_t *const rtc = (volatile struct rtc_t *)RTC_BASE_ADDR;
|
||||
|
||||
struct tm rtc_date_time;
|
||||
|
||||
int rtc_timer_set_mode(rtc_timer_mode_e timer_mode)
|
||||
{
|
||||
struct rtc_register_ctrl_t register_ctrl = rtc->register_ctrl;
|
||||
|
||||
switch (timer_mode) {
|
||||
case RTC_TIMER_PAUSE:
|
||||
register_ctrl.read_enable = 0;
|
||||
register_ctrl.write_enable = 0;
|
||||
break;
|
||||
case RTC_TIMER_RUNNING:
|
||||
register_ctrl.read_enable = 1;
|
||||
register_ctrl.write_enable = 0;
|
||||
break;
|
||||
case RTC_TIMER_SETTING:
|
||||
register_ctrl.read_enable = 0;
|
||||
register_ctrl.write_enable = 1;
|
||||
break;
|
||||
default:
|
||||
register_ctrl.read_enable = 0;
|
||||
register_ctrl.write_enable = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
rtc->register_ctrl = register_ctrl;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
rtc_timer_mode_e rtc_timer_get_mode(void)
|
||||
{
|
||||
struct rtc_register_ctrl_t register_ctrl = rtc->register_ctrl;
|
||||
rtc_timer_mode_e timer_mode = RTC_TIMER_PAUSE;
|
||||
|
||||
if ((!register_ctrl.read_enable) && (!register_ctrl.write_enable)) {
|
||||
/* RTC_TIMER_PAUSE */
|
||||
timer_mode = RTC_TIMER_PAUSE;
|
||||
} else if ((register_ctrl.read_enable) && (!register_ctrl.write_enable)) {
|
||||
/* RTC_TIMER_RUNNING */
|
||||
timer_mode = RTC_TIMER_RUNNING;
|
||||
} else if ((!register_ctrl.read_enable) && (register_ctrl.write_enable)) {
|
||||
/* RTC_TIMER_SETTING */
|
||||
timer_mode = RTC_TIMER_RUNNING;
|
||||
} else {
|
||||
/* Something is error, reset timer mode */
|
||||
rtc_timer_set_mode(timer_mode);
|
||||
}
|
||||
|
||||
return timer_mode;
|
||||
}
|
||||
|
||||
static inline int rtc_in_range(int value, int min, int max)
|
||||
{
|
||||
return ((value >= min) && (value <= max));
|
||||
}
|
||||
|
||||
int rtc_timer_set_tm(const struct tm *tm)
|
||||
{
|
||||
struct rtc_date_t timer_date;
|
||||
struct rtc_time_t timer_time;
|
||||
struct rtc_extended_t timer_extended;
|
||||
|
||||
if (tm) {
|
||||
/*
|
||||
* Range of tm->tm_sec could be [0,61]
|
||||
*
|
||||
* Range of tm->tm_sec allows for a positive leap second. Two
|
||||
* leap seconds in the same minute are not allowed (the C90
|
||||
* range 0..61 was a defect)
|
||||
*/
|
||||
if (rtc_in_range(tm->tm_sec, 0, 59))
|
||||
timer_time.second = tm->tm_sec;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_min could be [0,59] */
|
||||
if (rtc_in_range(tm->tm_min, 0, 59))
|
||||
timer_time.minute = tm->tm_min;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_hour could be [0, 23] */
|
||||
if (rtc_in_range(tm->tm_hour, 0, 23))
|
||||
timer_time.hour = tm->tm_hour;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_mday could be [1, 31] */
|
||||
if (rtc_in_range(tm->tm_mday, 1, 31))
|
||||
timer_date.day = tm->tm_mday;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Range of tm->tm_mon could be [0, 11]
|
||||
* But in this RTC, date.month should be [1, 12]
|
||||
*/
|
||||
if (rtc_in_range(tm->tm_mon, 0, 11))
|
||||
timer_date.month = tm->tm_mon + 1;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Range of tm->tm_year is the years since 1900
|
||||
* But in this RTC, year is split into year and century
|
||||
* In this RTC, century range is [0,31], year range is [0,99]
|
||||
*/
|
||||
int human_year = tm->tm_year + 1900;
|
||||
int rtc_year = human_year % 100;
|
||||
int rtc_century = human_year / 100;
|
||||
|
||||
if (rtc_in_range(rtc_year, 0, 99) &&
|
||||
rtc_in_range(rtc_century, 0, 31)) {
|
||||
timer_date.year = rtc_year;
|
||||
timer_extended.century = rtc_century;
|
||||
} else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_wday could be [0, 6] */
|
||||
if (rtc_in_range(tm->tm_wday, 0, 6))
|
||||
timer_date.week = tm->tm_wday;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Set RTC mode to timer setting mode */
|
||||
rtc_timer_set_mode(RTC_TIMER_SETTING);
|
||||
/* Write value to RTC */
|
||||
rtc->date = timer_date;
|
||||
rtc->time = timer_time;
|
||||
rtc->extended = timer_extended;
|
||||
/* Get CPU current freq */
|
||||
unsigned long freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
|
||||
/* Set threshold to 1/26000000 s */
|
||||
freq = freq / 26000000;
|
||||
/* Get current CPU cycle */
|
||||
unsigned long start_cycle = read_csr(mcycle);
|
||||
/* Wait for 1/26000000 s to sync data */
|
||||
while (read_csr(mcycle) - start_cycle < freq)
|
||||
continue;
|
||||
/* Set RTC mode to timer running mode */
|
||||
rtc_timer_set_mode(RTC_TIMER_RUNNING);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_timer_set_alarm_tm(const struct tm *tm)
|
||||
{
|
||||
struct rtc_alarm_date_t alarm_date;
|
||||
struct rtc_alarm_time_t alarm_time;
|
||||
|
||||
if (tm) {
|
||||
/*
|
||||
* Range of tm->tm_sec could be [0,61]
|
||||
*
|
||||
* Range of tm->tm_sec allows for a positive leap second. Two
|
||||
* leap seconds in the same minute are not allowed (the C90
|
||||
* range 0..61 was a defect)
|
||||
*/
|
||||
if (rtc_in_range(tm->tm_sec, 0, 59))
|
||||
alarm_time.second = tm->tm_sec;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_min could be [0,59] */
|
||||
if (rtc_in_range(tm->tm_min, 0, 59))
|
||||
alarm_time.minute = tm->tm_min;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_hour could be [0, 23] */
|
||||
if (rtc_in_range(tm->tm_hour, 0, 23))
|
||||
alarm_time.hour = tm->tm_hour;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_mday could be [1, 31] */
|
||||
if (rtc_in_range(tm->tm_mday, 1, 31))
|
||||
alarm_date.day = tm->tm_mday;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Range of tm->tm_mon could be [0, 11]
|
||||
* But in this RTC, date.month should be [1, 12]
|
||||
*/
|
||||
if (rtc_in_range(tm->tm_mon, 0, 11))
|
||||
alarm_date.month = tm->tm_mon + 1;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/*
|
||||
* Range of tm->tm_year is the years since 1900
|
||||
* But in this RTC, year is split into year and century
|
||||
* In this RTC, century range is [0,31], year range is [0,99]
|
||||
*/
|
||||
int human_year = tm->tm_year + 1900;
|
||||
int rtc_year = human_year % 100;
|
||||
int rtc_century = human_year / 100;
|
||||
|
||||
if (rtc_in_range(rtc_year, 0, 99) &&
|
||||
rtc_in_range(rtc_century, 0, 31)) {
|
||||
alarm_date.year = rtc_year;
|
||||
} else
|
||||
return -1;
|
||||
|
||||
/* Range of tm->tm_wday could be [0, 6] */
|
||||
if (rtc_in_range(tm->tm_wday, 0, 6))
|
||||
alarm_date.week = tm->tm_wday;
|
||||
else
|
||||
return -1;
|
||||
|
||||
/* Write value to RTC */
|
||||
rtc->alarm_date = alarm_date;
|
||||
rtc->alarm_time = alarm_time;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_year_is_leap(int year)
|
||||
{
|
||||
return (year % 4 == 0 && year % 100 != 0) || (year % 400 == 0);
|
||||
}
|
||||
|
||||
int rtc_get_yday(int year, int month, int day)
|
||||
{
|
||||
static const int days[2][13] = {
|
||||
{0, 0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334},
|
||||
{0, 0, 31, 60, 91, 121, 152, 182, 213, 244, 274, 305, 335}
|
||||
};
|
||||
int leap = rtc_year_is_leap(year);
|
||||
|
||||
return days[leap][month] + day;
|
||||
}
|
||||
|
||||
int rtc_get_wday(int year, int month, int day)
|
||||
{
|
||||
/* Magic method to get weekday */
|
||||
int weekday = (day += month < 3 ? year-- : year - 2, 23 * month / 9 + day + 4 + year / 4 - year / 100 + year / 400) % 7;
|
||||
return weekday;
|
||||
}
|
||||
|
||||
struct tm *rtc_timer_get_tm(void)
|
||||
{
|
||||
if (rtc_timer_get_mode() != RTC_TIMER_RUNNING)
|
||||
return NULL;
|
||||
|
||||
struct rtc_date_t timer_date = rtc->date;
|
||||
struct rtc_time_t timer_time = rtc->time;
|
||||
struct rtc_extended_t timer_extended = rtc->extended;
|
||||
|
||||
struct tm *tm = &rtc_date_time;
|
||||
|
||||
tm->tm_sec = timer_time.second % 60;
|
||||
tm->tm_min = timer_time.minute % 60;
|
||||
tm->tm_hour = timer_time.hour % 24;
|
||||
tm->tm_mday = timer_date.day % 31;
|
||||
tm->tm_mon = (timer_date.month % 12) - 1;
|
||||
tm->tm_year = (timer_date.year % 100) + (timer_extended.century * 100) - 1900;
|
||||
tm->tm_wday = timer_date.week;
|
||||
tm->tm_yday = rtc_get_yday(tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday);
|
||||
tm->tm_isdst = -1;
|
||||
|
||||
return tm;
|
||||
}
|
||||
|
||||
struct tm *rtc_timer_get_alarm_tm(void)
|
||||
{
|
||||
if (rtc_timer_get_mode() != RTC_TIMER_RUNNING)
|
||||
return NULL;
|
||||
|
||||
struct rtc_alarm_date_t alarm_date = rtc->alarm_date;
|
||||
struct rtc_alarm_time_t alarm_time = rtc->alarm_time;
|
||||
struct rtc_extended_t timer_extended = rtc->extended;
|
||||
|
||||
struct tm *tm = &rtc_date_time;
|
||||
|
||||
tm->tm_sec = alarm_time.second % 60;
|
||||
tm->tm_min = alarm_time.minute % 60;
|
||||
tm->tm_hour = alarm_time.hour % 24;
|
||||
tm->tm_mday = alarm_date.day % 31;
|
||||
tm->tm_mon = (alarm_date.month % 12) - 1;
|
||||
/* Alarm and Timer use same timer_extended.century */
|
||||
tm->tm_year = (alarm_date.year % 100) + (timer_extended.century * 100) - 1900;
|
||||
tm->tm_wday = alarm_date.week;
|
||||
tm->tm_yday = rtc_get_yday(tm->tm_year + 1900, tm->tm_mon + 1, tm->tm_mday);
|
||||
tm->tm_isdst = -1;
|
||||
|
||||
return tm;
|
||||
}
|
||||
|
||||
int rtc_timer_set(int year, int month, int day, int hour, int minute, int second)
|
||||
{
|
||||
struct tm date_time = {
|
||||
.tm_sec = second,
|
||||
.tm_min = minute,
|
||||
.tm_hour = hour,
|
||||
.tm_mday = day,
|
||||
.tm_mon = month - 1,
|
||||
.tm_year = year - 1900,
|
||||
.tm_wday = rtc_get_wday(year, month, day),
|
||||
.tm_yday = rtc_get_yday(year, month, day),
|
||||
.tm_isdst = -1,
|
||||
};
|
||||
|
||||
return rtc_timer_set_tm(&date_time);
|
||||
}
|
||||
|
||||
int rtc_timer_get(int *year, int *month, int *day, int *hour, int *minute, int *second)
|
||||
{
|
||||
struct tm *tm = rtc_timer_get_tm();
|
||||
|
||||
if (tm) {
|
||||
if (year)
|
||||
*year = tm->tm_year + 1900;
|
||||
if (month)
|
||||
*month = tm->tm_mon + 1;
|
||||
if (day)
|
||||
*day = tm->tm_mday;
|
||||
if (hour)
|
||||
*hour = tm->tm_hour;
|
||||
if (minute)
|
||||
*minute = tm->tm_min;
|
||||
if (second)
|
||||
*second = tm->tm_sec;
|
||||
} else
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_timer_set_alarm(int year, int month, int day, int hour, int minute, int second)
|
||||
{
|
||||
struct tm date_time = {
|
||||
.tm_sec = second,
|
||||
.tm_min = minute,
|
||||
.tm_hour = hour,
|
||||
.tm_mday = day,
|
||||
.tm_mon = month - 1,
|
||||
.tm_year = year - 1900,
|
||||
.tm_wday = rtc_get_wday(year, month, day),
|
||||
.tm_yday = rtc_get_yday(year, month, day),
|
||||
.tm_isdst = -1,
|
||||
};
|
||||
|
||||
return rtc_timer_set_alarm_tm(&date_time);
|
||||
}
|
||||
|
||||
int rtc_timer_get_alarm(int *year, int *month, int *day, int *hour, int *minute, int *second)
|
||||
{
|
||||
struct tm *tm = rtc_timer_get_alarm_tm();
|
||||
|
||||
if (tm) {
|
||||
if (year)
|
||||
*year = tm->tm_year + 1900;
|
||||
if (month)
|
||||
*month = tm->tm_mon + 1;
|
||||
if (day)
|
||||
*day = tm->tm_mday;
|
||||
if (hour)
|
||||
*hour = tm->tm_hour;
|
||||
if (minute)
|
||||
*minute = tm->tm_min;
|
||||
if (second)
|
||||
*second = tm->tm_sec;
|
||||
} else
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_timer_set_clock_frequency(unsigned int frequency)
|
||||
{
|
||||
struct rtc_initial_count_t initial_count;
|
||||
|
||||
initial_count.count = frequency;
|
||||
rtc->initial_count = initial_count;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int rtc_timer_get_clock_frequency(void)
|
||||
{
|
||||
return rtc->initial_count.count;
|
||||
}
|
||||
|
||||
int rtc_timer_set_clock_count_value(unsigned int count)
|
||||
{
|
||||
struct rtc_current_count_t current_count;
|
||||
|
||||
current_count.count = count;
|
||||
rtc->current_count = current_count;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int rtc_timer_get_clock_count_value(void)
|
||||
{
|
||||
return rtc->current_count.count;
|
||||
}
|
||||
|
||||
int rtc_tick_interrupt_set(int enable)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
interrupt_ctrl.tick_enable = enable;
|
||||
rtc->interrupt_ctrl = interrupt_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_tick_interrupt_get(void)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
return interrupt_ctrl.tick_enable;
|
||||
}
|
||||
|
||||
int rtc_tick_interrupt_mode_set(rtc_tick_interrupt_mode_e mode)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
interrupt_ctrl.tick_int_mode = mode;
|
||||
rtc->interrupt_ctrl = interrupt_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
rtc_tick_interrupt_mode_e rtc_tick_interrupt_mode_get(void)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
return interrupt_ctrl.tick_int_mode;
|
||||
}
|
||||
|
||||
int rtc_alarm_interrupt_set(int enable)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
interrupt_ctrl.alarm_enable = enable;
|
||||
rtc->interrupt_ctrl = interrupt_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_alarm_interrupt_get(void)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
return interrupt_ctrl.alarm_enable;
|
||||
}
|
||||
|
||||
int rtc_alarm_interrupt_mask_set(struct rtc_mask_t mask)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
interrupt_ctrl.alarm_compare_mask = *(uint8_t *)&mask;
|
||||
rtc->interrupt_ctrl = interrupt_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct rtc_mask_t rtc_alarm_interrupt_mask_get(void)
|
||||
{
|
||||
struct rtc_interrupt_ctrl_t interrupt_ctrl = rtc->interrupt_ctrl;
|
||||
|
||||
uint8_t compare_mask = interrupt_ctrl.alarm_compare_mask;
|
||||
|
||||
return *(struct rtc_mask_t *)&compare_mask;
|
||||
}
|
||||
|
||||
int rtc_protect_set(int enable)
|
||||
{
|
||||
struct rtc_register_ctrl_t register_ctrl = rtc->register_ctrl;
|
||||
|
||||
struct rtc_mask_t mask = {
|
||||
.second = 1,
|
||||
/* Second mask */
|
||||
.minute = 1,
|
||||
/* Minute mask */
|
||||
.hour = 1,
|
||||
/* Hour mask */
|
||||
.week = 1,
|
||||
/* Week mask */
|
||||
.day = 1,
|
||||
/* Day mask */
|
||||
.month = 1,
|
||||
/* Month mask */
|
||||
.year = 1,
|
||||
};
|
||||
|
||||
struct rtc_mask_t unmask = {
|
||||
.second = 0,
|
||||
/* Second mask */
|
||||
.minute = 0,
|
||||
/* Minute mask */
|
||||
.hour = 0,
|
||||
/* Hour mask */
|
||||
.week = 0,
|
||||
/* Week mask */
|
||||
.day = 0,
|
||||
/* Day mask */
|
||||
.month = 0,
|
||||
/* Month mask */
|
||||
.year = 0,
|
||||
};
|
||||
|
||||
if (enable) {
|
||||
/* Turn RTC in protect mode, no one can write time */
|
||||
register_ctrl.timer_mask = *(uint8_t *)&unmask;
|
||||
register_ctrl.alarm_mask = *(uint8_t *)&unmask;
|
||||
register_ctrl.initial_count_mask = 0;
|
||||
register_ctrl.interrupt_register_mask = 0;
|
||||
} else {
|
||||
/* Turn RTC in unprotect mode, everyone can write time */
|
||||
register_ctrl.timer_mask = *(uint8_t *)&mask;
|
||||
register_ctrl.alarm_mask = *(uint8_t *)&mask;
|
||||
register_ctrl.initial_count_mask = 1;
|
||||
register_ctrl.interrupt_register_mask = 1;
|
||||
}
|
||||
|
||||
rtc->register_ctrl = register_ctrl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int rtc_init(void)
|
||||
{
|
||||
/* Reset RTC */
|
||||
sysctl_reset(SYSCTL_RESET_RTC);
|
||||
/* Enable RTC */
|
||||
sysctl_clock_enable(SYSCTL_CLOCK_RTC);
|
||||
rtc_timer_set_mode(RTC_TIMER_SETTING);
|
||||
/* Unprotect RTC */
|
||||
rtc_protect_set(0);
|
||||
/* Set RTC clock frequency */
|
||||
rtc_timer_set_clock_frequency(
|
||||
sysctl_clock_source_get_freq(SYSCTL_SOURCE_IN0)
|
||||
);
|
||||
rtc_timer_set_clock_count_value(1);
|
||||
|
||||
/* Set RTC mode to timer running mode */
|
||||
rtc_timer_set_mode(RTC_TIMER_RUNNING);
|
||||
return 0;
|
||||
}
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,96 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include "uarths.h"
|
||||
#include "sysctl.h"
|
||||
#include "encoding.h"
|
||||
|
||||
volatile struct uarths_t *const uarths = (volatile struct uarths_t *)UARTHS_BASE_ADDR;
|
||||
|
||||
static inline int uart_putc(char c)
|
||||
{
|
||||
/* Read hart id */
|
||||
unsigned long hart_id = read_csr(mhartid);
|
||||
/* Set print data reg */
|
||||
volatile uint32_t *reg = (volatile uint32_t *)0x50440080UL;
|
||||
/* Push data out */
|
||||
if (hart_id == 0)
|
||||
{
|
||||
/* Select core 0 data reg */
|
||||
*reg = (0UL << 30) | c;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Select core 1 data reg */
|
||||
*reg = (1UL << 30) | c;
|
||||
}
|
||||
|
||||
/* Convert to DOS style (CRLF terminated) */
|
||||
if (c == '\n')
|
||||
{
|
||||
while (uarths->txdata.full)
|
||||
continue;
|
||||
uarths->txdata.data = '\r';
|
||||
}
|
||||
while (uarths->txdata.full)
|
||||
continue;
|
||||
uarths->txdata.data = c;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_getc(void)
|
||||
{
|
||||
/* while not empty */
|
||||
struct uarths_rxdata_t recv = uarths->rxdata;
|
||||
|
||||
if (recv.empty)
|
||||
return EOF;
|
||||
else
|
||||
return recv.data;
|
||||
}
|
||||
|
||||
int uart_putchar(char c)
|
||||
{
|
||||
return uart_putc(c);
|
||||
}
|
||||
|
||||
int uart_puts(const char *s)
|
||||
{
|
||||
while (*s)
|
||||
if (uart_putc(*s++) != 0)
|
||||
return -1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
int uart_init()
|
||||
{
|
||||
uint32_t freq = sysctl_clock_get_freq(SYSCTL_CLOCK_CPU);
|
||||
uint16_t div = freq / 115200 - 1;
|
||||
|
||||
/* Set UART registers */
|
||||
uarths->div.div = div;
|
||||
uarths->txctrl.txen = 1;
|
||||
uarths->rxctrl.rxen = 1;
|
||||
uarths->txctrl.txcnt = 0;
|
||||
uarths->rxctrl.rxcnt = 0;
|
||||
uarths->ip.txwm = 1;
|
||||
uarths->ip.rxwm = 1;
|
||||
uarths->ie.txwm = 0;
|
||||
uarths->ie.rxwm = 1;
|
||||
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,120 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include "wdt.h"
|
||||
#include "platform.h"
|
||||
#include "stddef.h"
|
||||
#include "common.h"
|
||||
#include "sysctl.h"
|
||||
#include "plic.h"
|
||||
|
||||
plic_irq_callback_t wdt_irq[2];
|
||||
|
||||
volatile struct wdt_t *const wdt[2] =
|
||||
{
|
||||
(volatile struct wdt_t *)WDT0_BASE_ADDR,
|
||||
(volatile struct wdt_t *)WDT1_BASE_ADDR
|
||||
};
|
||||
|
||||
void wdt_feed(uint8_t id)
|
||||
{
|
||||
wdt[id]->crr = WDT_CRR_MASK;
|
||||
}
|
||||
|
||||
void wdt_enable(uint8_t id)
|
||||
{
|
||||
wdt[id]->crr = WDT_CRR_MASK;
|
||||
wdt[id]->cr |= WDT_CR_ENABLE;
|
||||
}
|
||||
|
||||
void wdt_disable(uint8_t id)
|
||||
{
|
||||
wdt[id]->crr = WDT_CRR_MASK;
|
||||
wdt[id]->cr &= (~WDT_CR_ENABLE);
|
||||
}
|
||||
|
||||
void wdt_timeout_set(uint8_t id, uint8_t timeout)
|
||||
{
|
||||
wdt[id]->torr = WDT_TORR_TOP(timeout);
|
||||
}
|
||||
|
||||
void wdt_response_mode(uint8_t id, uint8_t mode)
|
||||
{
|
||||
wdt[id]->cr &= (~WDT_CR_RMOD_MASK);
|
||||
wdt[id]->cr |= mode;
|
||||
}
|
||||
|
||||
void wdt_interrupt_clear(uint8_t id)
|
||||
{
|
||||
wdt[id]->eoi = wdt[id]->eoi;
|
||||
}
|
||||
|
||||
void wdt_set_irq(uint8_t id, plic_irq_callback_t on_irq)
|
||||
{
|
||||
wdt_irq[id] = on_irq;
|
||||
}
|
||||
|
||||
size_t wdt_get_pclk(uint8_t id)
|
||||
{
|
||||
return id ? sysctl_clock_get_freq(SYSCTL_CLOCK_WDT1) : sysctl_clock_get_freq(SYSCTL_CLOCK_WDT0);
|
||||
}
|
||||
|
||||
ssize_t log_2(size_t x)
|
||||
{
|
||||
ssize_t i = 0;
|
||||
for (i = sizeof(size_t) * 8; i >= 0; i--)
|
||||
{
|
||||
if ((x >> i) & 0x1)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
return i;
|
||||
}
|
||||
|
||||
uint8_t wdt_get_top(uint8_t id, size_t timeout_ms)
|
||||
{
|
||||
size_t wdt_clk = wdt_get_pclk(id);
|
||||
size_t ret = (timeout_ms * wdt_clk / 1000) >> 16;
|
||||
if (ret)
|
||||
ret = log_2(ret);
|
||||
if (ret > 0xf)
|
||||
ret = 0xf;
|
||||
return (uint8_t)ret;
|
||||
}
|
||||
|
||||
|
||||
int wdt_start(uint8_t id, size_t toms)
|
||||
{
|
||||
wdt_disable(id);
|
||||
wdt_interrupt_clear(id);
|
||||
plic_irq_register(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, wdt_irq[id], NULL);
|
||||
plic_set_priority(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT, 1);
|
||||
plic_irq_enable(id ? IRQN_WDT1_INTERRUPT : IRQN_WDT0_INTERRUPT);
|
||||
|
||||
sysctl_reset(id ? SYSCTL_RESET_WDT1 : SYSCTL_RESET_WDT0);
|
||||
sysctl_clock_set_threshold(id ? SYSCTL_THRESHOLD_WDT1 : SYSCTL_THRESHOLD_WDT0, 0);
|
||||
sysctl_clock_enable(id ? SYSCTL_CLOCK_WDT1 : SYSCTL_CLOCK_WDT0);
|
||||
wdt_response_mode(id, WDT_CR_RMOD_INTERRUPT);
|
||||
uint8_t m_top = wdt_get_top(id, toms);
|
||||
wdt_timeout_set(id, m_top);
|
||||
wdt_enable(id);
|
||||
return 0;
|
||||
}
|
||||
|
||||
void wdt_stop(uint8_t id)
|
||||
{
|
||||
wdt_disable(id);
|
||||
}
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FREERTOS_CONFIG_H
|
||||
#define FREERTOS_CONFIG_H
|
||||
/*-----------------------------------------------------------
|
||||
* Application specific definitions.
|
||||
*
|
||||
* These definitions should be adjusted for your particular hardware and
|
||||
* application requirements.
|
||||
*
|
||||
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
|
||||
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
|
||||
*
|
||||
* See http://www.freertos.org/a00110.html.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* clock */
|
||||
#define configCPU_CLOCK_HZ ( ( unsigned long ) 160000000 )
|
||||
#define configTICK_CLOCK_HZ ( ( unsigned long ) 160000000 / 50 )
|
||||
#define configTICK_RATE_HZ ( ( TickType_t ) 100 )
|
||||
|
||||
/* multithreading */
|
||||
#define configUSE_NEWLIB_REENTRANT 1
|
||||
|
||||
#define configUSE_PREEMPTION 1
|
||||
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
|
||||
#define configMAX_PRIORITIES ( 5 )
|
||||
#define configMAX_TASK_NAME_LEN ( 16 )
|
||||
#define configUSE_TRACE_FACILITY 0
|
||||
#define configUSE_16_BIT_TICKS 0
|
||||
#define configIDLE_SHOULD_YIELD 0
|
||||
#define configQUEUE_REGISTRY_SIZE 8
|
||||
#define configCHECK_FOR_STACK_OVERFLOW 0
|
||||
|
||||
/* mutex */
|
||||
#define configUSE_MUTEXES 1
|
||||
#define configUSE_RECURSIVE_MUTEXES 1
|
||||
|
||||
/* hooks */
|
||||
#define configUSE_MALLOC_FAILED_HOOK 0
|
||||
#define configUSE_IDLE_HOOK 1
|
||||
#define configUSE_TICK_HOOK 0
|
||||
#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
|
||||
|
||||
/* memory */
|
||||
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 128 )
|
||||
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 1024 * 1024 ) )
|
||||
#define configSUPPORT_STATIC_ALLOCATION 0
|
||||
#define configSUPPORT_DYNAMIC_ALLOCATION 1
|
||||
|
||||
#define configUSE_APPLICATION_TASK_TAG 0
|
||||
#define configUSE_COUNTING_SEMAPHORES 1
|
||||
#define configUSE_TICKLESS_IDLE 1
|
||||
#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
|
||||
#define configGENERATE_RUN_TIME_STATS 0
|
||||
#define configUSE_STATS_FORMATTING_FUNCTIONS 1
|
||||
|
||||
/* Co-routine definitions. */
|
||||
#define configUSE_CO_ROUTINES 0
|
||||
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
|
||||
|
||||
/* Software timer definitions. */
|
||||
#define configUSE_TIMERS 0
|
||||
#define configTIMER_TASK_PRIORITY ( 2 )
|
||||
#define configTIMER_QUEUE_LENGTH 2
|
||||
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE )
|
||||
|
||||
/* Main task */
|
||||
#define configMAIN_TASK_PRIORITY 1
|
||||
#define configMAIN_TASK_STACK_SIZE 4096
|
||||
|
||||
/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */
|
||||
#define INCLUDE_vTaskPrioritySet 1
|
||||
#define INCLUDE_uxTaskPriorityGet 1
|
||||
#define INCLUDE_vTaskDelete 1
|
||||
#define INCLUDE_vTaskCleanUpResources 1
|
||||
#define INCLUDE_vTaskSuspend 1
|
||||
#define INCLUDE_vTaskDelayUntil 1
|
||||
#define INCLUDE_vTaskDelay 1
|
||||
#define INCLUDE_eTaskGetState 1
|
||||
#define INCLUDE_xTaskAbortDelay 1
|
||||
|
||||
/* configASSERT behaviour */
|
||||
extern void vPortFatal(const char* file, int line, const char* message);
|
||||
/* Normal assert() semantics without relying on the provision of an assert.h header file. */
|
||||
#define configASSERT( x ) if( ( x ) == 0 ) { \
|
||||
vPortFatal(__FILE__, __LINE__, #x); \
|
||||
}
|
||||
|
||||
#endif /* FREERTOS_CONFIG_H */
|
|
@ -0,0 +1,367 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "croutine.h"
|
||||
|
||||
/* Remove the whole file is co-routines are not being used. */
|
||||
#if( configUSE_CO_ROUTINES != 0 )
|
||||
|
||||
/*
|
||||
* Some kernel aware debuggers require data to be viewed to be global, rather
|
||||
* than file scope.
|
||||
*/
|
||||
#ifdef portREMOVE_STATIC_QUALIFIER
|
||||
#define static
|
||||
#endif
|
||||
|
||||
|
||||
/* Lists for ready and blocked co-routines. --------------------*/
|
||||
static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
|
||||
static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */
|
||||
static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
|
||||
static List_t * pxDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used. */
|
||||
static List_t * pxOverflowDelayedCoRoutineList; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
|
||||
static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
|
||||
|
||||
/* Other file private variables. --------------------------------*/
|
||||
CRCB_t * pxCurrentCoRoutine = NULL;
|
||||
static UBaseType_t uxTopCoRoutineReadyPriority = 0;
|
||||
static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
|
||||
|
||||
/* The initial state of the co-routine when it is created. */
|
||||
#define corINITIAL_STATE ( 0 )
|
||||
|
||||
/*
|
||||
* Place the co-routine represented by pxCRCB into the appropriate ready queue
|
||||
* for the priority. It is inserted at the end of the list.
|
||||
*
|
||||
* This macro accesses the co-routine ready lists and therefore must not be
|
||||
* used from within an ISR.
|
||||
*/
|
||||
#define prvAddCoRoutineToReadyQueue( pxCRCB ) \
|
||||
{ \
|
||||
if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \
|
||||
{ \
|
||||
uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \
|
||||
} \
|
||||
vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \
|
||||
}
|
||||
|
||||
/*
|
||||
* Utility to ready all the lists used by the scheduler. This is called
|
||||
* automatically upon the creation of the first co-routine.
|
||||
*/
|
||||
static void prvInitialiseCoRoutineLists( void );
|
||||
|
||||
/*
|
||||
* Co-routines that are readied by an interrupt cannot be placed directly into
|
||||
* the ready lists (there is no mutual exclusion). Instead they are placed in
|
||||
* in the pending ready list in order that they can later be moved to the ready
|
||||
* list by the co-routine scheduler.
|
||||
*/
|
||||
static void prvCheckPendingReadyList( void );
|
||||
|
||||
/*
|
||||
* Macro that looks at the list of co-routines that are currently delayed to
|
||||
* see if any require waking.
|
||||
*
|
||||
* Co-routines are stored in the queue in the order of their wake time -
|
||||
* meaning once one co-routine has been found whose timer has not expired
|
||||
* we need not look any further down the list.
|
||||
*/
|
||||
static void prvCheckDelayedList( void );
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
|
||||
{
|
||||
BaseType_t xReturn;
|
||||
CRCB_t *pxCoRoutine;
|
||||
|
||||
/* Allocate the memory that will store the co-routine control block. */
|
||||
pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
|
||||
if( pxCoRoutine )
|
||||
{
|
||||
/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
|
||||
be created and the co-routine data structures need initialising. */
|
||||
if( pxCurrentCoRoutine == NULL )
|
||||
{
|
||||
pxCurrentCoRoutine = pxCoRoutine;
|
||||
prvInitialiseCoRoutineLists();
|
||||
}
|
||||
|
||||
/* Check the priority is within limits. */
|
||||
if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
|
||||
{
|
||||
uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
|
||||
}
|
||||
|
||||
/* Fill out the co-routine control block from the function parameters. */
|
||||
pxCoRoutine->uxState = corINITIAL_STATE;
|
||||
pxCoRoutine->uxPriority = uxPriority;
|
||||
pxCoRoutine->uxIndex = uxIndex;
|
||||
pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
|
||||
|
||||
/* Initialise all the other co-routine control block parameters. */
|
||||
vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
|
||||
vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
|
||||
|
||||
/* Set the co-routine control block as a link back from the ListItem_t.
|
||||
This is so we can get back to the containing CRCB from a generic item
|
||||
in a list. */
|
||||
listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
|
||||
listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
|
||||
|
||||
/* Event lists are always in priority order. */
|
||||
listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
|
||||
|
||||
/* Now the co-routine has been initialised it can be added to the ready
|
||||
list at the correct priority. */
|
||||
prvAddCoRoutineToReadyQueue( pxCoRoutine );
|
||||
|
||||
xReturn = pdPASS;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
|
||||
{
|
||||
TickType_t xTimeToWake;
|
||||
|
||||
/* Calculate the time to wake - this may overflow but this is
|
||||
not a problem. */
|
||||
xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
|
||||
|
||||
/* We must remove ourselves from the ready list before adding
|
||||
ourselves to the blocked list as the same list item is used for
|
||||
both lists. */
|
||||
( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||
|
||||
/* The list item will be inserted in wake time order. */
|
||||
listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
|
||||
|
||||
if( xTimeToWake < xCoRoutineTickCount )
|
||||
{
|
||||
/* Wake time has overflowed. Place this item in the
|
||||
overflow list. */
|
||||
vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The wake time has not overflowed, so we can use the
|
||||
current block list. */
|
||||
vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||
}
|
||||
|
||||
if( pxEventList )
|
||||
{
|
||||
/* Also add the co-routine to an event list. If this is done then the
|
||||
function must be called with interrupts disabled. */
|
||||
vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckPendingReadyList( void )
|
||||
{
|
||||
/* Are there any co-routines waiting to get moved to the ready list? These
|
||||
are co-routines that have been readied by an ISR. The ISR cannot access
|
||||
the ready lists itself. */
|
||||
while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
|
||||
{
|
||||
CRCB_t *pxUnblockedCRCB;
|
||||
|
||||
/* The pending ready list can be accessed by an ISR. */
|
||||
portDISABLE_INTERRUPTS();
|
||||
{
|
||||
pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
|
||||
( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
|
||||
}
|
||||
portENABLE_INTERRUPTS();
|
||||
|
||||
( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
|
||||
prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
|
||||
}
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvCheckDelayedList( void )
|
||||
{
|
||||
CRCB_t *pxCRCB;
|
||||
|
||||
xPassedTicks = xTaskGetTickCount() - xLastTickCount;
|
||||
while( xPassedTicks )
|
||||
{
|
||||
xCoRoutineTickCount++;
|
||||
xPassedTicks--;
|
||||
|
||||
/* If the tick count has overflowed we need to swap the ready lists. */
|
||||
if( xCoRoutineTickCount == 0 )
|
||||
{
|
||||
List_t * pxTemp;
|
||||
|
||||
/* Tick count has overflowed so we need to swap the delay lists. If there are
|
||||
any items in pxDelayedCoRoutineList here then there is an error! */
|
||||
pxTemp = pxDelayedCoRoutineList;
|
||||
pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
|
||||
pxOverflowDelayedCoRoutineList = pxTemp;
|
||||
}
|
||||
|
||||
/* See if this tick has made a timeout expire. */
|
||||
while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
|
||||
{
|
||||
pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
|
||||
|
||||
if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
|
||||
{
|
||||
/* Timeout not yet expired. */
|
||||
break;
|
||||
}
|
||||
|
||||
portDISABLE_INTERRUPTS();
|
||||
{
|
||||
/* The event could have occurred just before this critical
|
||||
section. If this is the case then the generic list item will
|
||||
have been moved to the pending ready list and the following
|
||||
line is still valid. Also the pvContainer parameter will have
|
||||
been set to NULL so the following lines are also valid. */
|
||||
( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
|
||||
|
||||
/* Is the co-routine waiting on an event also? */
|
||||
if( pxCRCB->xEventListItem.pvContainer )
|
||||
{
|
||||
( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
|
||||
}
|
||||
}
|
||||
portENABLE_INTERRUPTS();
|
||||
|
||||
prvAddCoRoutineToReadyQueue( pxCRCB );
|
||||
}
|
||||
}
|
||||
|
||||
xLastTickCount = xCoRoutineTickCount;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vCoRoutineSchedule( void )
|
||||
{
|
||||
/* See if any co-routines readied by events need moving to the ready lists. */
|
||||
prvCheckPendingReadyList();
|
||||
|
||||
/* See if any delayed co-routines have timed out. */
|
||||
prvCheckDelayedList();
|
||||
|
||||
/* Find the highest priority queue that contains ready co-routines. */
|
||||
while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
|
||||
{
|
||||
if( uxTopCoRoutineReadyPriority == 0 )
|
||||
{
|
||||
/* No more co-routines to check. */
|
||||
return;
|
||||
}
|
||||
--uxTopCoRoutineReadyPriority;
|
||||
}
|
||||
|
||||
/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
|
||||
of the same priority get an equal share of the processor time. */
|
||||
listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
|
||||
|
||||
/* Call the co-routine. */
|
||||
( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
|
||||
|
||||
return;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvInitialiseCoRoutineLists( void )
|
||||
{
|
||||
UBaseType_t uxPriority;
|
||||
|
||||
for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
|
||||
{
|
||||
vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
|
||||
}
|
||||
|
||||
vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
|
||||
vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
|
||||
vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
|
||||
|
||||
/* Start with pxDelayedCoRoutineList using list1 and the
|
||||
pxOverflowDelayedCoRoutineList using list2. */
|
||||
pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
|
||||
pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
|
||||
{
|
||||
CRCB_t *pxUnblockedCRCB;
|
||||
BaseType_t xReturn;
|
||||
|
||||
/* This function is called from within an interrupt. It can only access
|
||||
event lists and the pending ready list. This function assumes that a
|
||||
check has already been made to ensure pxEventList is not empty. */
|
||||
pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
|
||||
( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
|
||||
vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
|
||||
|
||||
if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
|
||||
{
|
||||
xReturn = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pdFALSE;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
#endif /* configUSE_CO_ROUTINES == 0 */
|
||||
|
|
@ -0,0 +1,729 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#include <FreeRTOS.h>
|
||||
#include <atomic.h>
|
||||
#include <semphr.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sysctl.h>
|
||||
#include <uarths.h>
|
||||
#include "devices.h"
|
||||
#include "driver.h"
|
||||
#include "hal.h"
|
||||
|
||||
#define MAX_HANDLES 256
|
||||
#define HANDLE_OFFSET 256
|
||||
#define MAX_CUSTOM_DRIVERS 32
|
||||
|
||||
#define DEFINE_INSTALL_DRIVER(type) \
|
||||
static void install_##type##_drivers() \
|
||||
{ \
|
||||
driver_registry_t* head = g_##type##_drivers; \
|
||||
while (head->name) \
|
||||
{ \
|
||||
const driver_base_t* driver = head->driver; \
|
||||
driver->install(driver->userdata); \
|
||||
head++; \
|
||||
} \
|
||||
}
|
||||
|
||||
typedef struct
|
||||
{
|
||||
driver_registry_t* driver_reg;
|
||||
} _file;
|
||||
|
||||
static _file* handles_[MAX_HANDLES] = {0};
|
||||
static driver_registry_t g_custom_drivers[MAX_CUSTOM_DRIVERS] = {0};
|
||||
|
||||
uintptr_t fft_file_;
|
||||
uintptr_t aes_file_;
|
||||
uintptr_t sha256_file_;
|
||||
|
||||
DEFINE_INSTALL_DRIVER(hal);
|
||||
DEFINE_INSTALL_DRIVER(dma);
|
||||
DEFINE_INSTALL_DRIVER(system);
|
||||
|
||||
driver_registry_t* find_free_driver(driver_registry_t* registry, const char* name)
|
||||
{
|
||||
driver_registry_t* head = registry;
|
||||
while (head->name)
|
||||
{
|
||||
if (strcmp(name, head->name) == 0)
|
||||
{
|
||||
driver_base_t* driver = (driver_base_t*)head->driver;
|
||||
if (driver->open(driver->userdata))
|
||||
return head;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
head++;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static driver_registry_t* install_custom_driver_core(const char* name, driver_type type, const void* driver)
|
||||
{
|
||||
size_t i = 0;
|
||||
driver_registry_t* head = g_custom_drivers;
|
||||
for (i = 0; i < MAX_CUSTOM_DRIVERS; i++, head++)
|
||||
{
|
||||
if (!head->name)
|
||||
{
|
||||
head->name = strdup(name);
|
||||
head->type = type;
|
||||
head->driver = driver;
|
||||
return head;
|
||||
}
|
||||
}
|
||||
|
||||
configASSERT(!"Max custom drivers exceeded.");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void install_drivers()
|
||||
{
|
||||
install_system_drivers();
|
||||
|
||||
fft_file_ = io_open("/dev/fft0");
|
||||
aes_file_ = io_open("/dev/aes0");
|
||||
sha256_file_ = io_open("/dev/sha256");
|
||||
}
|
||||
|
||||
static _file* io_alloc_file(driver_registry_t* driver_reg)
|
||||
{
|
||||
if (driver_reg)
|
||||
{
|
||||
_file* file = (_file*)malloc(sizeof(_file));
|
||||
if (!file)
|
||||
return NULL;
|
||||
file->driver_reg = driver_reg;
|
||||
return file;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static _file* io_open_reg(driver_registry_t* registry, const char* name, _file** file)
|
||||
{
|
||||
driver_registry_t* driver_reg = find_free_driver(registry, name);
|
||||
_file* ret = io_alloc_file(driver_reg);
|
||||
*file = ret;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Generic IO Implementation Helper Macros */
|
||||
|
||||
#define DEFINE_READ_PROXY(tl, tu) \
|
||||
if (rfile->driver_reg->type == DRIVER_##tu) \
|
||||
{ \
|
||||
const tl##_driver_t* tl = (const tl##_driver_t*)rfile->driver_reg->driver; \
|
||||
return tl->read(buffer, len, tl->base.userdata); \
|
||||
}
|
||||
|
||||
#define DEFINE_WRITE_PROXY(tl, tu) \
|
||||
if (rfile->driver_reg->type == DRIVER_##tu) \
|
||||
{ \
|
||||
const tl##_driver_t* tl = (const tl##_driver_t*)rfile->driver_reg->driver; \
|
||||
return tl->write(buffer, len, tl->base.userdata); \
|
||||
}
|
||||
|
||||
#define DEFINE_CONTROL_PROXY(tl, tu) \
|
||||
if (rfile->driver_reg->type == DRIVER_##tu) \
|
||||
{ \
|
||||
const tl##_driver_t* tl = (const tl##_driver_t*)rfile->driver_reg->driver; \
|
||||
return tl->io_control(control_code, write_buffer, write_len, read_buffer, read_len, tl->base.userdata); \
|
||||
}
|
||||
|
||||
static void dma_add_free();
|
||||
|
||||
int io_read(uintptr_t file, char* buffer, size_t len)
|
||||
{
|
||||
_file* rfile = (_file*)handles_[file - HANDLE_OFFSET];
|
||||
/* clang-format off */
|
||||
DEFINE_READ_PROXY(uart, UART)
|
||||
else DEFINE_READ_PROXY(i2c_device, I2C_DEVICE)
|
||||
else DEFINE_READ_PROXY(spi_device, SPI_DEVICE)
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
/* clang-format on */
|
||||
}
|
||||
|
||||
static void io_free(_file* file)
|
||||
{
|
||||
if (file)
|
||||
{
|
||||
if (file->driver_reg->type == DRIVER_DMA)
|
||||
dma_add_free();
|
||||
|
||||
driver_base_t* driver = (driver_base_t*)file->driver_reg->driver;
|
||||
driver->close(driver->userdata);
|
||||
|
||||
free(file);
|
||||
}
|
||||
}
|
||||
|
||||
static uintptr_t io_alloc_handle(_file* file)
|
||||
{
|
||||
if (file)
|
||||
{
|
||||
size_t i, j;
|
||||
for (i = 0; i < 2; i++)
|
||||
{
|
||||
for (j = 0; j < MAX_HANDLES; j++)
|
||||
{
|
||||
if (atomic_cas(handles_ + j, 0, file) == 0)
|
||||
return j + HANDLE_OFFSET;
|
||||
}
|
||||
}
|
||||
|
||||
io_free(file);
|
||||
return 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
uintptr_t io_open(const char* name)
|
||||
{
|
||||
_file* file = 0;
|
||||
if (io_open_reg(g_system_drivers, name, &file))
|
||||
{
|
||||
}
|
||||
else if (io_open_reg(g_hal_drivers, name, &file))
|
||||
{
|
||||
}
|
||||
|
||||
if (file)
|
||||
return io_alloc_handle(file);
|
||||
configASSERT(file);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int io_close(uintptr_t file)
|
||||
{
|
||||
if (file)
|
||||
{
|
||||
_file* rfile = (_file*)handles_[file - HANDLE_OFFSET];
|
||||
io_free(rfile);
|
||||
atomic_set(handles_ + file - HANDLE_OFFSET, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int io_write(uintptr_t file, const char* buffer, size_t len)
|
||||
{
|
||||
_file* rfile = (_file*)handles_[file - HANDLE_OFFSET];
|
||||
/* clang-format off */
|
||||
DEFINE_WRITE_PROXY(uart, UART)
|
||||
else DEFINE_WRITE_PROXY(i2c_device, I2C_DEVICE)
|
||||
else DEFINE_WRITE_PROXY(spi_device, SPI_DEVICE)
|
||||
else
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
/* clang-format on */
|
||||
}
|
||||
|
||||
int io_control(uintptr_t file, size_t control_code, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len)
|
||||
{
|
||||
_file* rfile = (_file*)handles_[file - HANDLE_OFFSET];
|
||||
DEFINE_CONTROL_PROXY(custom, CUSTOM)
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Device IO Implementation Helper Macros */
|
||||
|
||||
#define COMMON_ENTRY(tl, tu) \
|
||||
_file* rfile = (_file*)handles_[file - HANDLE_OFFSET]; \
|
||||
configASSERT(rfile->driver_reg->type == DRIVER_##tu); \
|
||||
const tl##_driver_t* tl = (const tl##_driver_t*)rfile->driver_reg->driver;
|
||||
|
||||
#define COMMON_ENTRY_FILE(file, tl, tu) \
|
||||
_file* rfile = (_file*)handles_[file - HANDLE_OFFSET]; \
|
||||
configASSERT(rfile->driver_reg->type == DRIVER_##tu); \
|
||||
const tl##_driver_t* tl = (const tl##_driver_t*)rfile->driver_reg->driver;
|
||||
|
||||
/* UART */
|
||||
|
||||
void uart_config(uintptr_t file, size_t baud_rate, size_t data_width, uart_stopbit stopbit, uart_parity parity)
|
||||
{
|
||||
COMMON_ENTRY(uart, UART);
|
||||
uart->config(baud_rate, data_width, stopbit, parity, uart->base.userdata);
|
||||
}
|
||||
|
||||
/* GPIO */
|
||||
|
||||
size_t gpio_get_pin_count(uintptr_t file)
|
||||
{
|
||||
COMMON_ENTRY(gpio, GPIO);
|
||||
return gpio->pin_count;
|
||||
}
|
||||
|
||||
void gpio_set_drive_mode(uintptr_t file, size_t pin, gpio_drive_mode mode)
|
||||
{
|
||||
COMMON_ENTRY(gpio, GPIO);
|
||||
gpio->set_drive_mode(gpio->base.userdata, pin, mode);
|
||||
}
|
||||
|
||||
void gpio_set_pin_edge(uintptr_t file, size_t pin, gpio_pin_edge edge)
|
||||
{
|
||||
COMMON_ENTRY(gpio, GPIO);
|
||||
gpio->set_pin_edge(gpio->base.userdata, pin, edge);
|
||||
}
|
||||
|
||||
void gpio_set_onchanged(uintptr_t file, size_t pin, gpio_onchanged callback, void* userdata)
|
||||
{
|
||||
COMMON_ENTRY(gpio, GPIO);
|
||||
gpio->set_onchanged(gpio->base.userdata, pin, callback, userdata);
|
||||
}
|
||||
|
||||
gpio_pin_value gpio_get_pin_value(uintptr_t file, size_t pin)
|
||||
{
|
||||
COMMON_ENTRY(gpio, GPIO);
|
||||
return gpio->get_pin_value(gpio->base.userdata, pin);
|
||||
}
|
||||
|
||||
void gpio_set_pin_value(uintptr_t file, size_t pin, gpio_pin_value value)
|
||||
{
|
||||
COMMON_ENTRY(gpio, GPIO);
|
||||
gpio->set_pin_value(gpio->base.userdata, pin, value);
|
||||
}
|
||||
|
||||
/* I2C */
|
||||
|
||||
uintptr_t i2c_get_device(uintptr_t file, const char* name, size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode)
|
||||
{
|
||||
COMMON_ENTRY(i2c, I2C);
|
||||
i2c_device_driver_t* driver = i2c->get_device(slave_address, address_width, bus_speed_mode, i2c->base.userdata);
|
||||
driver_registry_t* reg = install_custom_driver_core(name, DRIVER_I2C_DEVICE, driver);
|
||||
return io_alloc_handle(io_alloc_file(reg));
|
||||
}
|
||||
|
||||
int i2c_dev_transfer_sequential(uintptr_t file, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len)
|
||||
{
|
||||
COMMON_ENTRY(i2c_device, I2C_DEVICE);
|
||||
return i2c_device->transfer_sequential(write_buffer, write_len, read_buffer, read_len, i2c_device->base.userdata);
|
||||
}
|
||||
|
||||
void i2c_config_as_slave(uintptr_t file, size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, i2c_slave_handler* handler)
|
||||
{
|
||||
COMMON_ENTRY(i2c, I2C);
|
||||
i2c->config_as_slave(slave_address, address_width, bus_speed_mode, handler, i2c->base.userdata);
|
||||
}
|
||||
|
||||
/* I2S */
|
||||
|
||||
void i2s_config_as_render(uintptr_t file, const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask)
|
||||
{
|
||||
COMMON_ENTRY(i2s, I2S);
|
||||
i2s->config_as_render(format, delay_ms, align_mode, channels_mask, i2s->base.userdata);
|
||||
}
|
||||
|
||||
void i2s_config_as_capture(uintptr_t file, const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask)
|
||||
{
|
||||
COMMON_ENTRY(i2s, I2S);
|
||||
i2s->config_as_capture(format, delay_ms, align_mode, channels_mask, i2s->base.userdata);
|
||||
}
|
||||
|
||||
void i2s_get_buffer(uintptr_t file, char** buffer, size_t* frames)
|
||||
{
|
||||
COMMON_ENTRY(i2s, I2S);
|
||||
i2s->get_buffer(buffer, frames, i2s->base.userdata);
|
||||
}
|
||||
|
||||
void i2s_release_buffer(uintptr_t file, size_t frames)
|
||||
{
|
||||
COMMON_ENTRY(i2s, I2S);
|
||||
i2s->release_buffer(frames, i2s->base.userdata);
|
||||
}
|
||||
|
||||
void i2s_start(uintptr_t file)
|
||||
{
|
||||
COMMON_ENTRY(i2s, I2S);
|
||||
i2s->start(i2s->base.userdata);
|
||||
}
|
||||
|
||||
void i2s_stop(uintptr_t file)
|
||||
{
|
||||
COMMON_ENTRY(i2s, I2S);
|
||||
i2s->stop(i2s->base.userdata);
|
||||
}
|
||||
|
||||
/* SPI */
|
||||
|
||||
uintptr_t spi_get_device(uintptr_t file, const char* name, spi_mode mode, spi_frame_format frame_format, size_t chip_select_line, size_t data_bit_length)
|
||||
{
|
||||
COMMON_ENTRY(spi, SPI);
|
||||
spi_device_driver_t* driver = spi->get_device(mode, frame_format, chip_select_line, data_bit_length, spi->base.userdata);
|
||||
driver_registry_t* reg = install_custom_driver_core(name, DRIVER_SPI_DEVICE, driver);
|
||||
return io_alloc_handle(io_alloc_file(reg));
|
||||
}
|
||||
|
||||
void spi_dev_config(uintptr_t file, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode trans_mode)
|
||||
{
|
||||
COMMON_ENTRY(spi_device, SPI_DEVICE);
|
||||
spi_device->config(instruction_length, address_length, wait_cycles, trans_mode, spi_device->base.userdata);
|
||||
}
|
||||
|
||||
double spi_dev_set_speed(uintptr_t file, double speed)
|
||||
{
|
||||
COMMON_ENTRY(spi_device, SPI_DEVICE);
|
||||
return spi_device->set_speed(speed, spi_device->base.userdata);
|
||||
}
|
||||
|
||||
int spi_dev_transfer_full_duplex(uintptr_t file, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len)
|
||||
{
|
||||
COMMON_ENTRY(spi_device, SPI_DEVICE);
|
||||
return spi_device->transfer_full_duplex(write_buffer, write_len, read_buffer, read_len, spi_device->base.userdata);
|
||||
}
|
||||
|
||||
int spi_dev_transfer_sequential(uintptr_t file, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len)
|
||||
{
|
||||
COMMON_ENTRY(spi_device, SPI_DEVICE);
|
||||
return spi_device->transfer_sequential(write_buffer, write_len, read_buffer, read_len, spi_device->base.userdata);
|
||||
}
|
||||
|
||||
void spi_dev_fill(uintptr_t file, size_t instruction, size_t address, uint32_t value, size_t count)
|
||||
{
|
||||
COMMON_ENTRY(spi_device, SPI_DEVICE);
|
||||
return spi_device->fill(instruction, address, value, count, spi_device->base.userdata);
|
||||
}
|
||||
|
||||
/* DVP */
|
||||
|
||||
void dvp_config(uintptr_t file, size_t width, size_t height, int auto_enable)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->config(width, height, auto_enable, dvp->base.userdata);
|
||||
}
|
||||
|
||||
void dvp_enable_frame(uintptr_t file)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->enable_frame(dvp->base.userdata);
|
||||
}
|
||||
|
||||
size_t dvp_get_output_num(uintptr_t file)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
return dvp->output_num;
|
||||
}
|
||||
|
||||
void dvp_set_signal(uintptr_t file, dvp_signal_type type, int value)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->set_signal(type, value, dvp->base.userdata);
|
||||
}
|
||||
|
||||
void dvp_set_output_enable(uintptr_t file, size_t index, int enable)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->set_output_enable(index, enable, dvp->base.userdata);
|
||||
}
|
||||
|
||||
void dvp_set_output_attributes(uintptr_t file, size_t index, video_format format, void* output_buffer)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->set_output_attributes(index, format, output_buffer, dvp->base.userdata);
|
||||
}
|
||||
|
||||
void dvp_set_frame_event_enable(uintptr_t file, video_frame_event event, int enable)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->set_frame_event_enable(event, enable, dvp->base.userdata);
|
||||
}
|
||||
|
||||
void dvp_set_on_frame_event(uintptr_t file, dvp_on_frame_event callback, void* callback_data)
|
||||
{
|
||||
COMMON_ENTRY(dvp, DVP);
|
||||
dvp->set_on_frame_event(callback, callback_data, dvp->base.userdata);
|
||||
}
|
||||
|
||||
/* SSCB */
|
||||
|
||||
uintptr_t sccb_get_device(uintptr_t file, const char* name, size_t slave_address, size_t address_width)
|
||||
{
|
||||
COMMON_ENTRY(sccb, SCCB);
|
||||
sccb_device_driver_t* driver = sccb->get_device(slave_address, address_width, sccb->base.userdata);
|
||||
driver_registry_t* reg = install_custom_driver_core(name, DRIVER_SCCB_DEVICE, driver);
|
||||
return io_alloc_handle(io_alloc_file(reg));
|
||||
}
|
||||
|
||||
uint8_t sccb_dev_read_byte(uintptr_t file, uint16_t reg_address)
|
||||
{
|
||||
COMMON_ENTRY(sccb_device, SCCB_DEVICE);
|
||||
return sccb_device->read_byte(reg_address, sccb_device->base.userdata);
|
||||
}
|
||||
|
||||
void sccb_dev_write_byte(uintptr_t file, uint16_t reg_address, uint8_t value)
|
||||
{
|
||||
COMMON_ENTRY(sccb_device, SCCB_DEVICE);
|
||||
sccb_device->write_byte(reg_address, value, sccb_device->base.userdata);
|
||||
}
|
||||
|
||||
/* FFT */
|
||||
|
||||
void fft_complex_uint16(fft_point point, fft_direction direction, uint32_t shifts_mask, const uint16_t* input, uint16_t* output)
|
||||
{
|
||||
COMMON_ENTRY_FILE(fft_file_, fft, FFT);
|
||||
fft->complex_uint16(point, direction, shifts_mask, input, output, fft->base.userdata);
|
||||
}
|
||||
|
||||
/* AES */
|
||||
|
||||
void aes_decrypt(aes_parameter* aes_param)
|
||||
{
|
||||
COMMON_ENTRY_FILE(aes_file_, aes, AES);
|
||||
aes->decrypt(aes_param, aes->base.userdata);
|
||||
}
|
||||
void aes_encrypt(aes_parameter* aes_param)
|
||||
{
|
||||
COMMON_ENTRY_FILE(aes_file_, aes, AES);
|
||||
aes->encrypt(aes_param, aes->base.userdata);
|
||||
}
|
||||
|
||||
/* SHA */
|
||||
|
||||
void sha256_str(const char* str, size_t length, uint8_t* hash)
|
||||
{
|
||||
COMMON_ENTRY_FILE(sha256_file_, sha256, SHA256);
|
||||
sha256->sha_str(str, length, hash, sha256->base.userdata);
|
||||
}
|
||||
|
||||
/* TIMER */
|
||||
|
||||
size_t timer_set_interval(uintptr_t file, size_t nanoseconds)
|
||||
{
|
||||
COMMON_ENTRY(timer, TIMER);
|
||||
return timer->set_interval(nanoseconds, timer->base.userdata);
|
||||
}
|
||||
|
||||
void timer_set_ontick(uintptr_t file, timer_ontick ontick, void* ontick_data)
|
||||
{
|
||||
COMMON_ENTRY(timer, TIMER);
|
||||
timer->set_ontick(ontick, ontick_data, timer->base.userdata);
|
||||
}
|
||||
|
||||
void timer_set_enable(uintptr_t file, int enable)
|
||||
{
|
||||
COMMON_ENTRY(timer, TIMER);
|
||||
timer->set_enable(enable, timer->base.userdata);
|
||||
}
|
||||
|
||||
/* PWM */
|
||||
|
||||
size_t pwm_get_pin_count(uintptr_t file)
|
||||
{
|
||||
COMMON_ENTRY(pwm, PWM);
|
||||
return pwm->pin_count;
|
||||
}
|
||||
|
||||
double pwm_set_frequency(uintptr_t file, double frequency)
|
||||
{
|
||||
COMMON_ENTRY(pwm, PWM);
|
||||
return pwm->set_frequency(frequency, pwm->base.userdata);
|
||||
}
|
||||
|
||||
double pwm_set_active_duty_cycle_percentage(uintptr_t file, size_t pin, double duty_cycle_percentage)
|
||||
{
|
||||
COMMON_ENTRY(pwm, PWM);
|
||||
return pwm->set_active_duty_cycle_percentage(pin, duty_cycle_percentage, pwm->base.userdata);
|
||||
}
|
||||
|
||||
void pwm_set_enable(uintptr_t file, size_t pin, int enable)
|
||||
{
|
||||
COMMON_ENTRY(pwm, PWM);
|
||||
pwm->set_enable(pin, enable, pwm->base.userdata);
|
||||
}
|
||||
|
||||
/* RTC */
|
||||
|
||||
void rtc_get_datetime(uintptr_t file, datetime_t* datetime)
|
||||
{
|
||||
COMMON_ENTRY(rtc, RTC);
|
||||
rtc->get_datetime(datetime, rtc->base.userdata);
|
||||
}
|
||||
|
||||
void rtc_set_datetime(uintptr_t file, const datetime_t* datetime)
|
||||
{
|
||||
COMMON_ENTRY(rtc, RTC);
|
||||
rtc->set_datetime(datetime, rtc->base.userdata);
|
||||
}
|
||||
|
||||
/* HAL */
|
||||
|
||||
static uintptr_t pic_file_;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
pic_irq_handler pic_callbacks[MAX_IRQN];
|
||||
void* callback_userdata[MAX_IRQN];
|
||||
} pic_context_t;
|
||||
|
||||
static pic_context_t pic_context_;
|
||||
static SemaphoreHandle_t dma_free_;
|
||||
|
||||
static void init_dma_system()
|
||||
{
|
||||
size_t count = 0;
|
||||
driver_registry_t* head = g_dma_drivers;
|
||||
while (head->name)
|
||||
{
|
||||
count++;
|
||||
head++;
|
||||
}
|
||||
|
||||
dma_free_ = xSemaphoreCreateCounting(count, count);
|
||||
}
|
||||
|
||||
void install_hal()
|
||||
{
|
||||
install_hal_drivers();
|
||||
pic_file_ = io_open("/dev/pic0");
|
||||
configASSERT(pic_file_);
|
||||
|
||||
install_dma_drivers();
|
||||
init_dma_system();
|
||||
}
|
||||
|
||||
/* PIC */
|
||||
|
||||
void pic_set_irq_enable(size_t irq, int enable)
|
||||
{
|
||||
COMMON_ENTRY_FILE(pic_file_, pic, PIC);
|
||||
pic->set_irq_enable(irq, enable, pic->base.userdata);
|
||||
}
|
||||
|
||||
void pic_set_irq_priority(size_t irq, size_t priority)
|
||||
{
|
||||
COMMON_ENTRY_FILE(pic_file_, pic, PIC);
|
||||
pic->set_irq_priority(irq, priority, pic->base.userdata);
|
||||
}
|
||||
|
||||
void pic_set_irq_handler(size_t irq, pic_irq_handler handler, void* userdata)
|
||||
{
|
||||
atomic_set(pic_context_.callback_userdata + irq, userdata);
|
||||
pic_context_.pic_callbacks[irq] = handler;
|
||||
}
|
||||
|
||||
void kernel_iface_pic_on_irq(size_t irq)
|
||||
{
|
||||
pic_irq_handler handler = pic_context_.pic_callbacks[irq];
|
||||
if (handler)
|
||||
handler(pic_context_.callback_userdata[irq]);
|
||||
}
|
||||
|
||||
/* DMA */
|
||||
|
||||
uintptr_t dma_open_free()
|
||||
{
|
||||
configASSERT(xSemaphoreTake(dma_free_, portMAX_DELAY) == pdTRUE);
|
||||
|
||||
driver_registry_t *head = g_dma_drivers, *driver_reg = NULL;
|
||||
while (head->name)
|
||||
{
|
||||
driver_base_t* driver = (driver_base_t*)head->driver;
|
||||
if (driver->open(driver->userdata))
|
||||
{
|
||||
driver_reg = head;
|
||||
break;
|
||||
}
|
||||
|
||||
head++;
|
||||
}
|
||||
|
||||
configASSERT(driver_reg);
|
||||
uintptr_t handle = io_alloc_handle(io_alloc_file(driver_reg));
|
||||
return handle;
|
||||
}
|
||||
|
||||
void dma_close(uintptr_t file)
|
||||
{
|
||||
io_close(file);
|
||||
}
|
||||
|
||||
static void dma_add_free()
|
||||
{
|
||||
xSemaphoreGive(dma_free_);
|
||||
}
|
||||
|
||||
void dma_set_select_request(uintptr_t file, uint32_t request)
|
||||
{
|
||||
COMMON_ENTRY(dma, DMA);
|
||||
dma->set_select_request(request, dma->base.userdata);
|
||||
}
|
||||
|
||||
void dma_transmit_async(uintptr_t file, const volatile void* src, volatile void* dest, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, SemaphoreHandle_t completion_event)
|
||||
{
|
||||
COMMON_ENTRY(dma, DMA);
|
||||
dma->transmit_async(src, dest, src_inc, dest_inc, element_size, count, burst_size, completion_event, dma->base.userdata);
|
||||
}
|
||||
|
||||
void dma_transmit(uintptr_t file, const volatile void* src, volatile void* dest, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size)
|
||||
{
|
||||
SemaphoreHandle_t event = xSemaphoreCreateBinary();
|
||||
dma_transmit_async(file, src, dest, src_inc, dest_inc, element_size, count, burst_size, event);
|
||||
// printf("event: %p\n", event);
|
||||
configASSERT(xSemaphoreTake(event, portMAX_DELAY) == pdTRUE);
|
||||
vSemaphoreDelete(event);
|
||||
}
|
||||
|
||||
void dma_loop_async(uintptr_t file, const volatile void** srcs, size_t src_num, volatile void** dests, size_t dest_num, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, dma_stage_completion_handler stage_completion_handler, void* stage_completion_handler_data, SemaphoreHandle_t completion_event, int* stop_signal)
|
||||
{
|
||||
COMMON_ENTRY(dma, DMA);
|
||||
dma->loop_async(srcs, src_num, dests, dest_num, src_inc, dest_inc, element_size, count, burst_size, stage_completion_handler, stage_completion_handler_data, completion_event, stop_signal, dma->base.userdata);
|
||||
}
|
||||
|
||||
/* Custom Driver */
|
||||
|
||||
void install_custom_driver(const char* name, const custom_driver_t* driver)
|
||||
{
|
||||
install_custom_driver_core(name, DRIVER_CUSTOM, driver);
|
||||
}
|
||||
|
||||
/* System */
|
||||
|
||||
uint32_t system_set_cpu_frequency(uint32_t frequency)
|
||||
{
|
||||
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_IN0);
|
||||
sysctl->pll0.pll_reset0 = 1;
|
||||
|
||||
uint32_t result = sysctl_pll_set_freq(SYSCTL_PLL0, SYSCTL_SOURCE_IN0, frequency * 2);
|
||||
sysctl->pll0.pll_reset0 = 0;
|
||||
while (1)
|
||||
{
|
||||
uint32_t lock = sysctl->pll_lock.pll_lock0 & 0x3;
|
||||
if (lock == 0x3)
|
||||
{
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
sysctl->pll_lock.pll_slip_clear0 = 1;
|
||||
}
|
||||
}
|
||||
|
||||
sysctl->pll0.pll_out_en0 = 1;
|
||||
sysctl_clock_set_clock_select(SYSCTL_CLOCK_SELECT_ACLK, SYSCTL_SOURCE_PLL0);
|
||||
uart_init();
|
||||
return result;
|
||||
}
|
|
@ -0,0 +1,565 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _FREERTOS_DEVICES_H
|
||||
#define _FREERTOS_DEVICES_H
|
||||
|
||||
#include <driver.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Install all drivers
|
||||
*/
|
||||
void install_drivers();
|
||||
|
||||
/**
|
||||
* @brief Open a device
|
||||
*
|
||||
* @param[in] name The device path
|
||||
*
|
||||
* @return result
|
||||
- 0 Fail
|
||||
- other The device handle
|
||||
*/
|
||||
uintptr_t io_open(const char* name);
|
||||
|
||||
/**
|
||||
* @brief Close a device
|
||||
*
|
||||
* @param[in] file The device handle
|
||||
*
|
||||
* @return result
|
||||
* - 0 Success
|
||||
* - other Fail
|
||||
*/
|
||||
int io_close(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Read from a device
|
||||
*
|
||||
* @param[in[ file The device handle
|
||||
* @param[out] buffer The destination buffer
|
||||
* @param[in] len Maximum bytes to read
|
||||
*
|
||||
* @return Actual bytes read
|
||||
*/
|
||||
int io_read(uintptr_t file, char* buffer, size_t len);
|
||||
|
||||
/**
|
||||
* @brief Write to a device
|
||||
*
|
||||
* @param[in] file The device handle
|
||||
* @param[in] buffer The source buffer
|
||||
* @param[in] len Bytes to write
|
||||
*
|
||||
* @return result
|
||||
* - len Success
|
||||
* - other Fail
|
||||
*/
|
||||
int io_write(uintptr_t file, const char* buffer, size_t len);
|
||||
|
||||
/**
|
||||
* @brief Send control info to a device
|
||||
*
|
||||
* @param[in] file The device handle
|
||||
* @param[in] control_code The control code
|
||||
* @param[in] write_buffer The source buffer
|
||||
* @param[in] write_len Bytes to write
|
||||
* @param[in] read_buffer The destination buffer
|
||||
* @param[in] read_len Maximum bytes to read
|
||||
*
|
||||
* @return Actual bytes read
|
||||
*/
|
||||
int io_control(uintptr_t file, size_t control_code, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len);
|
||||
|
||||
/**
|
||||
* @brief Configure a UART device
|
||||
*
|
||||
* @param[in] file The UART handle
|
||||
* @param[in] baud_rate The baud rate
|
||||
* @param[in] data_width The databits width
|
||||
* @param[in] stopbit The stopbit selection
|
||||
* @param[in] parity The parity selection
|
||||
*/
|
||||
void uart_config(uintptr_t file, size_t baud_rate, size_t data_width, uart_stopbit stopbit, uart_parity parity);
|
||||
|
||||
/**
|
||||
* @brief Get the pin count of a GPIO controller
|
||||
*
|
||||
* @param[in] file The GPIO controller handle
|
||||
*
|
||||
* @return The pin count
|
||||
*/
|
||||
size_t gpio_get_pin_count(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Set the drive mode of a GPIO pin
|
||||
*
|
||||
* @param[in] file The GPIO controller handle
|
||||
* @param[in] pin The GPIO pin
|
||||
* @param[in] stopbit The drive mode selection
|
||||
*/
|
||||
void gpio_set_drive_mode(uintptr_t file, size_t pin, gpio_drive_mode mode);
|
||||
|
||||
/**
|
||||
* @brief Set the edge trigger mode of a GPIO pin
|
||||
*
|
||||
* @param[in] file The GPIO controller handle
|
||||
* @param[in] pin The GPIO pin
|
||||
* @param[in] stopbit The edge trigger mode selection
|
||||
*/
|
||||
void gpio_set_pin_edge(uintptr_t file, size_t pin, gpio_pin_edge edge);
|
||||
|
||||
/**
|
||||
* @brief Set the changed handler of a GPIO pin
|
||||
*
|
||||
* @param[in] file The GPIO controller handle
|
||||
* @param[in] pin The GPIO pin
|
||||
* @param[in] callback The changed handler
|
||||
* @param[in] userdata The userdata of the handler
|
||||
*/
|
||||
void gpio_set_onchanged(uintptr_t file, size_t pin, gpio_onchanged callback, void* userdata);
|
||||
|
||||
/**
|
||||
* @brief Get the value of a GPIO pin
|
||||
*
|
||||
* @param[in] file The GPIO controller handle
|
||||
* @param[in] pin The GPIO pin
|
||||
*
|
||||
* @return The value of the pin
|
||||
*/
|
||||
gpio_pin_value gpio_get_pin_value(uintptr_t file, size_t pin);
|
||||
|
||||
/**
|
||||
* @brief Set the value of a GPIO pin
|
||||
*
|
||||
* @param[in] file The GPIO controller handle
|
||||
* @param[in] pin The GPIO pin
|
||||
* @param[in] value The value to be set
|
||||
*/
|
||||
void gpio_set_pin_value(uintptr_t file, size_t pin, gpio_pin_value value);
|
||||
|
||||
/**
|
||||
* @brief Register and open a I2C device
|
||||
*
|
||||
* @param[in] file The I2C controller handle
|
||||
* @param[in] name Specify the path to access the device
|
||||
* @param[in] slave_address The address of slave
|
||||
* @param[in] address_width The bits width of address
|
||||
* @param[in] bus_speed_mode The bus speed mode selection
|
||||
*
|
||||
* @return The I2C device handle
|
||||
*/
|
||||
uintptr_t i2c_get_device(uintptr_t file, const char* name, size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode);
|
||||
|
||||
/**
|
||||
* @brief Write to then read from a I2C device
|
||||
*
|
||||
* @param[in] file The I2C device handle
|
||||
* @param[in] write_buffer The source buffer
|
||||
* @param[in] write_len Bytes to write
|
||||
* @param[in] read_buffer The destination buffer
|
||||
* @param[in] read_len Maximum bytes to read
|
||||
*
|
||||
* @return Actual bytes read
|
||||
*/
|
||||
int i2c_dev_transfer_sequential(uintptr_t file, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len);
|
||||
|
||||
/**
|
||||
* @brief Configure a I2C controller with slave mode
|
||||
*
|
||||
* @param[in] file The I2C controller handle
|
||||
* @param[in] slave_address The address of slave
|
||||
* @param[in] address_width The bits width of address
|
||||
* @param[in] bus_speed_mode The bus speed mode selection
|
||||
* @param[in] handler The slave handler
|
||||
*/
|
||||
void i2c_config_as_slave(uintptr_t file, size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, i2c_slave_handler* handler);
|
||||
|
||||
/**
|
||||
* @brief Configure a I2S controller with render mode
|
||||
*
|
||||
* @param[in] file The I2S controller handle
|
||||
* @param[in] format The audio format
|
||||
* @param[in] delay_ms The buffer length in milliseconds
|
||||
* @param[in] align_mode The I2S align mode selection
|
||||
* @param[in] channels_mask The channels selection mask
|
||||
*/
|
||||
void i2s_config_as_render(uintptr_t file, const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask);
|
||||
|
||||
/**
|
||||
* @brief Configure a I2S controller with render mode
|
||||
*
|
||||
* @param[in] file The I2S controller handle
|
||||
* @param[in] format The audio format
|
||||
* @param[in] delay_ms The buffer length in milliseconds
|
||||
* @param[in] align_mode The I2S align mode selection
|
||||
* @param[in] channels_mask The channels selection mask
|
||||
*/
|
||||
void i2s_config_as_capture(uintptr_t file, const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask);
|
||||
|
||||
/**
|
||||
* @brief Get the audio buffer of a I2S controller
|
||||
*
|
||||
* @param[in] file The I2S controller handle
|
||||
* @param[out] buffer The address of audio buffer
|
||||
* @param[out] frames The available frames count in buffer
|
||||
*/
|
||||
void i2s_get_buffer(uintptr_t file, char** buffer, size_t* frames);
|
||||
|
||||
/**
|
||||
* @brief Release the audio buffer of a I2S controller
|
||||
*
|
||||
* @param[in] file The I2S controller handle
|
||||
* @param[out] frames The frames have been confirmed read or written
|
||||
*/
|
||||
void i2s_release_buffer(uintptr_t file, size_t frames);
|
||||
|
||||
/**
|
||||
* @brief Start rendering or recording of a I2S controller
|
||||
*
|
||||
* @param[in] file The I2S controller handle
|
||||
*/
|
||||
void i2s_start(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Stop rendering or recording of a I2S controller
|
||||
*
|
||||
* @param[in] file The I2S controller handle
|
||||
*/
|
||||
void i2s_stop(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Register and open a SPI device
|
||||
*
|
||||
* @param[in] file The SPI controller handle
|
||||
* @param[in] name Specify the path to access the device
|
||||
* @param[in] mode The SPI mode selection
|
||||
* @param[in] frame_format The SPI frame format selection
|
||||
* @param[in] chip_select_line The CS mask
|
||||
* @param[in] data_bit_length The length of data bits
|
||||
*
|
||||
* @return The SPI device handle
|
||||
*/
|
||||
uintptr_t spi_get_device(uintptr_t file, const char* name, spi_mode mode, spi_frame_format frame_format, size_t chip_select_line, size_t data_bit_length);
|
||||
|
||||
/**
|
||||
* @brief Configure a SPI device with non-standard mode
|
||||
*
|
||||
* @param[in] file The SPI device handle
|
||||
* @param[in] instruction_length The length of instruction
|
||||
* @param[in] address_length The length of address
|
||||
* @param[in] wait_cycles The wait cycles
|
||||
* @param[in] spi_addr_inst_trans_mode The transmition mode of address and instruction
|
||||
*/
|
||||
void spi_dev_config(uintptr_t file, size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode trans_mode);
|
||||
|
||||
/**
|
||||
* @brief Set the speed of a SPI device
|
||||
*
|
||||
* @param[in] file The SPI device handle
|
||||
* @param[in] speed The desired speed in Hz
|
||||
*
|
||||
* @return The actual speed after set
|
||||
*/
|
||||
double spi_dev_set_speed(uintptr_t file, double speed);
|
||||
|
||||
/**
|
||||
* @brief Transfer data between a SPI device using full duplex
|
||||
*
|
||||
* @param[in] file The SPI device handle
|
||||
* @param[in] write_buffer The source buffer
|
||||
* @param[in] write_len Bytes to write
|
||||
* @param[in] read_buffer The destination buffer
|
||||
* @param[in] read_len Maximum bytes to read
|
||||
*
|
||||
* @return Actual bytes read
|
||||
*/
|
||||
int spi_dev_transfer_full_duplex(uintptr_t file, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len);
|
||||
|
||||
/**
|
||||
* @brief Write to then read from a SPI device
|
||||
*
|
||||
* @param[in] file The SPI device handle
|
||||
* @param[in] write_buffer The source buffer
|
||||
* @param[in] write_len Bytes to write
|
||||
* @param[in] read_buffer The destination buffer
|
||||
* @param[in] read_len Maximum bytes to read
|
||||
*
|
||||
* @return Actual bytes read
|
||||
*/
|
||||
int spi_dev_transfer_sequential(uintptr_t file, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len);
|
||||
|
||||
/**
|
||||
* @brief Fill a sequence of idential frame to a SPI device
|
||||
*
|
||||
* @param[in] file The SPI device handle
|
||||
* @param[in] instruction The instruction
|
||||
* @param[in] file The SPI device handle
|
||||
* @param[in] address The address
|
||||
* @param[in] value The value
|
||||
* @param[in] count THe count of frames
|
||||
*/
|
||||
void spi_dev_fill(uintptr_t file, size_t instruction, size_t address, uint32_t value, size_t count);
|
||||
|
||||
/**
|
||||
* @brief Configure a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
* @param[in] width The frame width
|
||||
* @param[in] height The frame height
|
||||
* @param[in] auto_enable Process frames automatically
|
||||
*/
|
||||
void dvp_config(uintptr_t file, size_t width, size_t height, int auto_enable);
|
||||
|
||||
/**
|
||||
* @brief Enable to process of current frame
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
*/
|
||||
void dvp_enable_frame(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Get the count of outputs of a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
*
|
||||
* @return The count of outputs
|
||||
*/
|
||||
size_t dvp_get_output_num(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Set or unset a signal to a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
* @param[in] type The signal type
|
||||
* @param[in] value 1 is set, 0 is unset
|
||||
*/
|
||||
void dvp_set_signal(uintptr_t file, dvp_signal_type type, int value);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable a output of a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
* @param[in] index The output index
|
||||
* @param[in] enable 1 is enable, 0 is disable
|
||||
*/
|
||||
void dvp_set_output_enable(uintptr_t file, size_t index, int enable);
|
||||
|
||||
/**
|
||||
* @brief Set output attributes of a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
* @param[in] index The output index
|
||||
* @param[in] format The output format
|
||||
* @param[out] output_buffer The output buffer
|
||||
*/
|
||||
void dvp_set_output_attributes(uintptr_t file, size_t index, video_format format, void* output_buffer);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable a frame event of a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
* @param[in] event The frame event
|
||||
* @param[in] enable 1 is enable, 0 is disable
|
||||
*/
|
||||
void dvp_set_frame_event_enable(uintptr_t file, video_frame_event event, int enable);
|
||||
|
||||
/**
|
||||
* @brief Set the frame event handler of a DVP device
|
||||
*
|
||||
* @param[in] file The DVP device handle
|
||||
* @param[in] callback The event handler
|
||||
* @param[in] callback_data The userdata of the event handler
|
||||
*/
|
||||
void dvp_set_on_frame_event(uintptr_t file, dvp_on_frame_event callback, void* callback_data);
|
||||
|
||||
/**
|
||||
* @brief Register and open a SCCB device
|
||||
*
|
||||
* @param[in] file The SCCB controller handle
|
||||
* @param[in] name Specify the path to access the device
|
||||
* @param[in] slave_address The address of slave
|
||||
* @param[in] address_width The bits width of address
|
||||
*
|
||||
* @return The SCCB device handle
|
||||
*/
|
||||
uintptr_t sccb_get_device(uintptr_t file, const char* name, size_t slave_address, size_t address_width);
|
||||
|
||||
/**
|
||||
* @brief Read a byte from a SCCB device
|
||||
*
|
||||
* @param[in] file The SCCB controller handle
|
||||
* @param[in] reg_address The register address
|
||||
*
|
||||
* @return The byte read
|
||||
*/
|
||||
uint8_t sccb_dev_read_byte(uintptr_t file, uint16_t reg_address);
|
||||
|
||||
/**
|
||||
* @brief Write a byte to a SCCB device
|
||||
*
|
||||
* @param[in] file The SCCB controller handle
|
||||
* @param[in] reg_address The register address
|
||||
* @param[in] value The data byte
|
||||
*/
|
||||
void sccb_dev_write_byte(uintptr_t file, uint16_t reg_address, uint8_t value);
|
||||
|
||||
/**
|
||||
* @brief Do 16bit quantized complex FFT
|
||||
*
|
||||
* @param[in] point The FFT points count
|
||||
* @param[in] direction The direction
|
||||
* @param[in] shifts_mask The shifts selection in 9 stage
|
||||
* @param[in] input The input data
|
||||
* @param[out] output The output data
|
||||
*/
|
||||
void fft_complex_uint16(fft_point point, fft_direction direction, uint32_t shifts_mask, const uint16_t* input, uint16_t* output);
|
||||
|
||||
/**
|
||||
* @brief Do aes decrypt
|
||||
*
|
||||
* @param[in] aes_in_data The aes input decrypt data
|
||||
* @param[in] key_addr The aes key address
|
||||
* @param[in] key_length The aes key length.16:AES_128 24:AES_192 32:AES_256
|
||||
* @param[in] gcm_iv The gcm iv address
|
||||
* @param[in] iv_length The gcm iv length
|
||||
* @param[in] aes_aad The gcm add address
|
||||
* @param[in] add_size The gcm add length
|
||||
* @param[in] cipher_mod The cipher mode. 00:AES_CIPHER_ECB 01:AES_CIPHER_CBC 10:AES_CIPHER_GCM
|
||||
* @param[in] data_size The input data size
|
||||
* @param[out] aes_out_data The output data
|
||||
* @param[out] tag The gcm output tag
|
||||
*/
|
||||
void aes_decrypt(aes_parameter* aes_param);
|
||||
|
||||
/**
|
||||
* @brief Do aes encrypt
|
||||
*
|
||||
* @param[in] aes_in_data The aes input decrypt data
|
||||
* @param[in] key_addr The aes key address
|
||||
* @param[in] key_length The aes key length.16:AES_128 24:AES_192 32:AES_256
|
||||
* @param[in] gcm_iv The gcm iv address
|
||||
* @param[in] iv_length The gcm iv length
|
||||
* @param[in] aes_aad The gcm add address
|
||||
* @param[in] add_size The gcm add length
|
||||
* @param[in] cipher_mod The cipher mode. 00:AES_CIPHER_ECB 01:AES_CIPHER_CBC 10:AES_CIPHER_GCM
|
||||
* @param[in] data_size The input data size
|
||||
* @param[out] aes_out_data The output data
|
||||
* @param[out] tag The output tag
|
||||
*/
|
||||
void aes_encrypt(aes_parameter* aes_param);
|
||||
|
||||
/**
|
||||
* @brief Do sha256
|
||||
*
|
||||
* @param[in] str The sha256 string
|
||||
* @param[in] length The string length
|
||||
* @param[out] hash The sha256 result
|
||||
*/
|
||||
void sha256_str(const char* str, size_t length, uint8_t* hash);
|
||||
|
||||
/**
|
||||
* @brief Set the interval of a TIMER device
|
||||
*
|
||||
* @param[in] file The TIMER controller handle
|
||||
* @param[in] nanoseconds The desired interval in nanoseconds
|
||||
*
|
||||
* @return The actual interval
|
||||
*/
|
||||
size_t timer_set_interval(uintptr_t file, size_t nanoseconds);
|
||||
|
||||
/**
|
||||
* @brief Set the tick handler of a TIMER device
|
||||
*
|
||||
* @param[in] file The TIMER controller handle
|
||||
* @param[in] ontick The tick handler
|
||||
* @param[in] ontick_data The userdata of the handler
|
||||
*/
|
||||
void timer_set_ontick(uintptr_t file, timer_ontick ontick, void* ontick_data);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable a TIMER device
|
||||
*
|
||||
* @param[in] file The TIMER controller handle
|
||||
* @param[in] enable 1 is enable, 0 is disable
|
||||
*/
|
||||
void timer_set_enable(uintptr_t file, int enable);
|
||||
|
||||
/**
|
||||
* @brief Get the pin count of a PWM controller
|
||||
*
|
||||
* @param[in] file The PWM controller handle
|
||||
*
|
||||
* @return The pin count
|
||||
*/
|
||||
size_t pwm_get_pin_count(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Set the frequency of a PWM controller
|
||||
*
|
||||
* @param[in] file The PWM controller handle
|
||||
* @param[in] frequency The desired frequency in Hz
|
||||
*
|
||||
* @return The actual frequency after set
|
||||
*/
|
||||
double pwm_set_frequency(uintptr_t file, double frequency);
|
||||
|
||||
/**
|
||||
* @brief Set the active duty cycle percentage of a PWM pin
|
||||
*
|
||||
* @param[in] file The PWM controller handle
|
||||
* @param[in] pin The PWM pin
|
||||
* @param[in] duty_cycle_percentage The desired active duty cycle percentage
|
||||
*
|
||||
* @return The actual active duty cycle percentage after set
|
||||
*/
|
||||
double pwm_set_active_duty_cycle_percentage(uintptr_t file, size_t pin, double duty_cycle_percentage);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable a PWM pin
|
||||
*
|
||||
* @param[in] file The PWM controller handle
|
||||
* @param[in] pin The PWM pin
|
||||
* @param[in] enable 1 is enable, 0 is disable
|
||||
*/
|
||||
void pwm_set_enable(uintptr_t file, size_t pin, int enable);
|
||||
|
||||
/**
|
||||
* @brief Get the datetime of a RTC device
|
||||
*
|
||||
* @param[in] file The RTC device
|
||||
* @param[out] datetime The datatime
|
||||
*/
|
||||
void rtc_get_datetime(uintptr_t file, datetime_t* datetime);
|
||||
|
||||
/**
|
||||
* @brief Set the datetime of a RTC device
|
||||
*
|
||||
* @param[in] file The RTC device
|
||||
* @param[out] datetime The datatime to be set
|
||||
*/
|
||||
void rtc_set_datetime(uintptr_t file, const datetime_t* datetime);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FREERTOS_DEVICES_H */
|
|
@ -0,0 +1,436 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _FREERTOS_DRIVER_H
|
||||
#define _FREERTOS_DRIVER_H
|
||||
|
||||
#include <FreeRTOS.h>
|
||||
#include <semphr.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
typedef struct tag_driver_base
|
||||
{
|
||||
void* userdata;
|
||||
void (*install)(void* userdata);
|
||||
int (*open)(void* userdata);
|
||||
void (*close)(void* userdata);
|
||||
} driver_base_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DRIVER_UART,
|
||||
DRIVER_GPIO,
|
||||
DRIVER_I2C,
|
||||
DRIVER_I2C_DEVICE,
|
||||
DRIVER_I2S,
|
||||
DRIVER_SPI,
|
||||
DRIVER_SPI_DEVICE,
|
||||
DRIVER_DVP,
|
||||
DRIVER_SCCB,
|
||||
DRIVER_SCCB_DEVICE,
|
||||
DRIVER_FFT,
|
||||
DRIVER_AES,
|
||||
DRIVER_SHA256,
|
||||
DRIVER_TIMER,
|
||||
DRIVER_PWM,
|
||||
DRIVER_RTC,
|
||||
DRIVER_PIC,
|
||||
DRIVER_DMAC,
|
||||
DRIVER_DMA,
|
||||
DRIVER_CUSTOM
|
||||
} driver_type;
|
||||
|
||||
typedef struct tag_driver_registry
|
||||
{
|
||||
const char* name;
|
||||
const void* driver;
|
||||
driver_type type;
|
||||
} driver_registry_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UART_STOP_1,
|
||||
UART_STOP_1_5,
|
||||
UART_STOP_2
|
||||
} uart_stopbit;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UART_PARITY_NONE,
|
||||
UART_PARITY_ODD,
|
||||
UART_PARITY_EVEN
|
||||
} uart_parity;
|
||||
|
||||
typedef struct tag_uart_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*config)(size_t baud_rate, size_t data_width, uart_stopbit stopbit, uart_parity parity, void* userdata);
|
||||
int (*read)(char* buffer, size_t len, void* userdata);
|
||||
int (*write)(const char* buffer, size_t len, void* userdata);
|
||||
} uart_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DM_INPUT,
|
||||
GPIO_DM_INPUT_PULL_DOWN,
|
||||
GPIO_DM_INPUT_PULL_UP,
|
||||
GPIO_DM_OUTPUT,
|
||||
GPIO_DM_OUTPUT_OPEN_DRAIN,
|
||||
GPIO_DM_OUTPUT_OPEN_DRAIN_PULL_UP,
|
||||
GPIO_DM_OUTPUT_OPEN_SOURCE,
|
||||
GPIO_DM_OUTPUT_OPEN_SOURCE_PULL_DOWN
|
||||
} gpio_drive_mode;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PE_NONE,
|
||||
GPIO_PE_FALLING,
|
||||
GPIO_PE_RISING,
|
||||
GPIO_PE_BOTH
|
||||
} gpio_pin_edge;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PV_LOW,
|
||||
GPIO_PV_HIGH
|
||||
} gpio_pin_value;
|
||||
|
||||
typedef void (*gpio_onchanged)(size_t pin, void* userdata);
|
||||
|
||||
typedef struct tag_gpio_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
size_t pin_count;
|
||||
void (*set_drive_mode)(void* userdata, size_t pin, gpio_drive_mode mode);
|
||||
void (*set_pin_edge)(void* userdata, size_t pin, gpio_pin_edge edge);
|
||||
void (*set_onchanged)(void* userdata, size_t pin, gpio_onchanged callback, void* callback_data);
|
||||
void (*set_pin_value)(void* userdata, size_t pin, gpio_pin_value value);
|
||||
gpio_pin_value (*get_pin_value)(void* userdata, size_t pin);
|
||||
} gpio_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_BS_STANDARD,
|
||||
I2C_BS_FAST,
|
||||
I2C_BS_HIGH_SPEED
|
||||
} i2c_bus_speed_mode;
|
||||
|
||||
typedef struct tag_i2c_device_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
int (*read)(char* buffer, size_t len, void* userdata);
|
||||
int (*write)(const char* buffer, size_t len, void* userdata);
|
||||
int (*transfer_sequential)(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
} i2c_device_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2C_EV_START,
|
||||
I2C_EV_RESTART,
|
||||
I2C_EV_STOP
|
||||
} i2c_event;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
void (*on_receive)(uint32_t data);
|
||||
uint32_t (*on_transmit)();
|
||||
void (*on_event)(i2c_event event);
|
||||
} i2c_slave_handler;
|
||||
|
||||
typedef struct tag_i2c_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
i2c_device_driver_t* (*get_device)(size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, void* userdata);
|
||||
void (*config_as_slave)(size_t slave_address, size_t address_width, i2c_bus_speed_mode bus_speed_mode, i2c_slave_handler* handler, void* userdata);
|
||||
} i2c_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
I2S_AM_STANDARD,
|
||||
I2S_AM_RIGHT,
|
||||
I2S_AM_LEFT
|
||||
} i2s_align_mode;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AUDIO_FMT_PCM
|
||||
} audio_format_type;
|
||||
|
||||
typedef struct tag_audio_format
|
||||
{
|
||||
audio_format_type type;
|
||||
size_t bits_per_sample;
|
||||
size_t sample_rate;
|
||||
size_t channels;
|
||||
} audio_format_t;
|
||||
|
||||
typedef struct tag_i2s_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*config_as_render)(const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask, void* userdata);
|
||||
void (*config_as_capture)(const audio_format_t* format, size_t delay_ms, i2s_align_mode align_mode, size_t channels_mask, void* userdata);
|
||||
void (*get_buffer)(char** buffer, size_t* frames, void* userdata);
|
||||
void (*release_buffer)(size_t frames, void* userdata);
|
||||
void (*start)(void* userdata);
|
||||
void (*stop)(void* userdata);
|
||||
} i2s_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SPI_Mode_0,
|
||||
SPI_Mode_1,
|
||||
SPI_Mode_2,
|
||||
SPI_Mode_3,
|
||||
} spi_mode;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SPI_FF_STANDARD,
|
||||
SPI_FF_DUAL,
|
||||
SPI_FF_QUAD,
|
||||
SPI_FF_OCTAL
|
||||
} spi_frame_format;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SPI_AITM_STANDARD,
|
||||
SPI_AITM_ADDR_STANDARD,
|
||||
SPI_AITM_AS_FRAME_FORMAT
|
||||
} spi_addr_inst_trans_mode;
|
||||
|
||||
typedef struct tag_spi_device_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*config)(size_t instruction_length, size_t address_length, size_t wait_cycles, spi_addr_inst_trans_mode trans_mode, void* userdata);
|
||||
double (*set_speed)(double speed, void* userdata);
|
||||
int (*read)(char* buffer, size_t len, void* userdata);
|
||||
int (*write)(const char* buffer, size_t len, void* userdata);
|
||||
int (*transfer_full_duplex)(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
int (*transfer_sequential)(const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
void (*fill)(size_t instruction, size_t address, uint32_t value, size_t count, void* userdata);
|
||||
} spi_device_driver_t;
|
||||
|
||||
typedef struct tag_spi_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
spi_device_driver_t* (*get_device)(spi_mode mode, spi_frame_format frame_format, size_t chip_select_line, size_t data_bit_length, void* userdata);
|
||||
} spi_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
VIDEO_FMT_RGB565,
|
||||
VIDEO_FMT_RGB24Planar
|
||||
} video_format;
|
||||
|
||||
typedef struct tag_sccb_device_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
uint8_t (*read_byte)(uint16_t reg_address, void* userdata);
|
||||
void (*write_byte)(uint16_t reg_address, uint8_t value, void* userdata);
|
||||
} sccb_device_driver_t;
|
||||
|
||||
typedef struct tag_sccb_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
sccb_device_driver_t* (*get_device)(size_t slave_address, size_t address_width, void* userdata);
|
||||
} sccb_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
VIDEO_FE_BEGIN,
|
||||
VIDEO_FE_END
|
||||
} video_frame_event;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DVP_SIG_POWER_DOWN,
|
||||
DVP_SIG_RESET
|
||||
} dvp_signal_type;
|
||||
|
||||
typedef void (*dvp_on_frame_event)(video_frame_event event, void* userdata);
|
||||
|
||||
typedef struct tag_dvp_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
size_t output_num;
|
||||
void (*config)(size_t width, size_t height, int auto_enable, void* userdata);
|
||||
void (*enable_frame)(void* userdata);
|
||||
void (*set_signal)(dvp_signal_type type, int value, void* userdata);
|
||||
void (*set_output_enable)(size_t index, int enable, void* userdata);
|
||||
void (*set_output_attributes)(size_t index, video_format format, void* output_buffer, void* userdata);
|
||||
void (*set_frame_event_enable)(video_frame_event event, int enable, void* userdata);
|
||||
void (*set_on_frame_event)(dvp_on_frame_event callback, void* callback_data, void* userdata);
|
||||
} dvp_driver_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
int16_t I1;
|
||||
int16_t R1;
|
||||
int16_t I2;
|
||||
int16_t R2;
|
||||
} fft_data;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FFT_512,
|
||||
FFT_256,
|
||||
FFT_128,
|
||||
FFT_64
|
||||
} fft_point;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
FFT_DIR_BACKWARD,
|
||||
FFT_DIR_FORWARD
|
||||
} fft_direction;
|
||||
|
||||
typedef struct tag_fft_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*complex_uint16)(fft_point point, fft_direction direction, uint32_t shifts_mask, const uint16_t* input, uint16_t* output, void* userdata);
|
||||
} fft_driver_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AES_CIPHER_ECB = 0,
|
||||
AES_CIPHER_CBC = 1,
|
||||
AES_CIPHER_GCM = 2
|
||||
} aes_cipher_mod;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AES_128 = 16,
|
||||
AES_192 = 24,
|
||||
AES_256 = 32,
|
||||
} aes_kmode;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
AES_MODE_ENCRYPTION = 0,
|
||||
AES_MODE_DECRYPTION = 1,
|
||||
} aes_encrypt_sel;
|
||||
|
||||
typedef struct tag_aes_parameter
|
||||
{
|
||||
uint8_t* aes_in_data;
|
||||
uint8_t* key_addr;
|
||||
uint8_t key_length;
|
||||
uint8_t* gcm_iv;
|
||||
uint8_t iv_length;
|
||||
uint8_t* aes_aad;
|
||||
uint32_t add_size;
|
||||
aes_cipher_mod cipher_mod;
|
||||
uint32_t data_size;
|
||||
uint8_t* aes_out_data;
|
||||
uint8_t* tag;
|
||||
} aes_parameter;
|
||||
|
||||
typedef struct tag_aes_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*decrypt)(aes_parameter* aes_param, void* userdata);
|
||||
void (*encrypt)(aes_parameter* aes_param, void* userdata);
|
||||
} aes_driver_t;
|
||||
|
||||
typedef struct tag_sha256_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*sha_str)(const char* str, size_t length, uint8_t* hash, void* userdata);
|
||||
} sha256_driver_t;
|
||||
|
||||
typedef void (*timer_ontick)(void* userdata);
|
||||
|
||||
typedef struct tag_timer_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
size_t (*set_interval)(size_t nanoseconds, void* userdata);
|
||||
void (*set_ontick)(timer_ontick ontick, void* ontick_data, void* userdata);
|
||||
void (*set_enable)(int enable, void* userdata);
|
||||
} timer_driver_t;
|
||||
|
||||
typedef struct tag_pwm_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
size_t pin_count;
|
||||
double (*set_frequency)(double frequency, void* userdata);
|
||||
double (*set_active_duty_cycle_percentage)(size_t pin, double duty_cycle_percentage, void* userdata);
|
||||
void (*set_enable)(size_t pin, int enable, void* userdata);
|
||||
} pwm_driver_t;
|
||||
|
||||
typedef struct tag_datetime
|
||||
{
|
||||
uint32_t year;
|
||||
uint32_t month;
|
||||
uint32_t day;
|
||||
uint32_t hour;
|
||||
uint32_t minute;
|
||||
uint32_t second;
|
||||
} datetime_t;
|
||||
|
||||
typedef struct tag_rtc_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*get_datetime)(datetime_t* datetime, void* userdata);
|
||||
void (*set_datetime)(const datetime_t* datetime, void* userdata);
|
||||
} rtc_driver_t;
|
||||
|
||||
typedef struct tag_custom_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
int (*io_control)(size_t control_code, const char* write_buffer, size_t write_len, char* read_buffer, size_t read_len, void* userdata);
|
||||
} custom_driver_t;
|
||||
|
||||
/* ===== internal drivers ======*/
|
||||
|
||||
typedef void (*pic_irq_handler)(void* userdata);
|
||||
void kernel_iface_pic_on_irq(size_t irq);
|
||||
|
||||
typedef struct tag_pic_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*set_irq_enable)(size_t irq, int enable, void* userdata);
|
||||
void (*set_irq_priority)(size_t irq, size_t priority, void* userdata);
|
||||
} pic_driver_t;
|
||||
|
||||
typedef struct tag_dmac_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
} dmac_driver_t;
|
||||
|
||||
typedef void (*dma_stage_completion_handler)(void* userdata);
|
||||
|
||||
typedef struct tag_dma_driver
|
||||
{
|
||||
driver_base_t base;
|
||||
void (*set_select_request)(uint32_t request, void* userdata);
|
||||
void (*config)(uint32_t priority, void* userdata);
|
||||
void (*transmit_async)(const volatile void* src, volatile void* dest, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, SemaphoreHandle_t completion_event, void* userdata);
|
||||
void (*loop_async)(const volatile void** srcs, size_t src_num, volatile void** dests, size_t dest_num, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, dma_stage_completion_handler stage_completion_handler, void* stage_completion_handler_data, SemaphoreHandle_t completion_event, int* stop_signal, void* userdata);
|
||||
} dma_driver_t;
|
||||
|
||||
extern driver_registry_t g_hal_drivers[];
|
||||
extern driver_registry_t g_dma_drivers[];
|
||||
extern driver_registry_t g_system_drivers[];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FREERTOS_DRIVER_H */
|
|
@ -0,0 +1,142 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
#ifndef _FREERTOS_DEVICES_INTERN_H
|
||||
#define _FREERTOS_DEVICES_INTERN_H
|
||||
|
||||
#include <driver.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#define MAX_IRQN 256
|
||||
|
||||
/**
|
||||
* @brief Install HAL
|
||||
*/
|
||||
void install_hal();
|
||||
|
||||
/**
|
||||
* @brief Set frequency of CPU
|
||||
* @param[in] frequency The desired frequency in Hz
|
||||
*
|
||||
* @return The actual frequency of CPU after set
|
||||
*/
|
||||
uint32_t system_set_cpu_frequency(uint32_t frequency);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable IRQ
|
||||
* @param[in] irq IRQ number
|
||||
* @param[in] enable 1 is enable, 0 is disable
|
||||
*/
|
||||
void pic_set_irq_enable(size_t irq, int enable);
|
||||
|
||||
/**
|
||||
* @brief Set priority of IRQ
|
||||
* @param[in] irq IRQ number
|
||||
* @param[in] priority The priority of IRQ
|
||||
*/
|
||||
void pic_set_irq_priority(size_t irq, size_t priority);
|
||||
|
||||
/**
|
||||
* @brief Set handler of IRQ
|
||||
* @param[in] irq IRQ number
|
||||
* @param[in] handler The handler function
|
||||
* @param[in] userdata The userdata of the handler function
|
||||
*/
|
||||
void pic_set_irq_handler(size_t irq, pic_irq_handler handler, void* userdata);
|
||||
|
||||
/**
|
||||
* @brief Wait for a free DMA and open it
|
||||
*
|
||||
* @return The DMA handle
|
||||
*/
|
||||
uintptr_t dma_open_free();
|
||||
|
||||
/**
|
||||
* @brief Close DMA
|
||||
* @param[in] file The DMA handle
|
||||
*/
|
||||
void dma_close(uintptr_t file);
|
||||
|
||||
/**
|
||||
* @brief Set the request line of DMA
|
||||
* @param[in] file The DMA handle
|
||||
* @param[in] request The request line number
|
||||
*/
|
||||
void dma_set_select_request(uintptr_t file, uint32_t request);
|
||||
|
||||
/**
|
||||
* @brief DMA asynchronously
|
||||
* @param[in] file The DMA handle
|
||||
* @param[in] src The address of source
|
||||
* @param[out] dest The address of destination
|
||||
* @param[in] src_inc Enable increment of source address
|
||||
* @param[in] dest_inc Enable increment of destination address
|
||||
* @param[in] element_size Element size in bytes
|
||||
* @param[in] count Element count to transmit
|
||||
* @param[in] burst_size Element count to transmit per request
|
||||
* @param[in] completion_event Event to signal when this transmition is completed
|
||||
*/
|
||||
void dma_transmit_async(uintptr_t file, const volatile void* src, volatile void* dest, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, SemaphoreHandle_t completion_event);
|
||||
|
||||
/**
|
||||
* @brief DMA synchrnonously
|
||||
* @param[in] file The DMA handle
|
||||
* @param[in] src The address of source
|
||||
* @param[out] dest The address of destination
|
||||
* @param[in] src_inc Enable increment of source address
|
||||
* @param[in] dest_inc Enable increment of destination address
|
||||
* @param[in] element_size Element size in bytes
|
||||
* @param[in] count Element count to transmit
|
||||
* @param[in] burst_size Element count to transmit per request
|
||||
*/
|
||||
void dma_transmit(uintptr_t file, const volatile void* src, volatile void* dest, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size);
|
||||
|
||||
/**
|
||||
* @brief DMA loop asynchronously
|
||||
* @param[in] file The DMA handle
|
||||
* @param[in] srcs The addresses of source
|
||||
* @param[in] src_num The source addresses count
|
||||
* @param[out] dests The addresses of destination
|
||||
* @param[in] dest_num The destination addresses count
|
||||
* @param[in] src_inc Enable increment of source address
|
||||
* @param[in] dest_inc Enable increment of destination address
|
||||
* @param[in] element_size Element size in bytes
|
||||
* @param[in] count Element count to transmit in one loop
|
||||
* @param[in] burst_size Element count to transmit per request
|
||||
* @param[in] stage_completion_handler The handler function when on loop is completed
|
||||
* @param[in] stage_completion_handler_data The userdata of the handler function
|
||||
* @param[in] completion_event Event to signal when this transmition is completed
|
||||
* @param[in] stop_signal The address of signal indicating whether to stop the transmition, set to 1 to stop
|
||||
*/
|
||||
void dma_loop_async(uintptr_t file, const volatile void** srcs, size_t src_num, volatile void** dests, size_t dest_num, int src_inc, int dest_inc, size_t element_size, size_t count, size_t burst_size, dma_stage_completion_handler stage_completion_handler, void* stage_completion_handler_data, SemaphoreHandle_t completion_event, int* stop_signal);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Install a custom driver
|
||||
* @param[in] name Specify the path to access it later
|
||||
* @param[in] driver The driver info
|
||||
*/
|
||||
void install_custom_driver(const char* name, const custom_driver_t* driver);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FREERTOS_DEVICES_INTERN_H */
|
|
@ -0,0 +1,752 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/* Standard includes. */
|
||||
#include <stdlib.h>
|
||||
|
||||
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
|
||||
all the API functions to use the MPU wrappers. That should only be done when
|
||||
task.h is included from an application file. */
|
||||
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "timers.h"
|
||||
#include "event_groups.h"
|
||||
|
||||
/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
|
||||
MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
|
||||
header files above, but not in this file, in order to generate the correct
|
||||
privileged Vs unprivileged linkage and placement. */
|
||||
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
|
||||
|
||||
/* The following bit fields convey control information in a task's event list
|
||||
item value. It is important they don't clash with the
|
||||
taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
|
||||
#if configUSE_16_BIT_TICKS == 1
|
||||
#define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U
|
||||
#define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U
|
||||
#define eventWAIT_FOR_ALL_BITS 0x0400U
|
||||
#define eventEVENT_BITS_CONTROL_BYTES 0xff00U
|
||||
#else
|
||||
#define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL
|
||||
#define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL
|
||||
#define eventWAIT_FOR_ALL_BITS 0x04000000UL
|
||||
#define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL
|
||||
#endif
|
||||
|
||||
typedef struct xEventGroupDefinition
|
||||
{
|
||||
EventBits_t uxEventBits;
|
||||
List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
|
||||
|
||||
#if( configUSE_TRACE_FACILITY == 1 )
|
||||
UBaseType_t uxEventGroupNumber;
|
||||
#endif
|
||||
|
||||
#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
||||
uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
|
||||
#endif
|
||||
} EventGroup_t;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* Test the bits set in uxCurrentEventBits to see if the wait condition is met.
|
||||
* The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is
|
||||
* pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
|
||||
* are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the
|
||||
* wait condition is met if any of the bits set in uxBitsToWait for are also set
|
||||
* in uxCurrentEventBits.
|
||||
*/
|
||||
static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||||
|
||||
EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
|
||||
{
|
||||
EventGroup_t *pxEventBits;
|
||||
|
||||
/* A StaticEventGroup_t object must be provided. */
|
||||
configASSERT( pxEventGroupBuffer );
|
||||
|
||||
#if( configASSERT_DEFINED == 1 )
|
||||
{
|
||||
/* Sanity check that the size of the structure used to declare a
|
||||
variable of type StaticEventGroup_t equals the size of the real
|
||||
event group structure. */
|
||||
volatile size_t xSize = sizeof( StaticEventGroup_t );
|
||||
configASSERT( xSize == sizeof( EventGroup_t ) );
|
||||
}
|
||||
#endif /* configASSERT_DEFINED */
|
||||
|
||||
/* The user has provided a statically allocated event group - use it. */
|
||||
pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
|
||||
|
||||
if( pxEventBits != NULL )
|
||||
{
|
||||
pxEventBits->uxEventBits = 0;
|
||||
vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
|
||||
|
||||
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||||
{
|
||||
/* Both static and dynamic allocation can be used, so note that
|
||||
this event group was created statically in case the event group
|
||||
is later deleted. */
|
||||
pxEventBits->ucStaticallyAllocated = pdTRUE;
|
||||
}
|
||||
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||||
|
||||
traceEVENT_GROUP_CREATE( pxEventBits );
|
||||
}
|
||||
else
|
||||
{
|
||||
traceEVENT_GROUP_CREATE_FAILED();
|
||||
}
|
||||
|
||||
return ( EventGroupHandle_t ) pxEventBits;
|
||||
}
|
||||
|
||||
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||||
|
||||
EventGroupHandle_t xEventGroupCreate( void )
|
||||
{
|
||||
EventGroup_t *pxEventBits;
|
||||
|
||||
/* Allocate the event group. */
|
||||
pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
|
||||
|
||||
if( pxEventBits != NULL )
|
||||
{
|
||||
pxEventBits->uxEventBits = 0;
|
||||
vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
|
||||
|
||||
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||||
{
|
||||
/* Both static and dynamic allocation can be used, so note this
|
||||
event group was allocated statically in case the event group is
|
||||
later deleted. */
|
||||
pxEventBits->ucStaticallyAllocated = pdFALSE;
|
||||
}
|
||||
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||||
|
||||
traceEVENT_GROUP_CREATE( pxEventBits );
|
||||
}
|
||||
else
|
||||
{
|
||||
traceEVENT_GROUP_CREATE_FAILED();
|
||||
}
|
||||
|
||||
return ( EventGroupHandle_t ) pxEventBits;
|
||||
}
|
||||
|
||||
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
|
||||
{
|
||||
EventBits_t uxOriginalBitValue, uxReturn;
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
BaseType_t xAlreadyYielded;
|
||||
BaseType_t xTimeoutOccurred = pdFALSE;
|
||||
|
||||
configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||
configASSERT( uxBitsToWaitFor != 0 );
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
{
|
||||
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
||||
}
|
||||
#endif
|
||||
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
uxOriginalBitValue = pxEventBits->uxEventBits;
|
||||
|
||||
( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
|
||||
|
||||
if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
|
||||
{
|
||||
/* All the rendezvous bits are now set - no need to block. */
|
||||
uxReturn = ( uxOriginalBitValue | uxBitsToSet );
|
||||
|
||||
/* Rendezvous always clear the bits. They will have been cleared
|
||||
already unless this is the only task in the rendezvous. */
|
||||
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||
|
||||
xTicksToWait = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
if( xTicksToWait != ( TickType_t ) 0 )
|
||||
{
|
||||
traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
|
||||
|
||||
/* Store the bits that the calling task is waiting for in the
|
||||
task's event list item so the kernel knows when a match is
|
||||
found. Then enter the blocked state. */
|
||||
vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
|
||||
|
||||
/* This assignment is obsolete as uxReturn will get set after
|
||||
the task unblocks, but some compilers mistakenly generate a
|
||||
warning about uxReturn being returned without being set if the
|
||||
assignment is omitted. */
|
||||
uxReturn = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The rendezvous bits were not set, but no block time was
|
||||
specified - just return the current event bit value. */
|
||||
uxReturn = pxEventBits->uxEventBits;
|
||||
xTimeoutOccurred = pdTRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
xAlreadyYielded = xTaskResumeAll();
|
||||
|
||||
if( xTicksToWait != ( TickType_t ) 0 )
|
||||
{
|
||||
if( xAlreadyYielded == pdFALSE )
|
||||
{
|
||||
portYIELD_WITHIN_API();
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
|
||||
/* The task blocked to wait for its required bits to be set - at this
|
||||
point either the required bits were set or the block time expired. If
|
||||
the required bits were set they will have been stored in the task's
|
||||
event list item, and they should now be retrieved then cleared. */
|
||||
uxReturn = uxTaskResetEventItemValue();
|
||||
|
||||
if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
|
||||
{
|
||||
/* The task timed out, just return the current event bit value. */
|
||||
taskENTER_CRITICAL();
|
||||
{
|
||||
uxReturn = pxEventBits->uxEventBits;
|
||||
|
||||
/* Although the task got here because it timed out before the
|
||||
bits it was waiting for were set, it is possible that since it
|
||||
unblocked another task has set the bits. If this is the case
|
||||
then it needs to clear the bits before exiting. */
|
||||
if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
|
||||
{
|
||||
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
taskEXIT_CRITICAL();
|
||||
|
||||
xTimeoutOccurred = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The task unblocked because the bits were set. */
|
||||
}
|
||||
|
||||
/* Control bits might be set as the task had blocked should not be
|
||||
returned. */
|
||||
uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
|
||||
}
|
||||
|
||||
traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
|
||||
|
||||
/* Prevent compiler warnings when trace macros are not used. */
|
||||
( void ) xTimeoutOccurred;
|
||||
|
||||
return uxReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
|
||||
{
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
EventBits_t uxReturn, uxControlBits = 0;
|
||||
BaseType_t xWaitConditionMet, xAlreadyYielded;
|
||||
BaseType_t xTimeoutOccurred = pdFALSE;
|
||||
|
||||
/* Check the user is not attempting to wait on the bits used by the kernel
|
||||
itself, and that at least one bit is being requested. */
|
||||
configASSERT( xEventGroup );
|
||||
configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||
configASSERT( uxBitsToWaitFor != 0 );
|
||||
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||
{
|
||||
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
||||
}
|
||||
#endif
|
||||
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
|
||||
|
||||
/* Check to see if the wait condition is already met or not. */
|
||||
xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
|
||||
|
||||
if( xWaitConditionMet != pdFALSE )
|
||||
{
|
||||
/* The wait condition has already been met so there is no need to
|
||||
block. */
|
||||
uxReturn = uxCurrentEventBits;
|
||||
xTicksToWait = ( TickType_t ) 0;
|
||||
|
||||
/* Clear the wait bits if requested to do so. */
|
||||
if( xClearOnExit != pdFALSE )
|
||||
{
|
||||
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
else if( xTicksToWait == ( TickType_t ) 0 )
|
||||
{
|
||||
/* The wait condition has not been met, but no block time was
|
||||
specified, so just return the current value. */
|
||||
uxReturn = uxCurrentEventBits;
|
||||
xTimeoutOccurred = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The task is going to block to wait for its required bits to be
|
||||
set. uxControlBits are used to remember the specified behaviour of
|
||||
this call to xEventGroupWaitBits() - for use when the event bits
|
||||
unblock the task. */
|
||||
if( xClearOnExit != pdFALSE )
|
||||
{
|
||||
uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
|
||||
if( xWaitForAllBits != pdFALSE )
|
||||
{
|
||||
uxControlBits |= eventWAIT_FOR_ALL_BITS;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
|
||||
/* Store the bits that the calling task is waiting for in the
|
||||
task's event list item so the kernel knows when a match is
|
||||
found. Then enter the blocked state. */
|
||||
vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
|
||||
|
||||
/* This is obsolete as it will get set after the task unblocks, but
|
||||
some compilers mistakenly generate a warning about the variable
|
||||
being returned without being set if it is not done. */
|
||||
uxReturn = 0;
|
||||
|
||||
traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
|
||||
}
|
||||
}
|
||||
xAlreadyYielded = xTaskResumeAll();
|
||||
|
||||
if( xTicksToWait != ( TickType_t ) 0 )
|
||||
{
|
||||
if( xAlreadyYielded == pdFALSE )
|
||||
{
|
||||
portYIELD_WITHIN_API();
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
|
||||
/* The task blocked to wait for its required bits to be set - at this
|
||||
point either the required bits were set or the block time expired. If
|
||||
the required bits were set they will have been stored in the task's
|
||||
event list item, and they should now be retrieved then cleared. */
|
||||
uxReturn = uxTaskResetEventItemValue();
|
||||
|
||||
if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
|
||||
{
|
||||
taskENTER_CRITICAL();
|
||||
{
|
||||
/* The task timed out, just return the current event bit value. */
|
||||
uxReturn = pxEventBits->uxEventBits;
|
||||
|
||||
/* It is possible that the event bits were updated between this
|
||||
task leaving the Blocked state and running again. */
|
||||
if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
|
||||
{
|
||||
if( xClearOnExit != pdFALSE )
|
||||
{
|
||||
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
xTimeoutOccurred = pdTRUE;
|
||||
}
|
||||
taskEXIT_CRITICAL();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* The task unblocked because the bits were set. */
|
||||
}
|
||||
|
||||
/* The task blocked so control bits may have been set. */
|
||||
uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
|
||||
}
|
||||
traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
|
||||
|
||||
/* Prevent compiler warnings when trace macros are not used. */
|
||||
( void ) xTimeoutOccurred;
|
||||
|
||||
return uxReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
|
||||
{
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
EventBits_t uxReturn;
|
||||
|
||||
/* Check the user is not attempting to clear the bits used by the kernel
|
||||
itself. */
|
||||
configASSERT( xEventGroup );
|
||||
configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||
|
||||
taskENTER_CRITICAL();
|
||||
{
|
||||
traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
|
||||
|
||||
/* The value returned is the event group value prior to the bits being
|
||||
cleared. */
|
||||
uxReturn = pxEventBits->uxEventBits;
|
||||
|
||||
/* Clear the bits. */
|
||||
pxEventBits->uxEventBits &= ~uxBitsToClear;
|
||||
}
|
||||
taskEXIT_CRITICAL();
|
||||
|
||||
return uxReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
|
||||
|
||||
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
|
||||
{
|
||||
BaseType_t xReturn;
|
||||
|
||||
traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
|
||||
xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
|
||||
{
|
||||
UBaseType_t uxSavedInterruptStatus;
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
EventBits_t uxReturn;
|
||||
|
||||
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||
{
|
||||
uxReturn = pxEventBits->uxEventBits;
|
||||
}
|
||||
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
||||
|
||||
return uxReturn;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
|
||||
{
|
||||
ListItem_t *pxListItem, *pxNext;
|
||||
ListItem_t const *pxListEnd;
|
||||
List_t *pxList;
|
||||
EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
BaseType_t xMatchFound = pdFALSE;
|
||||
|
||||
/* Check the user is not attempting to set the bits used by the kernel
|
||||
itself. */
|
||||
configASSERT( xEventGroup );
|
||||
configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||
|
||||
pxList = &( pxEventBits->xTasksWaitingForBits );
|
||||
pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
|
||||
|
||||
pxListItem = listGET_HEAD_ENTRY( pxList );
|
||||
|
||||
/* Set the bits. */
|
||||
pxEventBits->uxEventBits |= uxBitsToSet;
|
||||
|
||||
/* See if the new bit value should unblock any tasks. */
|
||||
while( pxListItem != pxListEnd )
|
||||
{
|
||||
pxNext = listGET_NEXT( pxListItem );
|
||||
uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
|
||||
xMatchFound = pdFALSE;
|
||||
|
||||
/* Split the bits waited for from the control bits. */
|
||||
uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
|
||||
uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
|
||||
|
||||
if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
|
||||
{
|
||||
/* Just looking for single bit being set. */
|
||||
if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
|
||||
{
|
||||
xMatchFound = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
|
||||
{
|
||||
/* All bits are set. */
|
||||
xMatchFound = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Need all bits to be set, but not all the bits were set. */
|
||||
}
|
||||
|
||||
if( xMatchFound != pdFALSE )
|
||||
{
|
||||
/* The bits match. Should the bits be cleared on exit? */
|
||||
if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
|
||||
{
|
||||
uxBitsToClear |= uxBitsWaitedFor;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
|
||||
/* Store the actual event flag value in the task's event list
|
||||
item before removing the task from the event list. The
|
||||
eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
|
||||
that is was unblocked due to its required bits matching, rather
|
||||
than because it timed out. */
|
||||
vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
|
||||
}
|
||||
|
||||
/* Move onto the next list item. Note pxListItem->pxNext is not
|
||||
used here as the list item may have been removed from the event list
|
||||
and inserted into the ready/pending reading list. */
|
||||
pxListItem = pxNext;
|
||||
}
|
||||
|
||||
/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
|
||||
bit was set in the control word. */
|
||||
pxEventBits->uxEventBits &= ~uxBitsToClear;
|
||||
}
|
||||
( void ) xTaskResumeAll();
|
||||
|
||||
return pxEventBits->uxEventBits;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
void vEventGroupDelete( EventGroupHandle_t xEventGroup )
|
||||
{
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
|
||||
|
||||
vTaskSuspendAll();
|
||||
{
|
||||
traceEVENT_GROUP_DELETE( xEventGroup );
|
||||
|
||||
while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
|
||||
{
|
||||
/* Unblock the task, returning 0 as the event list is being deleted
|
||||
and cannot therefore have any bits set. */
|
||||
configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
|
||||
vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
|
||||
}
|
||||
|
||||
#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
|
||||
{
|
||||
/* The event group can only have been allocated dynamically - free
|
||||
it again. */
|
||||
vPortFree( pxEventBits );
|
||||
}
|
||||
#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
||||
{
|
||||
/* The event group could have been allocated statically or
|
||||
dynamically, so check before attempting to free the memory. */
|
||||
if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
|
||||
{
|
||||
vPortFree( pxEventBits );
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||||
}
|
||||
( void ) xTaskResumeAll();
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* For internal use only - execute a 'set bits' command that was pended from
|
||||
an interrupt. */
|
||||
void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
|
||||
{
|
||||
( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* For internal use only - execute a 'clear bits' command that was pended from
|
||||
an interrupt. */
|
||||
void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
|
||||
{
|
||||
( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
|
||||
{
|
||||
BaseType_t xWaitConditionMet = pdFALSE;
|
||||
|
||||
if( xWaitForAllBits == pdFALSE )
|
||||
{
|
||||
/* Task only has to wait for one bit within uxBitsToWaitFor to be
|
||||
set. Is one already set? */
|
||||
if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
|
||||
{
|
||||
xWaitConditionMet = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
|
||||
Are they set already? */
|
||||
if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
|
||||
{
|
||||
xWaitConditionMet = pdTRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
mtCOVERAGE_TEST_MARKER();
|
||||
}
|
||||
}
|
||||
|
||||
return xWaitConditionMet;
|
||||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
|
||||
|
||||
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
|
||||
{
|
||||
BaseType_t xReturn;
|
||||
|
||||
traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
|
||||
xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if (configUSE_TRACE_FACILITY == 1)
|
||||
|
||||
UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
|
||||
{
|
||||
UBaseType_t xReturn;
|
||||
EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
|
||||
|
||||
if( xEventGroup == NULL )
|
||||
{
|
||||
xReturn = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
xReturn = pxEventBits->uxEventGroupNumber;
|
||||
}
|
||||
|
||||
return xReturn;
|
||||
}
|
||||
|
||||
#endif /* configUSE_TRACE_FACILITY */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||
|
||||
void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber )
|
||||
{
|
||||
( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber;
|
||||
}
|
||||
|
||||
#endif /* configUSE_TRACE_FACILITY */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
|
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,147 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef STACK_MACROS_H
|
||||
#define STACK_MACROS_H
|
||||
|
||||
#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
|
||||
#warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released.
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Call the stack overflow hook function if the stack of the task being swapped
|
||||
* out is currently overflowed, or looks like it might have overflowed in the
|
||||
* past.
|
||||
*
|
||||
* Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
|
||||
* the current stack state only - comparing the current top of stack value to
|
||||
* the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
|
||||
* will also cause the last few stack bytes to be checked to ensure the value
|
||||
* to which the bytes were set when the task was created have not been
|
||||
* overwritten. Note this second test does not guarantee that an overflowed
|
||||
* stack will always be recognised.
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
|
||||
|
||||
/* Only the current stack state is to be checked. */
|
||||
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||
{ \
|
||||
/* Is the currently saved stack pointer within the stack limit? */ \
|
||||
if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack ) \
|
||||
{ \
|
||||
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
|
||||
|
||||
/* Only the current stack state is to be checked. */
|
||||
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||
{ \
|
||||
\
|
||||
/* Is the currently saved stack pointer within the stack limit? */ \
|
||||
if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack ) \
|
||||
{ \
|
||||
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
|
||||
|
||||
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||
{ \
|
||||
const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
|
||||
const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
|
||||
\
|
||||
if( ( pulStack[ 0 ] != ulCheckValue ) || \
|
||||
( pulStack[ 1 ] != ulCheckValue ) || \
|
||||
( pulStack[ 2 ] != ulCheckValue ) || \
|
||||
( pulStack[ 3 ] != ulCheckValue ) ) \
|
||||
{ \
|
||||
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
|
||||
|
||||
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||
{ \
|
||||
int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
|
||||
static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
|
||||
\
|
||||
\
|
||||
pcEndOfStack -= sizeof( ucExpectedStackBytes ); \
|
||||
\
|
||||
/* Has the extremity of the task stack ever been written over? */ \
|
||||
if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
|
||||
{ \
|
||||
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||
} \
|
||||
}
|
||||
|
||||
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Remove stack overflow macro if not being used. */
|
||||
#ifndef taskCHECK_FOR_STACK_OVERFLOW
|
||||
#define taskCHECK_FOR_STACK_OVERFLOW()
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#endif /* STACK_MACROS_H */
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
//
|
||||
// Core Synchronization
|
||||
|
||||
#ifndef CORE_SYNC_H
|
||||
#define CORE_SYNC_H
|
||||
|
||||
#include "FreeRTOS.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
typedef enum
|
||||
{
|
||||
CORE_SYNC_NONE,
|
||||
CORE_SYNC_ADD_TCB,
|
||||
CORE_SYNC_CONTEXT_SWITCH,
|
||||
CORE_SYNC_WAKE_UP
|
||||
} core_sync_event_t;
|
||||
|
||||
void core_sync_request_context_switch(uint64_t hart_id);
|
||||
void core_sync_complete(uint64_t hart_id);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CORE_SYNC_H */
|
|
@ -0,0 +1,734 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef CO_ROUTINE_H
|
||||
#define CO_ROUTINE_H
|
||||
|
||||
#ifndef INC_FREERTOS_H
|
||||
#error "include FreeRTOS.h must appear in source files before include croutine.h"
|
||||
#endif
|
||||
|
||||
#include "list.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Used to hide the implementation of the co-routine control block. The
|
||||
control block structure however has to be included in the header due to
|
||||
the macro implementation of the co-routine functionality. */
|
||||
typedef void * CoRoutineHandle_t;
|
||||
|
||||
/* Defines the prototype to which co-routine functions must conform. */
|
||||
typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
|
||||
|
||||
typedef struct corCoRoutineControlBlock
|
||||
{
|
||||
crCOROUTINE_CODE pxCoRoutineFunction;
|
||||
ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
|
||||
ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */
|
||||
UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */
|
||||
UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
|
||||
uint16_t uxState; /*< Used internally by the co-routine implementation. */
|
||||
} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
*<pre>
|
||||
BaseType_t xCoRoutineCreate(
|
||||
crCOROUTINE_CODE pxCoRoutineCode,
|
||||
UBaseType_t uxPriority,
|
||||
UBaseType_t uxIndex
|
||||
);</pre>
|
||||
*
|
||||
* Create a new co-routine and add it to the list of co-routines that are
|
||||
* ready to run.
|
||||
*
|
||||
* @param pxCoRoutineCode Pointer to the co-routine function. Co-routine
|
||||
* functions require special syntax - see the co-routine section of the WEB
|
||||
* documentation for more information.
|
||||
*
|
||||
* @param uxPriority The priority with respect to other co-routines at which
|
||||
* the co-routine will run.
|
||||
*
|
||||
* @param uxIndex Used to distinguish between different co-routines that
|
||||
* execute the same function. See the example below and the co-routine section
|
||||
* of the WEB documentation for further information.
|
||||
*
|
||||
* @return pdPASS if the co-routine was successfully created and added to a ready
|
||||
* list, otherwise an error code defined with ProjDefs.h.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Co-routine to be created.
|
||||
void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||
// This may not be necessary for const variables.
|
||||
static const char cLedToFlash[ 2 ] = { 5, 6 };
|
||||
static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
|
||||
|
||||
// Must start every co-routine with a call to crSTART();
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// This co-routine just delays for a fixed period, then toggles
|
||||
// an LED. Two co-routines are created using this function, so
|
||||
// the uxIndex parameter is used to tell the co-routine which
|
||||
// LED to flash and how int32_t to delay. This assumes xQueue has
|
||||
// already been created.
|
||||
vParTestToggleLED( cLedToFlash[ uxIndex ] );
|
||||
crDELAY( xHandle, uxFlashRates[ uxIndex ] );
|
||||
}
|
||||
|
||||
// Must end every co-routine with a call to crEND();
|
||||
crEND();
|
||||
}
|
||||
|
||||
// Function that creates two co-routines.
|
||||
void vOtherFunction( void )
|
||||
{
|
||||
uint8_t ucParameterToPass;
|
||||
TaskHandle_t xHandle;
|
||||
|
||||
// Create two co-routines at priority 0. The first is given index 0
|
||||
// so (from the code above) toggles LED 5 every 200 ticks. The second
|
||||
// is given index 1 so toggles LED 6 every 400 ticks.
|
||||
for( uxIndex = 0; uxIndex < 2; uxIndex++ )
|
||||
{
|
||||
xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xCoRoutineCreate xCoRoutineCreate
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
|
||||
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
*<pre>
|
||||
void vCoRoutineSchedule( void );</pre>
|
||||
*
|
||||
* Run a co-routine.
|
||||
*
|
||||
* vCoRoutineSchedule() executes the highest priority co-routine that is able
|
||||
* to run. The co-routine will execute until it either blocks, yields or is
|
||||
* preempted by a task. Co-routines execute cooperatively so one
|
||||
* co-routine cannot be preempted by another, but can be preempted by a task.
|
||||
*
|
||||
* If an application comprises of both tasks and co-routines then
|
||||
* vCoRoutineSchedule should be called from the idle task (in an idle task
|
||||
* hook).
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// This idle task hook will schedule a co-routine each time it is called.
|
||||
// The rest of the idle task will execute between co-routine calls.
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
vCoRoutineSchedule();
|
||||
}
|
||||
|
||||
// Alternatively, if you do not require any other part of the idle task to
|
||||
// execute, the idle task hook can call vCoRoutineScheduler() within an
|
||||
// infinite loop.
|
||||
void vApplicationIdleHook( void )
|
||||
{
|
||||
for( ;; )
|
||||
{
|
||||
vCoRoutineSchedule();
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup vCoRoutineSchedule vCoRoutineSchedule
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
void vCoRoutineSchedule( void );
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
* <pre>
|
||||
crSTART( CoRoutineHandle_t xHandle );</pre>
|
||||
*
|
||||
* This macro MUST always be called at the start of a co-routine function.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Co-routine to be created.
|
||||
void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||
static int32_t ulAVariable;
|
||||
|
||||
// Must start every co-routine with a call to crSTART();
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Co-routine functionality goes here.
|
||||
}
|
||||
|
||||
// Must end every co-routine with a call to crEND();
|
||||
crEND();
|
||||
}</pre>
|
||||
* \defgroup crSTART crSTART
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
* <pre>
|
||||
crEND();</pre>
|
||||
*
|
||||
* This macro MUST always be called at the end of a co-routine function.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Co-routine to be created.
|
||||
void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||
static int32_t ulAVariable;
|
||||
|
||||
// Must start every co-routine with a call to crSTART();
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Co-routine functionality goes here.
|
||||
}
|
||||
|
||||
// Must end every co-routine with a call to crEND();
|
||||
crEND();
|
||||
}</pre>
|
||||
* \defgroup crSTART crSTART
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crEND() }
|
||||
|
||||
/*
|
||||
* These macros are intended for internal use by the co-routine implementation
|
||||
* only. The macros should not be used directly by application writers.
|
||||
*/
|
||||
#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
|
||||
#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
*<pre>
|
||||
crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
|
||||
*
|
||||
* Delay a co-routine for a fixed period of time.
|
||||
*
|
||||
* crDELAY can only be called from the co-routine function itself - not
|
||||
* from within a function called by the co-routine function. This is because
|
||||
* co-routines do not maintain their own stack.
|
||||
*
|
||||
* @param xHandle The handle of the co-routine to delay. This is the xHandle
|
||||
* parameter of the co-routine function.
|
||||
*
|
||||
* @param xTickToDelay The number of ticks that the co-routine should delay
|
||||
* for. The actual amount of time this equates to is defined by
|
||||
* configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS
|
||||
* can be used to convert ticks to milliseconds.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Co-routine to be created.
|
||||
void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||
// This may not be necessary for const variables.
|
||||
// We are to delay for 200ms.
|
||||
static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
|
||||
|
||||
// Must start every co-routine with a call to crSTART();
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Delay for 200ms.
|
||||
crDELAY( xHandle, xDelayTime );
|
||||
|
||||
// Do something here.
|
||||
}
|
||||
|
||||
// Must end every co-routine with a call to crEND();
|
||||
crEND();
|
||||
}</pre>
|
||||
* \defgroup crDELAY crDELAY
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crDELAY( xHandle, xTicksToDelay ) \
|
||||
if( ( xTicksToDelay ) > 0 ) \
|
||||
{ \
|
||||
vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
|
||||
} \
|
||||
crSET_STATE0( ( xHandle ) );
|
||||
|
||||
/**
|
||||
* <pre>
|
||||
crQUEUE_SEND(
|
||||
CoRoutineHandle_t xHandle,
|
||||
QueueHandle_t pxQueue,
|
||||
void *pvItemToQueue,
|
||||
TickType_t xTicksToWait,
|
||||
BaseType_t *pxResult
|
||||
)</pre>
|
||||
*
|
||||
* The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
|
||||
* equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
|
||||
*
|
||||
* crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
|
||||
* xQueueSend() and xQueueReceive() can only be used from tasks.
|
||||
*
|
||||
* crQUEUE_SEND can only be called from the co-routine function itself - not
|
||||
* from within a function called by the co-routine function. This is because
|
||||
* co-routines do not maintain their own stack.
|
||||
*
|
||||
* See the co-routine section of the WEB documentation for information on
|
||||
* passing data between tasks and co-routines and between ISR's and
|
||||
* co-routines.
|
||||
*
|
||||
* @param xHandle The handle of the calling co-routine. This is the xHandle
|
||||
* parameter of the co-routine function.
|
||||
*
|
||||
* @param pxQueue The handle of the queue on which the data will be posted.
|
||||
* The handle is obtained as the return value when the queue is created using
|
||||
* the xQueueCreate() API function.
|
||||
*
|
||||
* @param pvItemToQueue A pointer to the data being posted onto the queue.
|
||||
* The number of bytes of each queued item is specified when the queue is
|
||||
* created. This number of bytes is copied from pvItemToQueue into the queue
|
||||
* itself.
|
||||
*
|
||||
* @param xTickToDelay The number of ticks that the co-routine should block
|
||||
* to wait for space to become available on the queue, should space not be
|
||||
* available immediately. The actual amount of time this equates to is defined
|
||||
* by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
|
||||
* portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
|
||||
* below).
|
||||
*
|
||||
* @param pxResult The variable pointed to by pxResult will be set to pdPASS if
|
||||
* data was successfully posted onto the queue, otherwise it will be set to an
|
||||
* error defined within ProjDefs.h.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Co-routine function that blocks for a fixed period then posts a number onto
|
||||
// a queue.
|
||||
static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||
static BaseType_t xNumberToPost = 0;
|
||||
static BaseType_t xResult;
|
||||
|
||||
// Co-routines must begin with a call to crSTART().
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// This assumes the queue has already been created.
|
||||
crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
|
||||
|
||||
if( xResult != pdPASS )
|
||||
{
|
||||
// The message was not posted!
|
||||
}
|
||||
|
||||
// Increment the number to be posted onto the queue.
|
||||
xNumberToPost++;
|
||||
|
||||
// Delay for 100 ticks.
|
||||
crDELAY( xHandle, 100 );
|
||||
}
|
||||
|
||||
// Co-routines must end with a call to crEND().
|
||||
crEND();
|
||||
}</pre>
|
||||
* \defgroup crQUEUE_SEND crQUEUE_SEND
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \
|
||||
{ \
|
||||
*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) ); \
|
||||
if( *( pxResult ) == errQUEUE_BLOCKED ) \
|
||||
{ \
|
||||
crSET_STATE0( ( xHandle ) ); \
|
||||
*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \
|
||||
} \
|
||||
if( *pxResult == errQUEUE_YIELD ) \
|
||||
{ \
|
||||
crSET_STATE1( ( xHandle ) ); \
|
||||
*pxResult = pdPASS; \
|
||||
} \
|
||||
}
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
* <pre>
|
||||
crQUEUE_RECEIVE(
|
||||
CoRoutineHandle_t xHandle,
|
||||
QueueHandle_t pxQueue,
|
||||
void *pvBuffer,
|
||||
TickType_t xTicksToWait,
|
||||
BaseType_t *pxResult
|
||||
)</pre>
|
||||
*
|
||||
* The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
|
||||
* equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
|
||||
*
|
||||
* crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
|
||||
* xQueueSend() and xQueueReceive() can only be used from tasks.
|
||||
*
|
||||
* crQUEUE_RECEIVE can only be called from the co-routine function itself - not
|
||||
* from within a function called by the co-routine function. This is because
|
||||
* co-routines do not maintain their own stack.
|
||||
*
|
||||
* See the co-routine section of the WEB documentation for information on
|
||||
* passing data between tasks and co-routines and between ISR's and
|
||||
* co-routines.
|
||||
*
|
||||
* @param xHandle The handle of the calling co-routine. This is the xHandle
|
||||
* parameter of the co-routine function.
|
||||
*
|
||||
* @param pxQueue The handle of the queue from which the data will be received.
|
||||
* The handle is obtained as the return value when the queue is created using
|
||||
* the xQueueCreate() API function.
|
||||
*
|
||||
* @param pvBuffer The buffer into which the received item is to be copied.
|
||||
* The number of bytes of each queued item is specified when the queue is
|
||||
* created. This number of bytes is copied into pvBuffer.
|
||||
*
|
||||
* @param xTickToDelay The number of ticks that the co-routine should block
|
||||
* to wait for data to become available from the queue, should data not be
|
||||
* available immediately. The actual amount of time this equates to is defined
|
||||
* by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
|
||||
* portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
|
||||
* crQUEUE_SEND example).
|
||||
*
|
||||
* @param pxResult The variable pointed to by pxResult will be set to pdPASS if
|
||||
* data was successfully retrieved from the queue, otherwise it will be set to
|
||||
* an error code as defined within ProjDefs.h.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// A co-routine receives the number of an LED to flash from a queue. It
|
||||
// blocks on the queue until the number is received.
|
||||
static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||
static BaseType_t xResult;
|
||||
static UBaseType_t uxLEDToFlash;
|
||||
|
||||
// All co-routines must start with a call to crSTART().
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Wait for data to become available on the queue.
|
||||
crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
|
||||
|
||||
if( xResult == pdPASS )
|
||||
{
|
||||
// We received the LED to flash - flash it!
|
||||
vParTestToggleLED( uxLEDToFlash );
|
||||
}
|
||||
}
|
||||
|
||||
crEND();
|
||||
}</pre>
|
||||
* \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \
|
||||
{ \
|
||||
*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) ); \
|
||||
if( *( pxResult ) == errQUEUE_BLOCKED ) \
|
||||
{ \
|
||||
crSET_STATE0( ( xHandle ) ); \
|
||||
*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 ); \
|
||||
} \
|
||||
if( *( pxResult ) == errQUEUE_YIELD ) \
|
||||
{ \
|
||||
crSET_STATE1( ( xHandle ) ); \
|
||||
*( pxResult ) = pdPASS; \
|
||||
} \
|
||||
}
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
* <pre>
|
||||
crQUEUE_SEND_FROM_ISR(
|
||||
QueueHandle_t pxQueue,
|
||||
void *pvItemToQueue,
|
||||
BaseType_t xCoRoutinePreviouslyWoken
|
||||
)</pre>
|
||||
*
|
||||
* The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
|
||||
* co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
|
||||
* functions used by tasks.
|
||||
*
|
||||
* crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
|
||||
* pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
|
||||
* xQueueReceiveFromISR() can only be used to pass data between a task and and
|
||||
* ISR.
|
||||
*
|
||||
* crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
|
||||
* that is being used from within a co-routine.
|
||||
*
|
||||
* See the co-routine section of the WEB documentation for information on
|
||||
* passing data between tasks and co-routines and between ISR's and
|
||||
* co-routines.
|
||||
*
|
||||
* @param xQueue The handle to the queue on which the item is to be posted.
|
||||
*
|
||||
* @param pvItemToQueue A pointer to the item that is to be placed on the
|
||||
* queue. The size of the items the queue will hold was defined when the
|
||||
* queue was created, so this many bytes will be copied from pvItemToQueue
|
||||
* into the queue storage area.
|
||||
*
|
||||
* @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
|
||||
* the same queue multiple times from a single interrupt. The first call
|
||||
* should always pass in pdFALSE. Subsequent calls should pass in
|
||||
* the value returned from the previous call.
|
||||
*
|
||||
* @return pdTRUE if a co-routine was woken by posting onto the queue. This is
|
||||
* used by the ISR to determine if a context switch may be required following
|
||||
* the ISR.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// A co-routine that blocks on a queue waiting for characters to be received.
|
||||
static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
char cRxedChar;
|
||||
BaseType_t xResult;
|
||||
|
||||
// All co-routines must start with a call to crSTART().
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Wait for data to become available on the queue. This assumes the
|
||||
// queue xCommsRxQueue has already been created!
|
||||
crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
|
||||
|
||||
// Was a character received?
|
||||
if( xResult == pdPASS )
|
||||
{
|
||||
// Process the character here.
|
||||
}
|
||||
}
|
||||
|
||||
// All co-routines must end with a call to crEND().
|
||||
crEND();
|
||||
}
|
||||
|
||||
// An ISR that uses a queue to send characters received on a serial port to
|
||||
// a co-routine.
|
||||
void vUART_ISR( void )
|
||||
{
|
||||
char cRxedChar;
|
||||
BaseType_t xCRWokenByPost = pdFALSE;
|
||||
|
||||
// We loop around reading characters until there are none left in the UART.
|
||||
while( UART_RX_REG_NOT_EMPTY() )
|
||||
{
|
||||
// Obtain the character from the UART.
|
||||
cRxedChar = UART_RX_REG;
|
||||
|
||||
// Post the character onto a queue. xCRWokenByPost will be pdFALSE
|
||||
// the first time around the loop. If the post causes a co-routine
|
||||
// to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
|
||||
// In this manner we can ensure that if more than one co-routine is
|
||||
// blocked on the queue only one is woken by this ISR no matter how
|
||||
// many characters are posted to the queue.
|
||||
xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
|
||||
}
|
||||
}</pre>
|
||||
* \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
|
||||
|
||||
|
||||
/**
|
||||
* croutine. h
|
||||
* <pre>
|
||||
crQUEUE_SEND_FROM_ISR(
|
||||
QueueHandle_t pxQueue,
|
||||
void *pvBuffer,
|
||||
BaseType_t * pxCoRoutineWoken
|
||||
)</pre>
|
||||
*
|
||||
* The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
|
||||
* co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
|
||||
* functions used by tasks.
|
||||
*
|
||||
* crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
|
||||
* pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
|
||||
* xQueueReceiveFromISR() can only be used to pass data between a task and and
|
||||
* ISR.
|
||||
*
|
||||
* crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
|
||||
* from a queue that is being used from within a co-routine (a co-routine
|
||||
* posted to the queue).
|
||||
*
|
||||
* See the co-routine section of the WEB documentation for information on
|
||||
* passing data between tasks and co-routines and between ISR's and
|
||||
* co-routines.
|
||||
*
|
||||
* @param xQueue The handle to the queue on which the item is to be posted.
|
||||
*
|
||||
* @param pvBuffer A pointer to a buffer into which the received item will be
|
||||
* placed. The size of the items the queue will hold was defined when the
|
||||
* queue was created, so this many bytes will be copied from the queue into
|
||||
* pvBuffer.
|
||||
*
|
||||
* @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
|
||||
* available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a
|
||||
* co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
|
||||
* *pxCoRoutineWoken will remain unchanged.
|
||||
*
|
||||
* @return pdTRUE an item was successfully received from the queue, otherwise
|
||||
* pdFALSE.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// A co-routine that posts a character to a queue then blocks for a fixed
|
||||
// period. The character is incremented each time.
|
||||
static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||
{
|
||||
// cChar holds its value while this co-routine is blocked and must therefore
|
||||
// be declared static.
|
||||
static char cCharToTx = 'a';
|
||||
BaseType_t xResult;
|
||||
|
||||
// All co-routines must start with a call to crSTART().
|
||||
crSTART( xHandle );
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Send the next character to the queue.
|
||||
crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
|
||||
|
||||
if( xResult == pdPASS )
|
||||
{
|
||||
// The character was successfully posted to the queue.
|
||||
}
|
||||
else
|
||||
{
|
||||
// Could not post the character to the queue.
|
||||
}
|
||||
|
||||
// Enable the UART Tx interrupt to cause an interrupt in this
|
||||
// hypothetical UART. The interrupt will obtain the character
|
||||
// from the queue and send it.
|
||||
ENABLE_RX_INTERRUPT();
|
||||
|
||||
// Increment to the next character then block for a fixed period.
|
||||
// cCharToTx will maintain its value across the delay as it is
|
||||
// declared static.
|
||||
cCharToTx++;
|
||||
if( cCharToTx > 'x' )
|
||||
{
|
||||
cCharToTx = 'a';
|
||||
}
|
||||
crDELAY( 100 );
|
||||
}
|
||||
|
||||
// All co-routines must end with a call to crEND().
|
||||
crEND();
|
||||
}
|
||||
|
||||
// An ISR that uses a queue to receive characters to send on a UART.
|
||||
void vUART_ISR( void )
|
||||
{
|
||||
char cCharToTx;
|
||||
BaseType_t xCRWokenByPost = pdFALSE;
|
||||
|
||||
while( UART_TX_REG_EMPTY() )
|
||||
{
|
||||
// Are there any characters in the queue waiting to be sent?
|
||||
// xCRWokenByPost will automatically be set to pdTRUE if a co-routine
|
||||
// is woken by the post - ensuring that only a single co-routine is
|
||||
// woken no matter how many times we go around this loop.
|
||||
if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
|
||||
{
|
||||
SEND_CHARACTER( cCharToTx );
|
||||
}
|
||||
}
|
||||
}</pre>
|
||||
* \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
|
||||
* \ingroup Tasks
|
||||
*/
|
||||
#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
|
||||
|
||||
/*
|
||||
* This function is intended for internal use by the co-routine macros only.
|
||||
* The macro nature of the co-routine implementation requires that the
|
||||
* prototype appears here. The function should not be used by application
|
||||
* writers.
|
||||
*
|
||||
* Removes the current co-routine from its ready list and places it in the
|
||||
* appropriate delayed list.
|
||||
*/
|
||||
void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
|
||||
|
||||
/*
|
||||
* This function is intended for internal use by the queue implementation only.
|
||||
* The function should not be used by application writers.
|
||||
*
|
||||
* Removes the highest priority co-routine from the event list and places it in
|
||||
* the pending ready list.
|
||||
*/
|
||||
BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CO_ROUTINE_H */
|
|
@ -0,0 +1,770 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef EVENT_GROUPS_H
|
||||
#define EVENT_GROUPS_H
|
||||
|
||||
#ifndef INC_FREERTOS_H
|
||||
#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
|
||||
#endif
|
||||
|
||||
/* FreeRTOS includes. */
|
||||
#include "timers.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* An event group is a collection of bits to which an application can assign a
|
||||
* meaning. For example, an application may create an event group to convey
|
||||
* the status of various CAN bus related events in which bit 0 might mean "A CAN
|
||||
* message has been received and is ready for processing", bit 1 might mean "The
|
||||
* application has queued a message that is ready for sending onto the CAN
|
||||
* network", and bit 2 might mean "It is time to send a SYNC message onto the
|
||||
* CAN network" etc. A task can then test the bit values to see which events
|
||||
* are active, and optionally enter the Blocked state to wait for a specified
|
||||
* bit or a group of specified bits to be active. To continue the CAN bus
|
||||
* example, a CAN controlling task can enter the Blocked state (and therefore
|
||||
* not consume any processing time) until either bit 0, bit 1 or bit 2 are
|
||||
* active, at which time the bit that was actually active would inform the task
|
||||
* which action it had to take (process a received message, send a message, or
|
||||
* send a SYNC).
|
||||
*
|
||||
* The event groups implementation contains intelligence to avoid race
|
||||
* conditions that would otherwise occur were an application to use a simple
|
||||
* variable for the same purpose. This is particularly important with respect
|
||||
* to when a bit within an event group is to be cleared, and when bits have to
|
||||
* be set and then tested atomically - as is the case where event groups are
|
||||
* used to create a synchronisation point between multiple tasks (a
|
||||
* 'rendezvous').
|
||||
*
|
||||
* \defgroup EventGroup
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*
|
||||
* Type by which event groups are referenced. For example, a call to
|
||||
* xEventGroupCreate() returns an EventGroupHandle_t variable that can then
|
||||
* be used as a parameter to other event group functions.
|
||||
*
|
||||
* \defgroup EventGroupHandle_t EventGroupHandle_t
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
typedef void * EventGroupHandle_t;
|
||||
|
||||
/*
|
||||
* The type that holds event bits always matches TickType_t - therefore the
|
||||
* number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
|
||||
* 32 bits if set to 0.
|
||||
*
|
||||
* \defgroup EventBits_t EventBits_t
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
typedef TickType_t EventBits_t;
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventGroupHandle_t xEventGroupCreate( void );
|
||||
</pre>
|
||||
*
|
||||
* Create a new event group.
|
||||
*
|
||||
* Internally, within the FreeRTOS implementation, event groups use a [small]
|
||||
* block of memory, in which the event group's structure is stored. If an event
|
||||
* groups is created using xEventGropuCreate() then the required memory is
|
||||
* automatically dynamically allocated inside the xEventGroupCreate() function.
|
||||
* (see http://www.freertos.org/a00111.html). If an event group is created
|
||||
* using xEventGropuCreateStatic() then the application writer must instead
|
||||
* provide the memory that will get used by the event group.
|
||||
* xEventGroupCreateStatic() therefore allows an event group to be created
|
||||
* without using any dynamic memory allocation.
|
||||
*
|
||||
* Although event groups are not related to ticks, for internal implementation
|
||||
* reasons the number of bits available for use in an event group is dependent
|
||||
* on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
|
||||
* configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
|
||||
* 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
|
||||
* 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
|
||||
* event bits within an event group.
|
||||
*
|
||||
* @return If the event group was created then a handle to the event group is
|
||||
* returned. If there was insufficient FreeRTOS heap available to create the
|
||||
* event group then NULL is returned. See http://www.freertos.org/a00111.html
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Declare a variable to hold the created event group.
|
||||
EventGroupHandle_t xCreatedEventGroup;
|
||||
|
||||
// Attempt to create the event group.
|
||||
xCreatedEventGroup = xEventGroupCreate();
|
||||
|
||||
// Was the event group created successfully?
|
||||
if( xCreatedEventGroup == NULL )
|
||||
{
|
||||
// The event group was not created because there was insufficient
|
||||
// FreeRTOS heap available.
|
||||
}
|
||||
else
|
||||
{
|
||||
// The event group was created.
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xEventGroupCreate xEventGroupCreate
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||||
EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
|
||||
</pre>
|
||||
*
|
||||
* Create a new event group.
|
||||
*
|
||||
* Internally, within the FreeRTOS implementation, event groups use a [small]
|
||||
* block of memory, in which the event group's structure is stored. If an event
|
||||
* groups is created using xEventGropuCreate() then the required memory is
|
||||
* automatically dynamically allocated inside the xEventGroupCreate() function.
|
||||
* (see http://www.freertos.org/a00111.html). If an event group is created
|
||||
* using xEventGropuCreateStatic() then the application writer must instead
|
||||
* provide the memory that will get used by the event group.
|
||||
* xEventGroupCreateStatic() therefore allows an event group to be created
|
||||
* without using any dynamic memory allocation.
|
||||
*
|
||||
* Although event groups are not related to ticks, for internal implementation
|
||||
* reasons the number of bits available for use in an event group is dependent
|
||||
* on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
|
||||
* configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
|
||||
* 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
|
||||
* 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
|
||||
* event bits within an event group.
|
||||
*
|
||||
* @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
|
||||
* StaticEventGroup_t, which will be then be used to hold the event group's data
|
||||
* structures, removing the need for the memory to be allocated dynamically.
|
||||
*
|
||||
* @return If the event group was created then a handle to the event group is
|
||||
* returned. If pxEventGroupBuffer was NULL then NULL is returned.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// StaticEventGroup_t is a publicly accessible structure that has the same
|
||||
// size and alignment requirements as the real event group structure. It is
|
||||
// provided as a mechanism for applications to know the size of the event
|
||||
// group (which is dependent on the architecture and configuration file
|
||||
// settings) without breaking the strict data hiding policy by exposing the
|
||||
// real event group internals. This StaticEventGroup_t variable is passed
|
||||
// into the xSemaphoreCreateEventGroupStatic() function and is used to store
|
||||
// the event group's data structures
|
||||
StaticEventGroup_t xEventGroupBuffer;
|
||||
|
||||
// Create the event group without dynamically allocating any memory.
|
||||
xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
|
||||
</pre>
|
||||
*/
|
||||
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||||
EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
|
||||
const EventBits_t uxBitsToWaitFor,
|
||||
const BaseType_t xClearOnExit,
|
||||
const BaseType_t xWaitForAllBits,
|
||||
const TickType_t xTicksToWait );
|
||||
</pre>
|
||||
*
|
||||
* [Potentially] block to wait for one or more bits to be set within a
|
||||
* previously created event group.
|
||||
*
|
||||
* This function cannot be called from an interrupt.
|
||||
*
|
||||
* @param xEventGroup The event group in which the bits are being tested. The
|
||||
* event group must have previously been created using a call to
|
||||
* xEventGroupCreate().
|
||||
*
|
||||
* @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
|
||||
* inside the event group. For example, to wait for bit 0 and/or bit 2 set
|
||||
* uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set
|
||||
* uxBitsToWaitFor to 0x07. Etc.
|
||||
*
|
||||
* @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
|
||||
* uxBitsToWaitFor that are set within the event group will be cleared before
|
||||
* xEventGroupWaitBits() returns if the wait condition was met (if the function
|
||||
* returns for a reason other than a timeout). If xClearOnExit is set to
|
||||
* pdFALSE then the bits set in the event group are not altered when the call to
|
||||
* xEventGroupWaitBits() returns.
|
||||
*
|
||||
* @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
|
||||
* xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
|
||||
* are set or the specified block time expires. If xWaitForAllBits is set to
|
||||
* pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
|
||||
* in uxBitsToWaitFor is set or the specified block time expires. The block
|
||||
* time is specified by the xTicksToWait parameter.
|
||||
*
|
||||
* @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
|
||||
* for one/all (depending on the xWaitForAllBits value) of the bits specified by
|
||||
* uxBitsToWaitFor to become set.
|
||||
*
|
||||
* @return The value of the event group at the time either the bits being waited
|
||||
* for became set, or the block time expired. Test the return value to know
|
||||
* which bits were set. If xEventGroupWaitBits() returned because its timeout
|
||||
* expired then not all the bits being waited for will be set. If
|
||||
* xEventGroupWaitBits() returned because the bits it was waiting for were set
|
||||
* then the returned value is the event group value before any bits were
|
||||
* automatically cleared in the case that xClearOnExit parameter was set to
|
||||
* pdTRUE.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
#define BIT_0 ( 1 << 0 )
|
||||
#define BIT_4 ( 1 << 4 )
|
||||
|
||||
void aFunction( EventGroupHandle_t xEventGroup )
|
||||
{
|
||||
EventBits_t uxBits;
|
||||
const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
|
||||
|
||||
// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
|
||||
// the event group. Clear the bits before exiting.
|
||||
uxBits = xEventGroupWaitBits(
|
||||
xEventGroup, // The event group being tested.
|
||||
BIT_0 | BIT_4, // The bits within the event group to wait for.
|
||||
pdTRUE, // BIT_0 and BIT_4 should be cleared before returning.
|
||||
pdFALSE, // Don't wait for both bits, either bit will do.
|
||||
xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
|
||||
|
||||
if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
|
||||
{
|
||||
// xEventGroupWaitBits() returned because both bits were set.
|
||||
}
|
||||
else if( ( uxBits & BIT_0 ) != 0 )
|
||||
{
|
||||
// xEventGroupWaitBits() returned because just BIT_0 was set.
|
||||
}
|
||||
else if( ( uxBits & BIT_4 ) != 0 )
|
||||
{
|
||||
// xEventGroupWaitBits() returned because just BIT_4 was set.
|
||||
}
|
||||
else
|
||||
{
|
||||
// xEventGroupWaitBits() returned because xTicksToWait ticks passed
|
||||
// without either BIT_0 or BIT_4 becoming set.
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xEventGroupWaitBits xEventGroupWaitBits
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
|
||||
</pre>
|
||||
*
|
||||
* Clear bits within an event group. This function cannot be called from an
|
||||
* interrupt.
|
||||
*
|
||||
* @param xEventGroup The event group in which the bits are to be cleared.
|
||||
*
|
||||
* @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
|
||||
* in the event group. For example, to clear bit 3 only, set uxBitsToClear to
|
||||
* 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
|
||||
*
|
||||
* @return The value of the event group before the specified bits were cleared.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
#define BIT_0 ( 1 << 0 )
|
||||
#define BIT_4 ( 1 << 4 )
|
||||
|
||||
void aFunction( EventGroupHandle_t xEventGroup )
|
||||
{
|
||||
EventBits_t uxBits;
|
||||
|
||||
// Clear bit 0 and bit 4 in xEventGroup.
|
||||
uxBits = xEventGroupClearBits(
|
||||
xEventGroup, // The event group being updated.
|
||||
BIT_0 | BIT_4 );// The bits being cleared.
|
||||
|
||||
if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
|
||||
{
|
||||
// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
|
||||
// called. Both will now be clear (not set).
|
||||
}
|
||||
else if( ( uxBits & BIT_0 ) != 0 )
|
||||
{
|
||||
// Bit 0 was set before xEventGroupClearBits() was called. It will
|
||||
// now be clear.
|
||||
}
|
||||
else if( ( uxBits & BIT_4 ) != 0 )
|
||||
{
|
||||
// Bit 4 was set before xEventGroupClearBits() was called. It will
|
||||
// now be clear.
|
||||
}
|
||||
else
|
||||
{
|
||||
// Neither bit 0 nor bit 4 were set in the first place.
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xEventGroupClearBits xEventGroupClearBits
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
|
||||
</pre>
|
||||
*
|
||||
* A version of xEventGroupClearBits() that can be called from an interrupt.
|
||||
*
|
||||
* Setting bits in an event group is not a deterministic operation because there
|
||||
* are an unknown number of tasks that may be waiting for the bit or bits being
|
||||
* set. FreeRTOS does not allow nondeterministic operations to be performed
|
||||
* while interrupts are disabled, so protects event groups that are accessed
|
||||
* from tasks by suspending the scheduler rather than disabling interrupts. As
|
||||
* a result event groups cannot be accessed directly from an interrupt service
|
||||
* routine. Therefore xEventGroupClearBitsFromISR() sends a message to the
|
||||
* timer task to have the clear operation performed in the context of the timer
|
||||
* task.
|
||||
*
|
||||
* @param xEventGroup The event group in which the bits are to be cleared.
|
||||
*
|
||||
* @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
|
||||
* For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3
|
||||
* and bit 0 set uxBitsToClear to 0x09.
|
||||
*
|
||||
* @return If the request to execute the function was posted successfully then
|
||||
* pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned
|
||||
* if the timer service queue was full.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
#define BIT_0 ( 1 << 0 )
|
||||
#define BIT_4 ( 1 << 4 )
|
||||
|
||||
// An event group which it is assumed has already been created by a call to
|
||||
// xEventGroupCreate().
|
||||
EventGroupHandle_t xEventGroup;
|
||||
|
||||
void anInterruptHandler( void )
|
||||
{
|
||||
// Clear bit 0 and bit 4 in xEventGroup.
|
||||
xResult = xEventGroupClearBitsFromISR(
|
||||
xEventGroup, // The event group being updated.
|
||||
BIT_0 | BIT_4 ); // The bits being set.
|
||||
|
||||
if( xResult == pdPASS )
|
||||
{
|
||||
// The message was posted successfully.
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
#if( configUSE_TRACE_FACILITY == 1 )
|
||||
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
|
||||
#else
|
||||
#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
|
||||
</pre>
|
||||
*
|
||||
* Set bits within an event group.
|
||||
* This function cannot be called from an interrupt. xEventGroupSetBitsFromISR()
|
||||
* is a version that can be called from an interrupt.
|
||||
*
|
||||
* Setting bits in an event group will automatically unblock tasks that are
|
||||
* blocked waiting for the bits.
|
||||
*
|
||||
* @param xEventGroup The event group in which the bits are to be set.
|
||||
*
|
||||
* @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
|
||||
* For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
|
||||
* and bit 0 set uxBitsToSet to 0x09.
|
||||
*
|
||||
* @return The value of the event group at the time the call to
|
||||
* xEventGroupSetBits() returns. There are two reasons why the returned value
|
||||
* might have the bits specified by the uxBitsToSet parameter cleared. First,
|
||||
* if setting a bit results in a task that was waiting for the bit leaving the
|
||||
* blocked state then it is possible the bit will be cleared automatically
|
||||
* (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any
|
||||
* unblocked (or otherwise Ready state) task that has a priority above that of
|
||||
* the task that called xEventGroupSetBits() will execute and may change the
|
||||
* event group value before the call to xEventGroupSetBits() returns.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
#define BIT_0 ( 1 << 0 )
|
||||
#define BIT_4 ( 1 << 4 )
|
||||
|
||||
void aFunction( EventGroupHandle_t xEventGroup )
|
||||
{
|
||||
EventBits_t uxBits;
|
||||
|
||||
// Set bit 0 and bit 4 in xEventGroup.
|
||||
uxBits = xEventGroupSetBits(
|
||||
xEventGroup, // The event group being updated.
|
||||
BIT_0 | BIT_4 );// The bits being set.
|
||||
|
||||
if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
|
||||
{
|
||||
// Both bit 0 and bit 4 remained set when the function returned.
|
||||
}
|
||||
else if( ( uxBits & BIT_0 ) != 0 )
|
||||
{
|
||||
// Bit 0 remained set when the function returned, but bit 4 was
|
||||
// cleared. It might be that bit 4 was cleared automatically as a
|
||||
// task that was waiting for bit 4 was removed from the Blocked
|
||||
// state.
|
||||
}
|
||||
else if( ( uxBits & BIT_4 ) != 0 )
|
||||
{
|
||||
// Bit 4 remained set when the function returned, but bit 0 was
|
||||
// cleared. It might be that bit 0 was cleared automatically as a
|
||||
// task that was waiting for bit 0 was removed from the Blocked
|
||||
// state.
|
||||
}
|
||||
else
|
||||
{
|
||||
// Neither bit 0 nor bit 4 remained set. It might be that a task
|
||||
// was waiting for both of the bits to be set, and the bits were
|
||||
// cleared as the task left the Blocked state.
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xEventGroupSetBits xEventGroupSetBits
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
|
||||
</pre>
|
||||
*
|
||||
* A version of xEventGroupSetBits() that can be called from an interrupt.
|
||||
*
|
||||
* Setting bits in an event group is not a deterministic operation because there
|
||||
* are an unknown number of tasks that may be waiting for the bit or bits being
|
||||
* set. FreeRTOS does not allow nondeterministic operations to be performed in
|
||||
* interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR()
|
||||
* sends a message to the timer task to have the set operation performed in the
|
||||
* context of the timer task - where a scheduler lock is used in place of a
|
||||
* critical section.
|
||||
*
|
||||
* @param xEventGroup The event group in which the bits are to be set.
|
||||
*
|
||||
* @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
|
||||
* For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
|
||||
* and bit 0 set uxBitsToSet to 0x09.
|
||||
*
|
||||
* @param pxHigherPriorityTaskWoken As mentioned above, calling this function
|
||||
* will result in a message being sent to the timer daemon task. If the
|
||||
* priority of the timer daemon task is higher than the priority of the
|
||||
* currently running task (the task the interrupt interrupted) then
|
||||
* *pxHigherPriorityTaskWoken will be set to pdTRUE by
|
||||
* xEventGroupSetBitsFromISR(), indicating that a context switch should be
|
||||
* requested before the interrupt exits. For that reason
|
||||
* *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the
|
||||
* example code below.
|
||||
*
|
||||
* @return If the request to execute the function was posted successfully then
|
||||
* pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned
|
||||
* if the timer service queue was full.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
#define BIT_0 ( 1 << 0 )
|
||||
#define BIT_4 ( 1 << 4 )
|
||||
|
||||
// An event group which it is assumed has already been created by a call to
|
||||
// xEventGroupCreate().
|
||||
EventGroupHandle_t xEventGroup;
|
||||
|
||||
void anInterruptHandler( void )
|
||||
{
|
||||
BaseType_t xHigherPriorityTaskWoken, xResult;
|
||||
|
||||
// xHigherPriorityTaskWoken must be initialised to pdFALSE.
|
||||
xHigherPriorityTaskWoken = pdFALSE;
|
||||
|
||||
// Set bit 0 and bit 4 in xEventGroup.
|
||||
xResult = xEventGroupSetBitsFromISR(
|
||||
xEventGroup, // The event group being updated.
|
||||
BIT_0 | BIT_4 // The bits being set.
|
||||
&xHigherPriorityTaskWoken );
|
||||
|
||||
// Was the message posted successfully?
|
||||
if( xResult == pdPASS )
|
||||
{
|
||||
// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
|
||||
// switch should be requested. The macro used is port specific and
|
||||
// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
|
||||
// refer to the documentation page for the port being used.
|
||||
portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
#if( configUSE_TRACE_FACILITY == 1 )
|
||||
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
|
||||
#else
|
||||
#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
|
||||
#endif
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
|
||||
const EventBits_t uxBitsToSet,
|
||||
const EventBits_t uxBitsToWaitFor,
|
||||
TickType_t xTicksToWait );
|
||||
</pre>
|
||||
*
|
||||
* Atomically set bits within an event group, then wait for a combination of
|
||||
* bits to be set within the same event group. This functionality is typically
|
||||
* used to synchronise multiple tasks, where each task has to wait for the other
|
||||
* tasks to reach a synchronisation point before proceeding.
|
||||
*
|
||||
* This function cannot be used from an interrupt.
|
||||
*
|
||||
* The function will return before its block time expires if the bits specified
|
||||
* by the uxBitsToWait parameter are set, or become set within that time. In
|
||||
* this case all the bits specified by uxBitsToWait will be automatically
|
||||
* cleared before the function returns.
|
||||
*
|
||||
* @param xEventGroup The event group in which the bits are being tested. The
|
||||
* event group must have previously been created using a call to
|
||||
* xEventGroupCreate().
|
||||
*
|
||||
* @param uxBitsToSet The bits to set in the event group before determining
|
||||
* if, and possibly waiting for, all the bits specified by the uxBitsToWait
|
||||
* parameter are set.
|
||||
*
|
||||
* @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
|
||||
* inside the event group. For example, to wait for bit 0 and bit 2 set
|
||||
* uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set
|
||||
* uxBitsToWaitFor to 0x07. Etc.
|
||||
*
|
||||
* @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
|
||||
* for all of the bits specified by uxBitsToWaitFor to become set.
|
||||
*
|
||||
* @return The value of the event group at the time either the bits being waited
|
||||
* for became set, or the block time expired. Test the return value to know
|
||||
* which bits were set. If xEventGroupSync() returned because its timeout
|
||||
* expired then not all the bits being waited for will be set. If
|
||||
* xEventGroupSync() returned because all the bits it was waiting for were
|
||||
* set then the returned value is the event group value before any bits were
|
||||
* automatically cleared.
|
||||
*
|
||||
* Example usage:
|
||||
<pre>
|
||||
// Bits used by the three tasks.
|
||||
#define TASK_0_BIT ( 1 << 0 )
|
||||
#define TASK_1_BIT ( 1 << 1 )
|
||||
#define TASK_2_BIT ( 1 << 2 )
|
||||
|
||||
#define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
|
||||
|
||||
// Use an event group to synchronise three tasks. It is assumed this event
|
||||
// group has already been created elsewhere.
|
||||
EventGroupHandle_t xEventBits;
|
||||
|
||||
void vTask0( void *pvParameters )
|
||||
{
|
||||
EventBits_t uxReturn;
|
||||
TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
|
||||
|
||||
for( ;; )
|
||||
{
|
||||
// Perform task functionality here.
|
||||
|
||||
// Set bit 0 in the event flag to note this task has reached the
|
||||
// sync point. The other two tasks will set the other two bits defined
|
||||
// by ALL_SYNC_BITS. All three tasks have reached the synchronisation
|
||||
// point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms
|
||||
// for this to happen.
|
||||
uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
|
||||
|
||||
if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
|
||||
{
|
||||
// All three tasks reached the synchronisation point before the call
|
||||
// to xEventGroupSync() timed out.
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void vTask1( void *pvParameters )
|
||||
{
|
||||
for( ;; )
|
||||
{
|
||||
// Perform task functionality here.
|
||||
|
||||
// Set bit 1 in the event flag to note this task has reached the
|
||||
// synchronisation point. The other two tasks will set the other two
|
||||
// bits defined by ALL_SYNC_BITS. All three tasks have reached the
|
||||
// synchronisation point when all the ALL_SYNC_BITS are set. Wait
|
||||
// indefinitely for this to happen.
|
||||
xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
|
||||
|
||||
// xEventGroupSync() was called with an indefinite block time, so
|
||||
// this task will only reach here if the syncrhonisation was made by all
|
||||
// three tasks, so there is no need to test the return value.
|
||||
}
|
||||
}
|
||||
|
||||
void vTask2( void *pvParameters )
|
||||
{
|
||||
for( ;; )
|
||||
{
|
||||
// Perform task functionality here.
|
||||
|
||||
// Set bit 2 in the event flag to note this task has reached the
|
||||
// synchronisation point. The other two tasks will set the other two
|
||||
// bits defined by ALL_SYNC_BITS. All three tasks have reached the
|
||||
// synchronisation point when all the ALL_SYNC_BITS are set. Wait
|
||||
// indefinitely for this to happen.
|
||||
xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
|
||||
|
||||
// xEventGroupSync() was called with an indefinite block time, so
|
||||
// this task will only reach here if the syncrhonisation was made by all
|
||||
// three tasks, so there is no need to test the return value.
|
||||
}
|
||||
}
|
||||
|
||||
</pre>
|
||||
* \defgroup xEventGroupSync xEventGroupSync
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
|
||||
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
|
||||
</pre>
|
||||
*
|
||||
* Returns the current value of the bits in an event group. This function
|
||||
* cannot be used from an interrupt.
|
||||
*
|
||||
* @param xEventGroup The event group being queried.
|
||||
*
|
||||
* @return The event group bits at the time xEventGroupGetBits() was called.
|
||||
*
|
||||
* \defgroup xEventGroupGetBits xEventGroupGetBits
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
|
||||
</pre>
|
||||
*
|
||||
* A version of xEventGroupGetBits() that can be called from an ISR.
|
||||
*
|
||||
* @param xEventGroup The event group being queried.
|
||||
*
|
||||
* @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
|
||||
*
|
||||
* \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
|
||||
* \ingroup EventGroup
|
||||
*/
|
||||
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/**
|
||||
* event_groups.h
|
||||
*<pre>
|
||||
void xEventGroupDelete( EventGroupHandle_t xEventGroup );
|
||||
</pre>
|
||||
*
|
||||
* Delete an event group that was previously created by a call to
|
||||
* xEventGroupCreate(). Tasks that are blocked on the event group will be
|
||||
* unblocked and obtain 0 as the event group's value.
|
||||
*
|
||||
* @param xEventGroup The event group being deleted.
|
||||
*/
|
||||
void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/* For internal use only. */
|
||||
void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
|
||||
void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
|
||||
|
||||
|
||||
#if (configUSE_TRACE_FACILITY == 1)
|
||||
UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
|
||||
void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* EVENT_GROUPS_H */
|
||||
|
||||
|
|
@ -0,0 +1,425 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* This is the list implementation used by the scheduler. While it is tailored
|
||||
* heavily for the schedulers needs, it is also available for use by
|
||||
* application code.
|
||||
*
|
||||
* list_ts can only store pointers to list_item_ts. Each ListItem_t contains a
|
||||
* numeric value (xItemValue). Most of the time the lists are sorted in
|
||||
* descending item value order.
|
||||
*
|
||||
* Lists are created already containing one list item. The value of this
|
||||
* item is the maximum possible that can be stored, it is therefore always at
|
||||
* the end of the list and acts as a marker. The list member pxHead always
|
||||
* points to this marker - even though it is at the tail of the list. This
|
||||
* is because the tail contains a wrap back pointer to the true head of
|
||||
* the list.
|
||||
*
|
||||
* In addition to it's value, each list item contains a pointer to the next
|
||||
* item in the list (pxNext), a pointer to the list it is in (pxContainer)
|
||||
* and a pointer to back to the object that contains it. These later two
|
||||
* pointers are included for efficiency of list manipulation. There is
|
||||
* effectively a two way link between the object containing the list item and
|
||||
* the list item itself.
|
||||
*
|
||||
*
|
||||
* \page ListIntroduction List Implementation
|
||||
* \ingroup FreeRTOSIntro
|
||||
*/
|
||||
|
||||
#ifndef INC_FREERTOS_H
|
||||
#error FreeRTOS.h must be included before list.h
|
||||
#endif
|
||||
|
||||
#ifndef LIST_H
|
||||
#define LIST_H
|
||||
|
||||
/*
|
||||
* The list structure members are modified from within interrupts, and therefore
|
||||
* by rights should be declared volatile. However, they are only modified in a
|
||||
* functionally atomic way (within critical sections of with the scheduler
|
||||
* suspended) and are either passed by reference into a function or indexed via
|
||||
* a volatile variable. Therefore, in all use cases tested so far, the volatile
|
||||
* qualifier can be omitted in order to provide a moderate performance
|
||||
* improvement without adversely affecting functional behaviour. The assembly
|
||||
* instructions generated by the IAR, ARM and GCC compilers when the respective
|
||||
* compiler's options were set for maximum optimisation has been inspected and
|
||||
* deemed to be as intended. That said, as compiler technology advances, and
|
||||
* especially if aggressive cross module optimisation is used (a use case that
|
||||
* has not been exercised to any great extend) then it is feasible that the
|
||||
* volatile qualifier will be needed for correct optimisation. It is expected
|
||||
* that a compiler removing essential code because, without the volatile
|
||||
* qualifier on the list structure members and with aggressive cross module
|
||||
* optimisation, the compiler deemed the code unnecessary will result in
|
||||
* complete and obvious failure of the scheduler. If this is ever experienced
|
||||
* then the volatile qualifier can be inserted in the relevant places within the
|
||||
* list structures by simply defining configLIST_VOLATILE to volatile in
|
||||
* FreeRTOSConfig.h (as per the example at the bottom of this comment block).
|
||||
* If configLIST_VOLATILE is not defined then the preprocessor directives below
|
||||
* will simply #define configLIST_VOLATILE away completely.
|
||||
*
|
||||
* To use volatile list structure members then add the following line to
|
||||
* FreeRTOSConfig.h (without the quotes):
|
||||
* "#define configLIST_VOLATILE volatile"
|
||||
*/
|
||||
#ifndef configLIST_VOLATILE
|
||||
#define configLIST_VOLATILE
|
||||
#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Macros that can be used to place known values within the list structures,
|
||||
then check that the known values do not get corrupted during the execution of
|
||||
the application. These may catch the list data structures being overwritten in
|
||||
memory. They will not catch data errors caused by incorrect configuration or
|
||||
use of FreeRTOS.*/
|
||||
#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
|
||||
/* Define the macros to do nothing. */
|
||||
#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
|
||||
#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
|
||||
#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
|
||||
#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
|
||||
#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
|
||||
#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
|
||||
#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
|
||||
#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
|
||||
#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
|
||||
#define listTEST_LIST_INTEGRITY( pxList )
|
||||
#else
|
||||
/* Define macros that add new members into the list structures. */
|
||||
#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1;
|
||||
#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2;
|
||||
#define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1;
|
||||
#define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2;
|
||||
|
||||
/* Define macros that set the new structure members to known values. */
|
||||
#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
|
||||
#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
|
||||
#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
|
||||
#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
|
||||
|
||||
/* Define macros that will assert if one of the structure members does not
|
||||
contain its expected value. */
|
||||
#define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
|
||||
#define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
|
||||
#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
|
||||
|
||||
|
||||
/*
|
||||
* Definition of the only type of object that a list can contain.
|
||||
*/
|
||||
struct xLIST_ITEM
|
||||
{
|
||||
listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */
|
||||
struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */
|
||||
struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */
|
||||
void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */
|
||||
void * configLIST_VOLATILE pvContainer; /*< Pointer to the list in which this list item is placed (if any). */
|
||||
listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
};
|
||||
typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
|
||||
|
||||
struct xMINI_LIST_ITEM
|
||||
{
|
||||
listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
configLIST_VOLATILE TickType_t xItemValue;
|
||||
struct xLIST_ITEM * configLIST_VOLATILE pxNext;
|
||||
struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
|
||||
};
|
||||
typedef struct xMINI_LIST_ITEM MiniListItem_t;
|
||||
|
||||
/*
|
||||
* Definition of the type of queue used by the scheduler.
|
||||
*/
|
||||
typedef struct xLIST
|
||||
{
|
||||
listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
volatile UBaseType_t uxNumberOfItems;
|
||||
ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
|
||||
MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
|
||||
listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||
} List_t;
|
||||
|
||||
/*
|
||||
* Access macro to set the owner of a list item. The owner of a list item
|
||||
* is the object (usually a TCB) that contains the list item.
|
||||
*
|
||||
* \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
|
||||
|
||||
/*
|
||||
* Access macro to get the owner of a list item. The owner of a list item
|
||||
* is the object (usually a TCB) that contains the list item.
|
||||
*
|
||||
* \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner )
|
||||
|
||||
/*
|
||||
* Access macro to set the value of the list item. In most cases the value is
|
||||
* used to sort the list in descending order.
|
||||
*
|
||||
* \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) )
|
||||
|
||||
/*
|
||||
* Access macro to retrieve the value of the list item. The value can
|
||||
* represent anything - for example the priority of a task, or the time at
|
||||
* which a task should be unblocked.
|
||||
*
|
||||
* \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )
|
||||
|
||||
/*
|
||||
* Access macro to retrieve the value of the list item at the head of a given
|
||||
* list.
|
||||
*
|
||||
* \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
|
||||
|
||||
/*
|
||||
* Return the list item at the head of the list.
|
||||
*
|
||||
* \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext )
|
||||
|
||||
/*
|
||||
* Return the list item at the head of the list.
|
||||
*
|
||||
* \page listGET_NEXT listGET_NEXT
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext )
|
||||
|
||||
/*
|
||||
* Return the list item that marks the end of the list
|
||||
*
|
||||
* \page listGET_END_MARKER listGET_END_MARKER
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
|
||||
|
||||
/*
|
||||
* Access macro to determine if a list contains any items. The macro will
|
||||
* only have the value true if the list is empty.
|
||||
*
|
||||
* \page listLIST_IS_EMPTY listLIST_IS_EMPTY
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listLIST_IS_EMPTY( pxList ) ( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )
|
||||
|
||||
/*
|
||||
* Access macro to return the number of items in the list.
|
||||
*/
|
||||
#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )
|
||||
|
||||
/*
|
||||
* Access function to obtain the owner of the next entry in a list.
|
||||
*
|
||||
* The list member pxIndex is used to walk through a list. Calling
|
||||
* listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
|
||||
* and returns that entry's pxOwner parameter. Using multiple calls to this
|
||||
* function it is therefore possible to move through every item contained in
|
||||
* a list.
|
||||
*
|
||||
* The pxOwner parameter of a list item is a pointer to the object that owns
|
||||
* the list item. In the scheduler this is normally a task control block.
|
||||
* The pxOwner parameter effectively creates a two way link between the list
|
||||
* item and its owner.
|
||||
*
|
||||
* @param pxTCB pxTCB is set to the address of the owner of the next list item.
|
||||
* @param pxList The list from which the next item owner is to be returned.
|
||||
*
|
||||
* \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
|
||||
{ \
|
||||
List_t * const pxConstList = ( pxList ); \
|
||||
/* Increment the index to the next item and return the item, ensuring */ \
|
||||
/* we don't return the marker used at the end of the list. */ \
|
||||
( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
|
||||
if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
|
||||
{ \
|
||||
( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
|
||||
} \
|
||||
( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Access function to obtain the owner of the first entry in a list. Lists
|
||||
* are normally sorted in ascending item value order.
|
||||
*
|
||||
* This function returns the pxOwner member of the first item in the list.
|
||||
* The pxOwner parameter of a list item is a pointer to the object that owns
|
||||
* the list item. In the scheduler this is normally a task control block.
|
||||
* The pxOwner parameter effectively creates a two way link between the list
|
||||
* item and its owner.
|
||||
*
|
||||
* @param pxList The list from which the owner of the head item is to be
|
||||
* returned.
|
||||
*
|
||||
* \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
|
||||
|
||||
/*
|
||||
* Check to see if a list item is within a list. The list item maintains a
|
||||
* "container" pointer that points to the list it is in. All this macro does
|
||||
* is check to see if the container and the list match.
|
||||
*
|
||||
* @param pxList The list we want to know if the list item is within.
|
||||
* @param pxListItem The list item we want to know if is in the list.
|
||||
* @return pdTRUE if the list item is in the list, otherwise pdFALSE.
|
||||
*/
|
||||
#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )
|
||||
|
||||
/*
|
||||
* Return the list a list item is contained within (referenced from).
|
||||
*
|
||||
* @param pxListItem The list item being queried.
|
||||
* @return A pointer to the List_t object that references the pxListItem
|
||||
*/
|
||||
#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )
|
||||
|
||||
/*
|
||||
* This provides a crude means of knowing if a list has been initialised, as
|
||||
* pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
|
||||
* function.
|
||||
*/
|
||||
#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
|
||||
|
||||
/*
|
||||
* Must be called before a list is used! This initialises all the members
|
||||
* of the list structure and inserts the xListEnd item into the list as a
|
||||
* marker to the back of the list.
|
||||
*
|
||||
* @param pxList Pointer to the list being initialised.
|
||||
*
|
||||
* \page vListInitialise vListInitialise
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* Must be called before a list item is used. This sets the list container to
|
||||
* null so the item does not think that it is already contained in a list.
|
||||
*
|
||||
* @param pxItem Pointer to the list item being initialised.
|
||||
*
|
||||
* \page vListInitialiseItem vListInitialiseItem
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* Insert a list item into a list. The item will be inserted into the list in
|
||||
* a position determined by its item value (descending item value order).
|
||||
*
|
||||
* @param pxList The list into which the item is to be inserted.
|
||||
*
|
||||
* @param pxNewListItem The item that is to be placed in the list.
|
||||
*
|
||||
* \page vListInsert vListInsert
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* Insert a list item into a list. The item will be inserted in a position
|
||||
* such that it will be the last item within the list returned by multiple
|
||||
* calls to listGET_OWNER_OF_NEXT_ENTRY.
|
||||
*
|
||||
* The list member pxIndex is used to walk through a list. Calling
|
||||
* listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
|
||||
* Placing an item in a list using vListInsertEnd effectively places the item
|
||||
* in the list position pointed to by pxIndex. This means that every other
|
||||
* item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
|
||||
* the pxIndex parameter again points to the item being inserted.
|
||||
*
|
||||
* @param pxList The list into which the item is to be inserted.
|
||||
*
|
||||
* @param pxNewListItem The list item to be inserted into the list.
|
||||
*
|
||||
* \page vListInsertEnd vListInsertEnd
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* Remove an item from a list. The list item has a pointer to the list that
|
||||
* it is in, so only the list item need be passed into the function.
|
||||
*
|
||||
* @param uxListRemove The item to be removed. The item will remove itself from
|
||||
* the list pointed to by it's pxContainer parameter.
|
||||
*
|
||||
* @return The number of items that remain in the list after the list item has
|
||||
* been removed.
|
||||
*
|
||||
* \page uxListRemove uxListRemove
|
||||
* \ingroup LinkedList
|
||||
*/
|
||||
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,793 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Message buffers build functionality on top of FreeRTOS stream buffers.
|
||||
* Whereas stream buffers are used to send a continuous stream of data from one
|
||||
* task or interrupt to another, message buffers are used to send variable
|
||||
* length discrete messages from one task or interrupt to another. Their
|
||||
* implementation is light weight, making them particularly suited for interrupt
|
||||
* to task and core to core communication scenarios.
|
||||
*
|
||||
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||
* implementation (so also the message buffer implementation, as message buffers
|
||||
* are built on top of stream buffers) assumes there is only one task or
|
||||
* interrupt that will write to the buffer (the writer), and only one task or
|
||||
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||
* multiple different readers. If there are to be multiple different writers
|
||||
* then the application writer must place each call to a writing API function
|
||||
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||
* block time to 0. Likewise, if there are to be multiple different readers
|
||||
* then the application writer must place each call to a reading API function
|
||||
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||
* timeout to 0.
|
||||
*
|
||||
* Message buffers hold variable length messages. To enable that, when a
|
||||
* message is written to the message buffer an additional sizeof( size_t ) bytes
|
||||
* are also written to store the message's length (that happens internally, with
|
||||
* the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit
|
||||
* architecture, so writing a 10 byte message to a message buffer on a 32-bit
|
||||
* architecture will actually reduce the available space in the message buffer
|
||||
* by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
|
||||
* of the message).
|
||||
*/
|
||||
|
||||
#ifndef FREERTOS_MESSAGE_BUFFER_H
|
||||
#define FREERTOS_MESSAGE_BUFFER_H
|
||||
|
||||
/* Message buffers are built onto of stream buffers. */
|
||||
#include "stream_buffer.h"
|
||||
|
||||
#if defined( __cplusplus )
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Type by which message buffers are referenced. For example, a call to
|
||||
* xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
|
||||
* then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
|
||||
* etc.
|
||||
*/
|
||||
typedef void * MessageBufferHandle_t;
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
|
||||
</pre>
|
||||
*
|
||||
* Creates a new message buffer using dynamically allocated memory. See
|
||||
* xMessageBufferCreateStatic() for a version that uses statically allocated
|
||||
* memory (memory that is allocated at compile time).
|
||||
*
|
||||
* configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
|
||||
* FreeRTOSConfig.h for xMessageBufferCreate() to be available.
|
||||
*
|
||||
* @param xBufferSizeBytes The total number of bytes (not messages) the message
|
||||
* buffer will be able to hold at any one time. When a message is written to
|
||||
* the message buffer an additional sizeof( size_t ) bytes are also written to
|
||||
* store the message's length. sizeof( size_t ) is typically 4 bytes on a
|
||||
* 32-bit architecture, so on most 32-bit architectures a 10 byte message will
|
||||
* take up 14 bytes of message buffer space.
|
||||
*
|
||||
* @return If NULL is returned, then the message buffer cannot be created
|
||||
* because there is insufficient heap memory available for FreeRTOS to allocate
|
||||
* the message buffer data structures and storage area. A non-NULL value being
|
||||
* returned indicates that the message buffer has been created successfully -
|
||||
* the returned value should be stored as the handle to the created message
|
||||
* buffer.
|
||||
*
|
||||
* Example use:
|
||||
<pre>
|
||||
|
||||
void vAFunction( void )
|
||||
{
|
||||
MessageBufferHandle_t xMessageBuffer;
|
||||
const size_t xMessageBufferSizeBytes = 100;
|
||||
|
||||
// Create a message buffer that can hold 100 bytes. The memory used to hold
|
||||
// both the message buffer structure and the messages themselves is allocated
|
||||
// dynamically. Each message added to the buffer consumes an additional 4
|
||||
// bytes which are used to hold the lengh of the message.
|
||||
xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
|
||||
|
||||
if( xMessageBuffer == NULL )
|
||||
{
|
||||
// There was not enough heap memory space available to create the
|
||||
// message buffer.
|
||||
}
|
||||
else
|
||||
{
|
||||
// The message buffer was created successfully and can now be used.
|
||||
}
|
||||
|
||||
</pre>
|
||||
* \defgroup xMessageBufferCreate xMessageBufferCreate
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
|
||||
uint8_t *pucMessageBufferStorageArea,
|
||||
StaticMessageBuffer_t *pxStaticMessageBuffer );
|
||||
</pre>
|
||||
* Creates a new message buffer using statically allocated memory. See
|
||||
* xMessageBufferCreate() for a version that uses dynamically allocated memory.
|
||||
*
|
||||
* @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
|
||||
* pucMessageBufferStorageArea parameter. When a message is written to the
|
||||
* message buffer an additional sizeof( size_t ) bytes are also written to store
|
||||
* the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit
|
||||
* architecture, so on most 32-bit architecture a 10 byte message will take up
|
||||
* 14 bytes of message buffer space. The maximum number of bytes that can be
|
||||
* stored in the message buffer is actually (xBufferSizeBytes - 1).
|
||||
*
|
||||
* @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
|
||||
* least xBufferSizeBytes + 1 big. This is the array to which messages are
|
||||
* copied when they are written to the message buffer.
|
||||
*
|
||||
* @param pxStaticMessageBuffer Must point to a variable of type
|
||||
* StaticMessageBuffer_t, which will be used to hold the message buffer's data
|
||||
* structure.
|
||||
*
|
||||
* @return If the message buffer is created successfully then a handle to the
|
||||
* created message buffer is returned. If either pucMessageBufferStorageArea or
|
||||
* pxStaticmessageBuffer are NULL then NULL is returned.
|
||||
*
|
||||
* Example use:
|
||||
<pre>
|
||||
|
||||
// Used to dimension the array used to hold the messages. The available space
|
||||
// will actually be one less than this, so 999.
|
||||
#define STORAGE_SIZE_BYTES 1000
|
||||
|
||||
// Defines the memory that will actually hold the messages within the message
|
||||
// buffer.
|
||||
static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
|
||||
|
||||
// The variable used to hold the message buffer structure.
|
||||
StaticMessageBuffer_t xMessageBufferStruct;
|
||||
|
||||
void MyFunction( void )
|
||||
{
|
||||
MessageBufferHandle_t xMessageBuffer;
|
||||
|
||||
xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
|
||||
ucBufferStorage,
|
||||
&xMessageBufferStruct );
|
||||
|
||||
// As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
|
||||
// parameters were NULL, xMessageBuffer will not be NULL, and can be used to
|
||||
// reference the created message buffer in other message buffer API calls.
|
||||
|
||||
// Other code that uses the message buffer can go here.
|
||||
}
|
||||
|
||||
</pre>
|
||||
* \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
|
||||
const void *pvTxData,
|
||||
size_t xDataLengthBytes,
|
||||
TickType_t xTicksToWait );
|
||||
<pre>
|
||||
*
|
||||
* Sends a discrete message to the message buffer. The message can be any
|
||||
* length that fits within the buffer's free space, and is copied into the
|
||||
* buffer.
|
||||
*
|
||||
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||
* implementation (so also the message buffer implementation, as message buffers
|
||||
* are built on top of stream buffers) assumes there is only one task or
|
||||
* interrupt that will write to the buffer (the writer), and only one task or
|
||||
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||
* multiple different readers. If there are to be multiple different writers
|
||||
* then the application writer must place each call to a writing API function
|
||||
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||
* block time to 0. Likewise, if there are to be multiple different readers
|
||||
* then the application writer must place each call to a reading API function
|
||||
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||
* block time to 0.
|
||||
*
|
||||
* Use xMessageBufferSend() to write to a message buffer from a task. Use
|
||||
* xMessageBufferSendFromISR() to write to a message buffer from an interrupt
|
||||
* service routine (ISR).
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer to which a message is
|
||||
* being sent.
|
||||
*
|
||||
* @param pvTxData A pointer to the message that is to be copied into the
|
||||
* message buffer.
|
||||
*
|
||||
* @param xDataLengthBytes The length of the message. That is, the number of
|
||||
* bytes to copy from pvTxData into the message buffer. When a message is
|
||||
* written to the message buffer an additional sizeof( size_t ) bytes are also
|
||||
* written to store the message's length. sizeof( size_t ) is typically 4 bytes
|
||||
* on a 32-bit architecture, so on most 32-bit architecture setting
|
||||
* xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
|
||||
* bytes (20 bytes of message data and 4 bytes to hold the message length).
|
||||
*
|
||||
* @param xTicksToWait The maximum amount of time the calling task should remain
|
||||
* in the Blocked state to wait for enough space to become available in the
|
||||
* message buffer, should the message buffer have insufficient space when
|
||||
* xMessageBufferSend() is called. The calling task will never block if
|
||||
* xTicksToWait is zero. The block time is specified in tick periods, so the
|
||||
* absolute time it represents is dependent on the tick frequency. The macro
|
||||
* pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
|
||||
* a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause
|
||||
* the task to wait indefinitely (without timing out), provided
|
||||
* INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any
|
||||
* CPU time when they are in the Blocked state.
|
||||
*
|
||||
* @return The number of bytes written to the message buffer. If the call to
|
||||
* xMessageBufferSend() times out before there was enough space to write the
|
||||
* message into the message buffer then zero is returned. If the call did not
|
||||
* time out then xDataLengthBytes is returned.
|
||||
*
|
||||
* Example use:
|
||||
<pre>
|
||||
void vAFunction( MessageBufferHandle_t xMessageBuffer )
|
||||
{
|
||||
size_t xBytesSent;
|
||||
uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
|
||||
char *pcStringToSend = "String to send";
|
||||
const TickType_t x100ms = pdMS_TO_TICKS( 100 );
|
||||
|
||||
// Send an array to the message buffer, blocking for a maximum of 100ms to
|
||||
// wait for enough space to be available in the message buffer.
|
||||
xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
|
||||
|
||||
if( xBytesSent != sizeof( ucArrayToSend ) )
|
||||
{
|
||||
// The call to xMessageBufferSend() times out before there was enough
|
||||
// space in the buffer for the data to be written.
|
||||
}
|
||||
|
||||
// Send the string to the message buffer. Return immediately if there is
|
||||
// not enough space in the buffer.
|
||||
xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
|
||||
|
||||
if( xBytesSent != strlen( pcStringToSend ) )
|
||||
{
|
||||
// The string could not be added to the message buffer because there was
|
||||
// not enough free space in the buffer.
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xMessageBufferSend xMessageBufferSend
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
|
||||
const void *pvTxData,
|
||||
size_t xDataLengthBytes,
|
||||
BaseType_t *pxHigherPriorityTaskWoken );
|
||||
<pre>
|
||||
*
|
||||
* Interrupt safe version of the API function that sends a discrete message to
|
||||
* the message buffer. The message can be any length that fits within the
|
||||
* buffer's free space, and is copied into the buffer.
|
||||
*
|
||||
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||
* implementation (so also the message buffer implementation, as message buffers
|
||||
* are built on top of stream buffers) assumes there is only one task or
|
||||
* interrupt that will write to the buffer (the writer), and only one task or
|
||||
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||
* multiple different readers. If there are to be multiple different writers
|
||||
* then the application writer must place each call to a writing API function
|
||||
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||
* block time to 0. Likewise, if there are to be multiple different readers
|
||||
* then the application writer must place each call to a reading API function
|
||||
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||
* block time to 0.
|
||||
*
|
||||
* Use xMessageBufferSend() to write to a message buffer from a task. Use
|
||||
* xMessageBufferSendFromISR() to write to a message buffer from an interrupt
|
||||
* service routine (ISR).
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer to which a message is
|
||||
* being sent.
|
||||
*
|
||||
* @param pvTxData A pointer to the message that is to be copied into the
|
||||
* message buffer.
|
||||
*
|
||||
* @param xDataLengthBytes The length of the message. That is, the number of
|
||||
* bytes to copy from pvTxData into the message buffer. When a message is
|
||||
* written to the message buffer an additional sizeof( size_t ) bytes are also
|
||||
* written to store the message's length. sizeof( size_t ) is typically 4 bytes
|
||||
* on a 32-bit architecture, so on most 32-bit architecture setting
|
||||
* xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
|
||||
* bytes (20 bytes of message data and 4 bytes to hold the message length).
|
||||
*
|
||||
* @param pxHigherPriorityTaskWoken It is possible that a message buffer will
|
||||
* have a task blocked on it waiting for data. Calling
|
||||
* xMessageBufferSendFromISR() can make data available, and so cause a task that
|
||||
* was waiting for data to leave the Blocked state. If calling
|
||||
* xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
|
||||
* unblocked task has a priority higher than the currently executing task (the
|
||||
* task that was interrupted), then, internally, xMessageBufferSendFromISR()
|
||||
* will set *pxHigherPriorityTaskWoken to pdTRUE. If
|
||||
* xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
|
||||
* context switch should be performed before the interrupt is exited. This will
|
||||
* ensure that the interrupt returns directly to the highest priority Ready
|
||||
* state task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it
|
||||
* is passed into the function. See the code example below for an example.
|
||||
*
|
||||
* @return The number of bytes actually written to the message buffer. If the
|
||||
* message buffer didn't have enough free space for the message to be stored
|
||||
* then 0 is returned, otherwise xDataLengthBytes is returned.
|
||||
*
|
||||
* Example use:
|
||||
<pre>
|
||||
// A message buffer that has already been created.
|
||||
MessageBufferHandle_t xMessageBuffer;
|
||||
|
||||
void vAnInterruptServiceRoutine( void )
|
||||
{
|
||||
size_t xBytesSent;
|
||||
char *pcStringToSend = "String to send";
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
|
||||
|
||||
// Attempt to send the string to the message buffer.
|
||||
xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
|
||||
( void * ) pcStringToSend,
|
||||
strlen( pcStringToSend ),
|
||||
&xHigherPriorityTaskWoken );
|
||||
|
||||
if( xBytesSent != strlen( pcStringToSend ) )
|
||||
{
|
||||
// The string could not be added to the message buffer because there was
|
||||
// not enough free space in the buffer.
|
||||
}
|
||||
|
||||
// If xHigherPriorityTaskWoken was set to pdTRUE inside
|
||||
// xMessageBufferSendFromISR() then a task that has a priority above the
|
||||
// priority of the currently executing task was unblocked and a context
|
||||
// switch should be performed to ensure the ISR returns to the unblocked
|
||||
// task. In most FreeRTOS ports this is done by simply passing
|
||||
// xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
|
||||
// variables value, and perform the context switch if necessary. Check the
|
||||
// documentation for the port in use for port specific instructions.
|
||||
taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
|
||||
void *pvRxData,
|
||||
size_t xBufferLengthBytes,
|
||||
TickType_t xTicksToWait );
|
||||
</pre>
|
||||
*
|
||||
* Receives a discrete message from a message buffer. Messages can be of
|
||||
* variable length and are copied out of the buffer.
|
||||
*
|
||||
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||
* implementation (so also the message buffer implementation, as message buffers
|
||||
* are built on top of stream buffers) assumes there is only one task or
|
||||
* interrupt that will write to the buffer (the writer), and only one task or
|
||||
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||
* multiple different readers. If there are to be multiple different writers
|
||||
* then the application writer must place each call to a writing API function
|
||||
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||
* block time to 0. Likewise, if there are to be multiple different readers
|
||||
* then the application writer must place each call to a reading API function
|
||||
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||
* block time to 0.
|
||||
*
|
||||
* Use xMessageBufferReceive() to read from a message buffer from a task. Use
|
||||
* xMessageBufferReceiveFromISR() to read from a message buffer from an
|
||||
* interrupt service routine (ISR).
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer from which a message
|
||||
* is being received.
|
||||
*
|
||||
* @param pvRxData A pointer to the buffer into which the received message is
|
||||
* to be copied.
|
||||
*
|
||||
* @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
|
||||
* parameter. This sets the maximum length of the message that can be received.
|
||||
* If xBufferLengthBytes is too small to hold the next message then the message
|
||||
* will be left in the message buffer and 0 will be returned.
|
||||
*
|
||||
* @param xTicksToWait The maximum amount of time the task should remain in the
|
||||
* Blocked state to wait for a message, should the message buffer be empty.
|
||||
* xMessageBufferReceive() will return immediately if xTicksToWait is zero and
|
||||
* the message buffer is empty. The block time is specified in tick periods, so
|
||||
* the absolute time it represents is dependent on the tick frequency. The
|
||||
* macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
|
||||
* into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will
|
||||
* cause the task to wait indefinitely (without timing out), provided
|
||||
* INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any
|
||||
* CPU time when they are in the Blocked state.
|
||||
*
|
||||
* @return The length, in bytes, of the message read from the message buffer, if
|
||||
* any. If xMessageBufferReceive() times out before a message became available
|
||||
* then zero is returned. If the length of the message is greater than
|
||||
* xBufferLengthBytes then the message will be left in the message buffer and
|
||||
* zero is returned.
|
||||
*
|
||||
* Example use:
|
||||
<pre>
|
||||
void vAFunction( MessageBuffer_t xMessageBuffer )
|
||||
{
|
||||
uint8_t ucRxData[ 20 ];
|
||||
size_t xReceivedBytes;
|
||||
const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
|
||||
|
||||
// Receive the next message from the message buffer. Wait in the Blocked
|
||||
// state (so not using any CPU processing time) for a maximum of 100ms for
|
||||
// a message to become available.
|
||||
xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
|
||||
( void * ) ucRxData,
|
||||
sizeof( ucRxData ),
|
||||
xBlockTime );
|
||||
|
||||
if( xReceivedBytes > 0 )
|
||||
{
|
||||
// A ucRxData contains a message that is xReceivedBytes long. Process
|
||||
// the message here....
|
||||
}
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xMessageBufferReceive xMessageBufferReceive
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
|
||||
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
|
||||
void *pvRxData,
|
||||
size_t xBufferLengthBytes,
|
||||
BaseType_t *pxHigherPriorityTaskWoken );
|
||||
</pre>
|
||||
*
|
||||
* An interrupt safe version of the API function that receives a discrete
|
||||
* message from a message buffer. Messages can be of variable length and are
|
||||
* copied out of the buffer.
|
||||
*
|
||||
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||
* implementation (so also the message buffer implementation, as message buffers
|
||||
* are built on top of stream buffers) assumes there is only one task or
|
||||
* interrupt that will write to the buffer (the writer), and only one task or
|
||||
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||
* multiple different readers. If there are to be multiple different writers
|
||||
* then the application writer must place each call to a writing API function
|
||||
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||
* block time to 0. Likewise, if there are to be multiple different readers
|
||||
* then the application writer must place each call to a reading API function
|
||||
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||
* block time to 0.
|
||||
*
|
||||
* Use xMessageBufferReceive() to read from a message buffer from a task. Use
|
||||
* xMessageBufferReceiveFromISR() to read from a message buffer from an
|
||||
* interrupt service routine (ISR).
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer from which a message
|
||||
* is being received.
|
||||
*
|
||||
* @param pvRxData A pointer to the buffer into which the received message is
|
||||
* to be copied.
|
||||
*
|
||||
* @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
|
||||
* parameter. This sets the maximum length of the message that can be received.
|
||||
* If xBufferLengthBytes is too small to hold the next message then the message
|
||||
* will be left in the message buffer and 0 will be returned.
|
||||
*
|
||||
* @param pxHigherPriorityTaskWoken It is possible that a message buffer will
|
||||
* have a task blocked on it waiting for space to become available. Calling
|
||||
* xMessageBufferReceiveFromISR() can make space available, and so cause a task
|
||||
* that is waiting for space to leave the Blocked state. If calling
|
||||
* xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
|
||||
* the unblocked task has a priority higher than the currently executing task
|
||||
* (the task that was interrupted), then, internally,
|
||||
* xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
|
||||
* If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
|
||||
* context switch should be performed before the interrupt is exited. That will
|
||||
* ensure the interrupt returns directly to the highest priority Ready state
|
||||
* task. *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
|
||||
* passed into the function. See the code example below for an example.
|
||||
*
|
||||
* @return The length, in bytes, of the message read from the message buffer, if
|
||||
* any.
|
||||
*
|
||||
* Example use:
|
||||
<pre>
|
||||
// A message buffer that has already been created.
|
||||
MessageBuffer_t xMessageBuffer;
|
||||
|
||||
void vAnInterruptServiceRoutine( void )
|
||||
{
|
||||
uint8_t ucRxData[ 20 ];
|
||||
size_t xReceivedBytes;
|
||||
BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
|
||||
|
||||
// Receive the next message from the message buffer.
|
||||
xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
|
||||
( void * ) ucRxData,
|
||||
sizeof( ucRxData ),
|
||||
&xHigherPriorityTaskWoken );
|
||||
|
||||
if( xReceivedBytes > 0 )
|
||||
{
|
||||
// A ucRxData contains a message that is xReceivedBytes long. Process
|
||||
// the message here....
|
||||
}
|
||||
|
||||
// If xHigherPriorityTaskWoken was set to pdTRUE inside
|
||||
// xMessageBufferReceiveFromISR() then a task that has a priority above the
|
||||
// priority of the currently executing task was unblocked and a context
|
||||
// switch should be performed to ensure the ISR returns to the unblocked
|
||||
// task. In most FreeRTOS ports this is done by simply passing
|
||||
// xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
|
||||
// variables value, and perform the context switch if necessary. Check the
|
||||
// documentation for the port in use for port specific instructions.
|
||||
taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||
}
|
||||
</pre>
|
||||
* \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
|
||||
</pre>
|
||||
*
|
||||
* Deletes a message buffer that was previously created using a call to
|
||||
* xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message
|
||||
* buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
|
||||
* then the allocated memory is freed.
|
||||
*
|
||||
* A message buffer handle must not be used after the message buffer has been
|
||||
* deleted.
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer to be deleted.
|
||||
*
|
||||
*/
|
||||
#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
<pre>
|
||||
BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
|
||||
</pre>
|
||||
*
|
||||
* Tests to see if a message buffer is full. A message buffer is full if it
|
||||
* cannot accept any more messages, of any size, until space is made available
|
||||
* by a message being removed from the message buffer.
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||
*
|
||||
* @return If the message buffer referenced by xMessageBuffer is full then
|
||||
* pdTRUE is returned. Otherwise pdFALSE is returned.
|
||||
*/
|
||||
#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
<pre>
|
||||
BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
|
||||
</pre>
|
||||
*
|
||||
* Tests to see if a message buffer is empty (does not contain any messages).
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||
*
|
||||
* @return If the message buffer referenced by xMessageBuffer is empty then
|
||||
* pdTRUE is returned. Otherwise pdFALSE is returned.
|
||||
*
|
||||
*/
|
||||
#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
<pre>
|
||||
BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
|
||||
</pre>
|
||||
*
|
||||
* Resets a message buffer to its initial empty state, discarding any message it
|
||||
* contained.
|
||||
*
|
||||
* A message buffer can only be reset if there are no tasks blocked on it.
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer being reset.
|
||||
*
|
||||
* @return If the message buffer was reset then pdPASS is returned. If the
|
||||
* message buffer could not be reset because either there was a task blocked on
|
||||
* the message queue to wait for space to become available, or to wait for a
|
||||
* a message to be available, then pdFAIL is returned.
|
||||
*
|
||||
* \defgroup xMessageBufferReset xMessageBufferReset
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
<pre>
|
||||
size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
|
||||
</pre>
|
||||
* Returns the number of bytes of free space in the message buffer.
|
||||
*
|
||||
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||
*
|
||||
* @return The number of bytes that can be written to the message buffer before
|
||||
* the message buffer would be full. When a message is written to the message
|
||||
* buffer an additional sizeof( size_t ) bytes are also written to store the
|
||||
* message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit
|
||||
* architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
|
||||
* of the largest message that can be written to the message buffer is 6 bytes.
|
||||
*
|
||||
* \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
|
||||
* \ingroup MessageBufferManagement
|
||||
*/
|
||||
#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
|
||||
</pre>
|
||||
*
|
||||
* For advanced users only.
|
||||
*
|
||||
* The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
|
||||
* data is sent to a message buffer or stream buffer. If there was a task that
|
||||
* was blocked on the message or stream buffer waiting for data to arrive then
|
||||
* the sbSEND_COMPLETED() macro sends a notification to the task to remove it
|
||||
* from the Blocked state. xMessageBufferSendCompletedFromISR() does the same
|
||||
* thing. It is provided to enable application writers to implement their own
|
||||
* version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
|
||||
*
|
||||
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
|
||||
* additional information.
|
||||
*
|
||||
* @param xStreamBuffer The handle of the stream buffer to which data was
|
||||
* written.
|
||||
*
|
||||
* @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
|
||||
* initialised to pdFALSE before it is passed into
|
||||
* xMessageBufferSendCompletedFromISR(). If calling
|
||||
* xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
|
||||
* and the task has a priority above the priority of the currently running task,
|
||||
* then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
|
||||
* context switch should be performed before exiting the ISR.
|
||||
*
|
||||
* @return If a task was removed from the Blocked state then pdTRUE is returned.
|
||||
* Otherwise pdFALSE is returned.
|
||||
*
|
||||
* \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
|
||||
* \ingroup StreamBufferManagement
|
||||
*/
|
||||
#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
|
||||
|
||||
/**
|
||||
* message_buffer.h
|
||||
*
|
||||
<pre>
|
||||
BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
|
||||
</pre>
|
||||
*
|
||||
* For advanced users only.
|
||||
*
|
||||
* The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
|
||||
* data is read out of a message buffer or stream buffer. If there was a task
|
||||
* that was blocked on the message or stream buffer waiting for data to arrive
|
||||
* then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
|
||||
* remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR()
|
||||
* does the same thing. It is provided to enable application writers to
|
||||
* implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
|
||||
* ANY OTHER TIME.
|
||||
*
|
||||
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
|
||||
* additional information.
|
||||
*
|
||||
* @param xStreamBuffer The handle of the stream buffer from which data was
|
||||
* read.
|
||||
*
|
||||
* @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
|
||||
* initialised to pdFALSE before it is passed into
|
||||
* xMessageBufferReceiveCompletedFromISR(). If calling
|
||||
* xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
|
||||
* and the task has a priority above the priority of the currently running task,
|
||||
* then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
|
||||
* context switch should be performed before exiting the ISR.
|
||||
*
|
||||
* @return If a task was removed from the Blocked state then pdTRUE is returned.
|
||||
* Otherwise pdFALSE is returned.
|
||||
*
|
||||
* \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
|
||||
* \ingroup StreamBufferManagement
|
||||
*/
|
||||
#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
|
||||
|
||||
#if defined( __cplusplus )
|
||||
} /* extern "C" */
|
||||
#endif
|
||||
|
||||
#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
|
|
@ -0,0 +1,169 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*
|
||||
* When the MPU is used the standard (non MPU) API functions are mapped to
|
||||
* equivalents that start "MPU_", the prototypes for which are defined in this
|
||||
* header files. This will cause the application code to call the MPU_ version
|
||||
* which wraps the non-MPU version with privilege promoting then demoting code,
|
||||
* so the kernel code always runs will full privileges.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef MPU_PROTOTYPES_H
|
||||
#define MPU_PROTOTYPES_H
|
||||
|
||||
/* MPU versions of tasks.h API functions. */
|
||||
BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
|
||||
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
|
||||
BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
|
||||
BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
|
||||
void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
|
||||
void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
|
||||
void MPU_vTaskDelay( const TickType_t xTicksToDelay );
|
||||
void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
|
||||
BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
|
||||
UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
|
||||
eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
|
||||
void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
|
||||
void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
|
||||
void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
|
||||
void MPU_vTaskResume( TaskHandle_t xTaskToResume );
|
||||
void MPU_vTaskStartScheduler( void );
|
||||
void MPU_vTaskSuspendAll( void );
|
||||
BaseType_t MPU_xTaskResumeAll( void );
|
||||
TickType_t MPU_xTaskGetTickCount( void );
|
||||
UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
|
||||
char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
|
||||
TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
|
||||
UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
|
||||
void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
|
||||
TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
|
||||
void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
|
||||
void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
|
||||
BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
|
||||
TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
|
||||
UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
|
||||
void MPU_vTaskList( char * pcWriteBuffer );
|
||||
void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
|
||||
BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
|
||||
BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
|
||||
uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
|
||||
BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
|
||||
BaseType_t MPU_xTaskIncrementTick( void );
|
||||
TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
|
||||
void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
|
||||
BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
|
||||
void MPU_vTaskMissedYield( void );
|
||||
BaseType_t MPU_xTaskGetSchedulerState( void );
|
||||
|
||||
/* MPU versions of queue.h API functions. */
|
||||
BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
|
||||
BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
|
||||
BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait );
|
||||
BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait );
|
||||
UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
|
||||
UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
|
||||
void MPU_vQueueDelete( QueueHandle_t xQueue );
|
||||
QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
|
||||
QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
|
||||
QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
|
||||
QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
|
||||
void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
|
||||
BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
|
||||
BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
|
||||
void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
|
||||
void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
|
||||
const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
|
||||
QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
|
||||
QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
|
||||
QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
|
||||
BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
|
||||
BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
|
||||
QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
|
||||
BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
|
||||
void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
|
||||
UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
|
||||
uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
|
||||
|
||||
/* MPU versions of timers.h API functions. */
|
||||
TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
|
||||
TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
|
||||
void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
|
||||
void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
|
||||
BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
|
||||
TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
|
||||
BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
|
||||
const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
|
||||
TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
|
||||
TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
|
||||
BaseType_t MPU_xTimerCreateTimerTask( void );
|
||||
BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
|
||||
|
||||
/* MPU versions of event_group.h API functions. */
|
||||
EventGroupHandle_t MPU_xEventGroupCreate( void );
|
||||
EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
|
||||
EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
|
||||
EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
|
||||
EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
|
||||
EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
|
||||
void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
|
||||
UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
|
||||
|
||||
/* MPU versions of message/stream_buffer.h API functions. */
|
||||
size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait );
|
||||
size_t MPU_xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
|
||||
size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait );
|
||||
size_t MPU_xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, BaseType_t * const pxHigherPriorityTaskWoken );
|
||||
void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
|
||||
BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
|
||||
BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
|
||||
BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
|
||||
size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
|
||||
size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
|
||||
BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
|
||||
StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer );
|
||||
StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer );
|
||||
|
||||
|
||||
|
||||
#endif /* MPU_PROTOTYPES_H */
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef MPU_WRAPPERS_H
|
||||
#define MPU_WRAPPERS_H
|
||||
|
||||
/* This file redefines API functions to be called through a wrapper macro, but
|
||||
only for ports that are using the MPU. */
|
||||
#ifdef portUSING_MPU_WRAPPERS
|
||||
|
||||
/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
|
||||
included from queue.c or task.c to prevent it from having an effect within
|
||||
those files. */
|
||||
#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||
|
||||
/*
|
||||
* Map standard (non MPU) API functions to equivalents that start
|
||||
* "MPU_". This will cause the application code to call the MPU_
|
||||
* version, which wraps the non-MPU version with privilege promoting
|
||||
* then demoting code, so the kernel code always runs will full
|
||||
* privileges.
|
||||
*/
|
||||
|
||||
/* Map standard tasks.h API functions to the MPU equivalents. */
|
||||
#define xTaskCreate MPU_xTaskCreate
|
||||
#define xTaskCreateStatic MPU_xTaskCreateStatic
|
||||
#define xTaskCreateRestricted MPU_xTaskCreateRestricted
|
||||
#define vTaskAllocateMPURegions MPU_vTaskAllocateMPURegions
|
||||
#define vTaskDelete MPU_vTaskDelete
|
||||
#define vTaskDelay MPU_vTaskDelay
|
||||
#define vTaskDelayUntil MPU_vTaskDelayUntil
|
||||
#define xTaskAbortDelay MPU_xTaskAbortDelay
|
||||
#define uxTaskPriorityGet MPU_uxTaskPriorityGet
|
||||
#define eTaskGetState MPU_eTaskGetState
|
||||
#define vTaskGetInfo MPU_vTaskGetInfo
|
||||
#define vTaskPrioritySet MPU_vTaskPrioritySet
|
||||
#define vTaskSuspend MPU_vTaskSuspend
|
||||
#define vTaskResume MPU_vTaskResume
|
||||
#define vTaskSuspendAll MPU_vTaskSuspendAll
|
||||
#define xTaskResumeAll MPU_xTaskResumeAll
|
||||
#define xTaskGetTickCount MPU_xTaskGetTickCount
|
||||
#define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks
|
||||
#define pcTaskGetName MPU_pcTaskGetName
|
||||
#define xTaskGetHandle MPU_xTaskGetHandle
|
||||
#define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark
|
||||
#define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag
|
||||
#define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag
|
||||
#define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer
|
||||
#define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer
|
||||
#define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook
|
||||
#define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle
|
||||
#define uxTaskGetSystemState MPU_uxTaskGetSystemState
|
||||
#define vTaskList MPU_vTaskList
|
||||
#define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats
|
||||
#define xTaskGenericNotify MPU_xTaskGenericNotify
|
||||
#define xTaskNotifyWait MPU_xTaskNotifyWait
|
||||
#define ulTaskNotifyTake MPU_ulTaskNotifyTake
|
||||
#define xTaskNotifyStateClear MPU_xTaskNotifyStateClear
|
||||
|
||||
#define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle
|
||||
#define vTaskSetTimeOutState MPU_vTaskSetTimeOutState
|
||||
#define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut
|
||||
#define xTaskGetSchedulerState MPU_xTaskGetSchedulerState
|
||||
|
||||
/* Map standard queue.h API functions to the MPU equivalents. */
|
||||
#define xQueueGenericSend MPU_xQueueGenericSend
|
||||
#define xQueueReceive MPU_xQueueReceive
|
||||
#define xQueuePeek MPU_xQueuePeek
|
||||
#define xQueueSemaphoreTake MPU_xQueueSemaphoreTake
|
||||
#define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting
|
||||
#define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable
|
||||
#define vQueueDelete MPU_vQueueDelete
|
||||
#define xQueueCreateMutex MPU_xQueueCreateMutex
|
||||
#define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic
|
||||
#define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore
|
||||
#define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic
|
||||
#define xQueueGetMutexHolder MPU_xQueueGetMutexHolder
|
||||
#define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive
|
||||
#define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive
|
||||
#define xQueueGenericCreate MPU_xQueueGenericCreate
|
||||
#define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic
|
||||
#define xQueueCreateSet MPU_xQueueCreateSet
|
||||
#define xQueueAddToSet MPU_xQueueAddToSet
|
||||
#define xQueueRemoveFromSet MPU_xQueueRemoveFromSet
|
||||
#define xQueueSelectFromSet MPU_xQueueSelectFromSet
|
||||
#define xQueueGenericReset MPU_xQueueGenericReset
|
||||
|
||||
#if( configQUEUE_REGISTRY_SIZE > 0 )
|
||||
#define vQueueAddToRegistry MPU_vQueueAddToRegistry
|
||||
#define vQueueUnregisterQueue MPU_vQueueUnregisterQueue
|
||||
#define pcQueueGetName MPU_pcQueueGetName
|
||||
#endif
|
||||
|
||||
/* Map standard timer.h API functions to the MPU equivalents. */
|
||||
#define xTimerCreate MPU_xTimerCreate
|
||||
#define xTimerCreateStatic MPU_xTimerCreateStatic
|
||||
#define pvTimerGetTimerID MPU_pvTimerGetTimerID
|
||||
#define vTimerSetTimerID MPU_vTimerSetTimerID
|
||||
#define xTimerIsTimerActive MPU_xTimerIsTimerActive
|
||||
#define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle
|
||||
#define xTimerPendFunctionCall MPU_xTimerPendFunctionCall
|
||||
#define pcTimerGetName MPU_pcTimerGetName
|
||||
#define xTimerGetPeriod MPU_xTimerGetPeriod
|
||||
#define xTimerGetExpiryTime MPU_xTimerGetExpiryTime
|
||||
#define xTimerGenericCommand MPU_xTimerGenericCommand
|
||||
|
||||
/* Map standard event_group.h API functions to the MPU equivalents. */
|
||||
#define xEventGroupCreate MPU_xEventGroupCreate
|
||||
#define xEventGroupCreateStatic MPU_xEventGroupCreateStatic
|
||||
#define xEventGroupWaitBits MPU_xEventGroupWaitBits
|
||||
#define xEventGroupClearBits MPU_xEventGroupClearBits
|
||||
#define xEventGroupSetBits MPU_xEventGroupSetBits
|
||||
#define xEventGroupSync MPU_xEventGroupSync
|
||||
#define vEventGroupDelete MPU_vEventGroupDelete
|
||||
|
||||
/* Map standard message/stream_buffer.h API functions to the MPU
|
||||
equivalents. */
|
||||
#define xStreamBufferSend MPU_xStreamBufferSend
|
||||
#define xStreamBufferSendFromISR MPU_xStreamBufferSendFromISR
|
||||
#define xStreamBufferReceive MPU_xStreamBufferReceive
|
||||
#define xStreamBufferReceiveFromISR MPU_xStreamBufferReceiveFromISR
|
||||
#define vStreamBufferDelete MPU_vStreamBufferDelete
|
||||
#define xStreamBufferIsFull MPU_xStreamBufferIsFull
|
||||
#define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty
|
||||
#define xStreamBufferReset MPU_xStreamBufferReset
|
||||
#define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable
|
||||
#define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable
|
||||
#define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel
|
||||
#define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate
|
||||
#define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic
|
||||
|
||||
|
||||
/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
|
||||
macro so applications can place data in privileged access sections
|
||||
(useful when using statically allocated objects). */
|
||||
#define PRIVILEGED_FUNCTION
|
||||
#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
|
||||
|
||||
#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
|
||||
|
||||
/* Ensure API functions go in the privileged execution section. */
|
||||
#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
|
||||
#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
|
||||
|
||||
#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
|
||||
|
||||
#else /* portUSING_MPU_WRAPPERS */
|
||||
|
||||
#define PRIVILEGED_FUNCTION
|
||||
#define PRIVILEGED_DATA
|
||||
#define portUSING_MPU_WRAPPERS 0
|
||||
|
||||
#endif /* portUSING_MPU_WRAPPERS */
|
||||
|
||||
|
||||
#endif /* MPU_WRAPPERS_H */
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Portable layer API. Each function must be defined for each port.
|
||||
*----------------------------------------------------------*/
|
||||
|
||||
#ifndef PORTABLE_H
|
||||
#define PORTABLE_H
|
||||
|
||||
/* Each FreeRTOS port has a unique portmacro.h header file. Originally a
|
||||
pre-processor definition was used to ensure the pre-processor found the correct
|
||||
portmacro.h file for the port being used. That scheme was deprecated in favour
|
||||
of setting the compiler's include path such that it found the correct
|
||||
portmacro.h file - removing the need for the constant and allowing the
|
||||
portmacro.h file to be located anywhere in relation to the port being used.
|
||||
Purely for reasons of backward compatibility the old method is still valid, but
|
||||
to make it clear that new projects should not use it, support for the port
|
||||
specific constants has been moved into the deprecated_definitions.h header
|
||||
file. */
|
||||
|
||||
/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
|
||||
did not result in a portmacro.h header file being included - and it should be
|
||||
included here. In this case the path to the correct portmacro.h header file
|
||||
must be set in the compiler's include path. */
|
||||
#ifndef portENTER_CRITICAL
|
||||
#include "portmacro.h"
|
||||
#endif
|
||||
|
||||
#if portBYTE_ALIGNMENT == 32
|
||||
#define portBYTE_ALIGNMENT_MASK ( 0x001f )
|
||||
#endif
|
||||
|
||||
#if portBYTE_ALIGNMENT == 16
|
||||
#define portBYTE_ALIGNMENT_MASK ( 0x000f )
|
||||
#endif
|
||||
|
||||
#if portBYTE_ALIGNMENT == 8
|
||||
#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
|
||||
#endif
|
||||
|
||||
#if portBYTE_ALIGNMENT == 4
|
||||
#define portBYTE_ALIGNMENT_MASK ( 0x0003 )
|
||||
#endif
|
||||
|
||||
#if portBYTE_ALIGNMENT == 2
|
||||
#define portBYTE_ALIGNMENT_MASK ( 0x0001 )
|
||||
#endif
|
||||
|
||||
#if portBYTE_ALIGNMENT == 1
|
||||
#define portBYTE_ALIGNMENT_MASK ( 0x0000 )
|
||||
#endif
|
||||
|
||||
#ifndef portBYTE_ALIGNMENT_MASK
|
||||
#error "Invalid portBYTE_ALIGNMENT definition"
|
||||
#endif
|
||||
|
||||
#ifndef portNUM_CONFIGURABLE_REGIONS
|
||||
#define portNUM_CONFIGURABLE_REGIONS 1
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "mpu_wrappers.h"
|
||||
|
||||
/*
|
||||
* Setup the stack of a new task so it is ready to be placed under the
|
||||
* scheduler control. The registers have to be placed on the stack in
|
||||
* the order that the port expects to find them.
|
||||
*
|
||||
*/
|
||||
#if( portUSING_MPU_WRAPPERS == 1 )
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
|
||||
#else
|
||||
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
|
||||
#endif
|
||||
|
||||
/* Used by heap_5.c. */
|
||||
typedef struct HeapRegion
|
||||
{
|
||||
uint8_t *pucStartAddress;
|
||||
size_t xSizeInBytes;
|
||||
} HeapRegion_t;
|
||||
|
||||
/*
|
||||
* Used to define multiple heap regions for use by heap_5.c. This function
|
||||
* must be called before any calls to pvPortMalloc() - not creating a task,
|
||||
* queue, semaphore, mutex, software timer, event group, etc. will result in
|
||||
* pvPortMalloc being called.
|
||||
*
|
||||
* pxHeapRegions passes in an array of HeapRegion_t structures - each of which
|
||||
* defines a region of memory that can be used as the heap. The array is
|
||||
* terminated by a HeapRegions_t structure that has a size of 0. The region
|
||||
* with the lowest start address must appear first in the array.
|
||||
*/
|
||||
void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
|
||||
|
||||
|
||||
/*
|
||||
* Map to the memory management routines required for the port.
|
||||
*/
|
||||
void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
|
||||
void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
|
||||
void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
|
||||
size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
|
||||
size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* Setup the hardware ready for the scheduler to take control. This generally
|
||||
* sets up a tick interrupt and sets timers for the correct tick frequency.
|
||||
*/
|
||||
BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
|
||||
* the hardware is left in its original condition after the scheduler stops
|
||||
* executing.
|
||||
*/
|
||||
void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
|
||||
|
||||
/*
|
||||
* The structures and methods of manipulating the MPU are contained within the
|
||||
* port layer.
|
||||
*
|
||||
* Fills the xMPUSettings structure with the memory region information
|
||||
* contained in xRegions.
|
||||
*/
|
||||
#if( portUSING_MPU_WRAPPERS == 1 )
|
||||
struct xMEMORY_REGION;
|
||||
void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* PORTABLE_H */
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/* Copyright 2018 Canaan Inc.
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
/*
|
||||
* FreeRTOS Kernel V10.0.1
|
||||
* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||
* this software and associated documentation files (the "Software"), to deal in
|
||||
* the Software without restriction, including without limitation the rights to
|
||||
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||
* subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in all
|
||||
* copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* http://www.FreeRTOS.org
|
||||
* http://aws.amazon.com/freertos
|
||||
*
|
||||
* 1 tab == 4 spaces!
|
||||
*/
|
||||
|
||||
#ifndef PROJDEFS_H
|
||||
#define PROJDEFS_H
|
||||
|
||||
/*
|
||||
* Defines the prototype to which task functions must conform. Defined in this
|
||||
* file to ensure the type is known before portable.h is included.
|
||||
*/
|
||||
typedef void (*TaskFunction_t)( void * );
|
||||
|
||||
/* Converts a time in milliseconds to a time in ticks. This macro can be
|
||||
overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
|
||||
definition here is not suitable for your application. */
|
||||
#ifndef pdMS_TO_TICKS
|
||||
#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
|
||||
#endif
|
||||
|
||||
#define pdFALSE ( ( BaseType_t ) 0 )
|
||||
#define pdTRUE ( ( BaseType_t ) 1 )
|
||||
|
||||
#define pdPASS ( pdTRUE )
|
||||
#define pdFAIL ( pdFALSE )
|
||||
#define errQUEUE_EMPTY ( ( BaseType_t ) 0 )
|
||||
#define errQUEUE_FULL ( ( BaseType_t ) 0 )
|
||||
|
||||
/* FreeRTOS error definitions. */
|
||||
#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
|
||||
#define errQUEUE_BLOCKED ( -4 )
|
||||
#define errQUEUE_YIELD ( -5 )
|
||||
|
||||
/* Macros used for basic data corruption checks. */
|
||||
#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
|
||||
#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
|
||||
#endif
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
#define pdINTEGRITY_CHECK_VALUE 0x5a5a
|
||||
#else
|
||||
#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
|
||||
#endif
|
||||
|
||||
/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
|
||||
itself. */
|
||||
#define pdFREERTOS_ERRNO_NONE 0 /* No errors */
|
||||
#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */
|
||||
#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */
|
||||
#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */
|
||||
#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */
|
||||
#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */
|
||||
#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */
|
||||
#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */
|
||||
#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */
|
||||
#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */
|
||||
#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */
|
||||
#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */
|
||||
#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */
|
||||
#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */
|
||||
#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */
|
||||
#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */
|
||||
#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */
|
||||
#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */
|
||||
#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */
|
||||
#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */
|
||||
#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */
|
||||
#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */
|
||||
#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */
|
||||
#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */
|
||||
#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */
|
||||
#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */
|
||||
#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */
|
||||
#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||
#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */
|
||||
#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */
|
||||
#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */
|
||||
#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */
|
||||
#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */
|
||||
#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */
|
||||
#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */
|
||||
#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */
|
||||
#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */
|
||||
#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */
|
||||
#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */
|
||||
#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */
|
||||
|
||||
/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
|
||||
itself. */
|
||||
#define pdFREERTOS_LITTLE_ENDIAN 0
|
||||
#define pdFREERTOS_BIG_ENDIAN 1
|
||||
|
||||
/* Re-defining endian values for generic naming. */
|
||||
#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN
|
||||
#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN
|
||||
|
||||
|
||||
#endif /* PROJDEFS_H */
|
||||
|
||||
|
||||
|
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